1.\"- 2.\" Copyright (c) 2012 Robert N. M. Watson 3.\" All rights reserved. 4.\" 5.\" This software was developed by SRI International and the University of 6.\" Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237) 7.\" ("CTSRD"), as part of the DARPA CRASH research programme. 8.\" 9.\" Redistribution and use in source and binary forms, with or without 10.\" modification, are permitted provided that the following conditions 11.\" are met: 12.\" 1. Redistributions of source code must retain the above copyright 13.\" notice, this list of conditions and the following disclaimer. 14.\" 2. Redistributions in binary form must reproduce the above copyright 15.\" notice, this list of conditions and the following disclaimer in the 16.\" documentation and/or other materials provided with the distribution. 17.\" 18.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21.\" ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28.\" SUCH DAMAGE. 29.\" 30.Dd August 18, 2012 31.Dt ALTERA_JTAG_UART 4 32.Os 33.Sh NAME 34.Nm altera_jtag_uart 35.Nd driver for the Altera JTAG UART Core 36.Sh SYNOPSIS 37.Cd "device altera_jtag_uart" 38.Pp 39In 40.Pa /boot/device.hints : 41.Cd hint.altera_jtag_uart.0.at="nexus0" 42.Cd hint.altera_jtag_uart.0.maddr=0x7f000000 43.Cd hint.altera_jtag_uart.0.msize=0x40 44.Cd hint.altera_jtag_uart.0.irq=0 45.Cd hint.altera_jtag_uart.1.at="nexus0" 46.Cd hint.altera_jtag_uart.1.maddr=0x7f001000 47.Cd hint.altera_jtag_uart.1.msize=0x40 48.Sh DESCRIPTION 49The 50.Nm 51device driver provides support for the Altera JTAG UART core, which allows 52multiple UART-like streams to be carried over JTAG. 53.Nm 54allows JTAG UART streams to be attached to both the low-level console 55interface, used for direct kernel input and output, and the 56.Xr tty 4 57layer, to be used with 58.Xr ttys 5 59and 60.Xr login 1 . 61Sequential Altera JTAG UART devices will appear as 62.Li ttyu0 , 63.Li ttyu1 , 64etc. 65.Sh HARDWARE 66Altera JTAG UART devices can be connected to using Altera's 67.Pa nios2-terminal 68program, with the instance selected using the 69.Li --instance 70argument on the management host. 71.Nm 72supports JTAG UART cores with or without interrupt lines connected; if the 73.Li irq 74portion of the 75.Pa device.hints 76entry is omitted, the driver will poll rather than configure interrupts. 77.Sh SEE ALSO 78.Xr login 1 , 79.Xr tty 4 , 80.Xr ttys 5 81.Rs 82.%T Altera Embedded Peripherals IP User Guide 83.%D June 2011 84.%I Altera Corporation 85.%U http://www.altera.com/literature/ug/ug_embedded_ip.pdf 86.Re 87.Sh HISTORY 88The 89.Nm 90device driver first appeared in 91.Fx 10.0 . 92.Sh AUTHORS 93The 94.Nm 95device driver and this manual page were 96developed by SRI International and the University of Cambridge Computer 97Laboratory under DARPA/AFRL contract 98.Pq FA8750-10-C-0237 99.Pq Do CTSRD Dc , 100as part of the DARPA CRASH research programme. 101This device driver was written by 102.An Robert N. M. Watson . 103.Sh BUGS 104.Nm 105must dynamically poll to detect when JTAG is present, in order to disable flow 106control in the event that there is no receiving endpoint. 107Otherwise, the boot may hang waiting for the JTAG client to be attached, and 108user processes attached to JTAG UART devices might block indefinitely. 109However, there is no way to flush the output buffer once JTAG is detected to 110have disappeared; this means that a small amount of stale output data will 111remain in the output buffer, being displayed by 112.Li nios2-terminal 113when it is connected. 114Loss of JTAG will not generate a hang-up event, as that is rarely the desired 115behaviour. 116.Pp 117.Li nios2-terminal 118does not place the client-side TTY in raw mode, and so by default will not 119pass all control characters through to the UART. 120