1 /*- 2 * Copyright (c) 2003 Peter Wemm. 3 * Copyright (c) 1992 Terrence R. Lambert. 4 * Copyright (c) 1982, 1987, 1990 The Regents of the University of California. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * William Jolitz. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the University of 21 * California, Berkeley and its contributors. 22 * 4. Neither the name of the University nor the names of its contributors 23 * may be used to endorse or promote products derived from this software 24 * without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 29 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 36 * SUCH DAMAGE. 37 * 38 * from: @(#)machdep.c 7.4 (Berkeley) 6/3/91 39 */ 40 41 #include <sys/cdefs.h> 42 __FBSDID("$FreeBSD$"); 43 44 #include "opt_atalk.h" 45 #include "opt_atpic.h" 46 #include "opt_compat.h" 47 #include "opt_cpu.h" 48 #include "opt_ddb.h" 49 #include "opt_inet.h" 50 #include "opt_ipx.h" 51 #include "opt_isa.h" 52 #include "opt_kstack_pages.h" 53 #include "opt_maxmem.h" 54 #include "opt_mp_watchdog.h" 55 #include "opt_perfmon.h" 56 #include "opt_platform.h" 57 #include "opt_sched.h" 58 #include "opt_kdtrace.h" 59 60 #include <sys/param.h> 61 #include <sys/proc.h> 62 #include <sys/systm.h> 63 #include <sys/bio.h> 64 #include <sys/buf.h> 65 #include <sys/bus.h> 66 #include <sys/callout.h> 67 #include <sys/cons.h> 68 #include <sys/cpu.h> 69 #include <sys/eventhandler.h> 70 #include <sys/exec.h> 71 #include <sys/imgact.h> 72 #include <sys/kdb.h> 73 #include <sys/kernel.h> 74 #include <sys/ktr.h> 75 #include <sys/linker.h> 76 #include <sys/lock.h> 77 #include <sys/malloc.h> 78 #include <sys/memrange.h> 79 #include <sys/msgbuf.h> 80 #include <sys/mutex.h> 81 #include <sys/pcpu.h> 82 #include <sys/ptrace.h> 83 #include <sys/reboot.h> 84 #include <sys/rwlock.h> 85 #include <sys/sched.h> 86 #include <sys/signalvar.h> 87 #ifdef SMP 88 #include <sys/smp.h> 89 #endif 90 #include <sys/syscallsubr.h> 91 #include <sys/sysctl.h> 92 #include <sys/sysent.h> 93 #include <sys/sysproto.h> 94 #include <sys/ucontext.h> 95 #include <sys/vmmeter.h> 96 97 #include <vm/vm.h> 98 #include <vm/vm_extern.h> 99 #include <vm/vm_kern.h> 100 #include <vm/vm_page.h> 101 #include <vm/vm_map.h> 102 #include <vm/vm_object.h> 103 #include <vm/vm_pager.h> 104 #include <vm/vm_param.h> 105 106 #ifdef DDB 107 #ifndef KDB 108 #error KDB must be enabled in order for DDB to work! 109 #endif 110 #include <ddb/ddb.h> 111 #include <ddb/db_sym.h> 112 #endif 113 114 #include <net/netisr.h> 115 116 #include <machine/clock.h> 117 #include <machine/cpu.h> 118 #include <machine/cputypes.h> 119 #include <machine/intr_machdep.h> 120 #include <x86/mca.h> 121 #include <machine/md_var.h> 122 #include <machine/metadata.h> 123 #include <machine/mp_watchdog.h> 124 #include <machine/pc/bios.h> 125 #include <machine/pcb.h> 126 #include <machine/proc.h> 127 #include <machine/reg.h> 128 #include <machine/sigframe.h> 129 #include <machine/specialreg.h> 130 #ifdef PERFMON 131 #include <machine/perfmon.h> 132 #endif 133 #include <machine/tss.h> 134 #ifdef SMP 135 #include <machine/smp.h> 136 #endif 137 #ifdef FDT 138 #include <x86/fdt.h> 139 #endif 140 141 #ifdef DEV_ATPIC 142 #include <x86/isa/icu.h> 143 #else 144 #include <machine/apicvar.h> 145 #endif 146 147 #include <isa/isareg.h> 148 #include <isa/rtc.h> 149 150 /* Sanity check for __curthread() */ 151 CTASSERT(offsetof(struct pcpu, pc_curthread) == 0); 152 153 extern u_int64_t hammer_time(u_int64_t, u_int64_t); 154 155 extern void printcpuinfo(void); /* XXX header file */ 156 extern void identify_cpu(void); 157 extern void panicifcpuunsupported(void); 158 159 #define CS_SECURE(cs) (ISPL(cs) == SEL_UPL) 160 #define EFL_SECURE(ef, oef) ((((ef) ^ (oef)) & ~PSL_USERCHANGE) == 0) 161 162 static void cpu_startup(void *); 163 static void get_fpcontext(struct thread *td, mcontext_t *mcp, 164 char *xfpusave, size_t xfpusave_len); 165 static int set_fpcontext(struct thread *td, const mcontext_t *mcp, 166 char *xfpustate, size_t xfpustate_len); 167 SYSINIT(cpu, SI_SUB_CPU, SI_ORDER_FIRST, cpu_startup, NULL); 168 169 /* 170 * The file "conf/ldscript.amd64" defines the symbol "kernphys". Its value is 171 * the physical address at which the kernel is loaded. 172 */ 173 extern char kernphys[]; 174 #ifdef DDB 175 extern vm_offset_t ksym_start, ksym_end; 176 #endif 177 178 struct msgbuf *msgbufp; 179 180 /* Intel ICH registers */ 181 #define ICH_PMBASE 0x400 182 #define ICH_SMI_EN ICH_PMBASE + 0x30 183 184 int _udatasel, _ucodesel, _ucode32sel, _ufssel, _ugssel; 185 186 int cold = 1; 187 188 long Maxmem = 0; 189 long realmem = 0; 190 191 /* 192 * The number of PHYSMAP entries must be one less than the number of 193 * PHYSSEG entries because the PHYSMAP entry that spans the largest 194 * physical address that is accessible by ISA DMA is split into two 195 * PHYSSEG entries. 196 */ 197 #define PHYSMAP_SIZE (2 * (VM_PHYSSEG_MAX - 1)) 198 199 vm_paddr_t phys_avail[PHYSMAP_SIZE + 2]; 200 vm_paddr_t dump_avail[PHYSMAP_SIZE + 2]; 201 202 /* must be 2 less so 0 0 can signal end of chunks */ 203 #define PHYS_AVAIL_ARRAY_END ((sizeof(phys_avail) / sizeof(phys_avail[0])) - 2) 204 #define DUMP_AVAIL_ARRAY_END ((sizeof(dump_avail) / sizeof(dump_avail[0])) - 2) 205 206 struct kva_md_info kmi; 207 208 static struct trapframe proc0_tf; 209 struct region_descriptor r_gdt, r_idt; 210 211 struct pcpu __pcpu[MAXCPU]; 212 213 struct mtx icu_lock; 214 215 struct mem_range_softc mem_range_softc; 216 217 struct mtx dt_lock; /* lock for GDT and LDT */ 218 219 static void 220 cpu_startup(dummy) 221 void *dummy; 222 { 223 uintmax_t memsize; 224 char *sysenv; 225 226 /* 227 * On MacBooks, we need to disallow the legacy USB circuit to 228 * generate an SMI# because this can cause several problems, 229 * namely: incorrect CPU frequency detection and failure to 230 * start the APs. 231 * We do this by disabling a bit in the SMI_EN (SMI Control and 232 * Enable register) of the Intel ICH LPC Interface Bridge. 233 */ 234 sysenv = getenv("smbios.system.product"); 235 if (sysenv != NULL) { 236 if (strncmp(sysenv, "MacBook1,1", 10) == 0 || 237 strncmp(sysenv, "MacBook3,1", 10) == 0 || 238 strncmp(sysenv, "MacBookPro1,1", 13) == 0 || 239 strncmp(sysenv, "MacBookPro1,2", 13) == 0 || 240 strncmp(sysenv, "MacBookPro3,1", 13) == 0 || 241 strncmp(sysenv, "Macmini1,1", 10) == 0) { 242 if (bootverbose) 243 printf("Disabling LEGACY_USB_EN bit on " 244 "Intel ICH.\n"); 245 outl(ICH_SMI_EN, inl(ICH_SMI_EN) & ~0x8); 246 } 247 freeenv(sysenv); 248 } 249 250 /* 251 * Good {morning,afternoon,evening,night}. 252 */ 253 startrtclock(); 254 printcpuinfo(); 255 panicifcpuunsupported(); 256 #ifdef PERFMON 257 perfmon_init(); 258 #endif 259 realmem = Maxmem; 260 261 /* 262 * Display physical memory if SMBIOS reports reasonable amount. 263 */ 264 memsize = 0; 265 sysenv = getenv("smbios.memory.enabled"); 266 if (sysenv != NULL) { 267 memsize = (uintmax_t)strtoul(sysenv, (char **)NULL, 10) << 10; 268 freeenv(sysenv); 269 } 270 if (memsize < ptoa((uintmax_t)cnt.v_free_count)) 271 memsize = ptoa((uintmax_t)Maxmem); 272 printf("real memory = %ju (%ju MB)\n", memsize, memsize >> 20); 273 274 /* 275 * Display any holes after the first chunk of extended memory. 276 */ 277 if (bootverbose) { 278 int indx; 279 280 printf("Physical memory chunk(s):\n"); 281 for (indx = 0; phys_avail[indx + 1] != 0; indx += 2) { 282 vm_paddr_t size; 283 284 size = phys_avail[indx + 1] - phys_avail[indx]; 285 printf( 286 "0x%016jx - 0x%016jx, %ju bytes (%ju pages)\n", 287 (uintmax_t)phys_avail[indx], 288 (uintmax_t)phys_avail[indx + 1] - 1, 289 (uintmax_t)size, (uintmax_t)size / PAGE_SIZE); 290 } 291 } 292 293 vm_ksubmap_init(&kmi); 294 295 printf("avail memory = %ju (%ju MB)\n", 296 ptoa((uintmax_t)cnt.v_free_count), 297 ptoa((uintmax_t)cnt.v_free_count) / 1048576); 298 299 /* 300 * Set up buffers, so they can be used to read disk labels. 301 */ 302 bufinit(); 303 vm_pager_bufferinit(); 304 305 cpu_setregs(); 306 } 307 308 /* 309 * Send an interrupt to process. 310 * 311 * Stack is set up to allow sigcode stored 312 * at top to call routine, followed by call 313 * to sigreturn routine below. After sigreturn 314 * resets the signal mask, the stack, and the 315 * frame pointer, it returns to the user 316 * specified pc, psl. 317 */ 318 void 319 sendsig(sig_t catcher, ksiginfo_t *ksi, sigset_t *mask) 320 { 321 struct sigframe sf, *sfp; 322 struct pcb *pcb; 323 struct proc *p; 324 struct thread *td; 325 struct sigacts *psp; 326 char *sp; 327 struct trapframe *regs; 328 char *xfpusave; 329 size_t xfpusave_len; 330 int sig; 331 int oonstack; 332 333 td = curthread; 334 pcb = td->td_pcb; 335 p = td->td_proc; 336 PROC_LOCK_ASSERT(p, MA_OWNED); 337 sig = ksi->ksi_signo; 338 psp = p->p_sigacts; 339 mtx_assert(&psp->ps_mtx, MA_OWNED); 340 regs = td->td_frame; 341 oonstack = sigonstack(regs->tf_rsp); 342 343 if (cpu_max_ext_state_size > sizeof(struct savefpu) && use_xsave) { 344 xfpusave_len = cpu_max_ext_state_size - sizeof(struct savefpu); 345 xfpusave = __builtin_alloca(xfpusave_len); 346 } else { 347 xfpusave_len = 0; 348 xfpusave = NULL; 349 } 350 351 /* Save user context. */ 352 bzero(&sf, sizeof(sf)); 353 sf.sf_uc.uc_sigmask = *mask; 354 sf.sf_uc.uc_stack = td->td_sigstk; 355 sf.sf_uc.uc_stack.ss_flags = (td->td_pflags & TDP_ALTSTACK) 356 ? ((oonstack) ? SS_ONSTACK : 0) : SS_DISABLE; 357 sf.sf_uc.uc_mcontext.mc_onstack = (oonstack) ? 1 : 0; 358 bcopy(regs, &sf.sf_uc.uc_mcontext.mc_rdi, sizeof(*regs)); 359 sf.sf_uc.uc_mcontext.mc_len = sizeof(sf.sf_uc.uc_mcontext); /* magic */ 360 get_fpcontext(td, &sf.sf_uc.uc_mcontext, xfpusave, xfpusave_len); 361 fpstate_drop(td); 362 sf.sf_uc.uc_mcontext.mc_fsbase = pcb->pcb_fsbase; 363 sf.sf_uc.uc_mcontext.mc_gsbase = pcb->pcb_gsbase; 364 bzero(sf.sf_uc.uc_mcontext.mc_spare, 365 sizeof(sf.sf_uc.uc_mcontext.mc_spare)); 366 bzero(sf.sf_uc.__spare__, sizeof(sf.sf_uc.__spare__)); 367 368 /* Allocate space for the signal handler context. */ 369 if ((td->td_pflags & TDP_ALTSTACK) != 0 && !oonstack && 370 SIGISMEMBER(psp->ps_sigonstack, sig)) { 371 sp = td->td_sigstk.ss_sp + td->td_sigstk.ss_size; 372 #if defined(COMPAT_43) 373 td->td_sigstk.ss_flags |= SS_ONSTACK; 374 #endif 375 } else 376 sp = (char *)regs->tf_rsp - 128; 377 if (xfpusave != NULL) { 378 sp -= xfpusave_len; 379 sp = (char *)((unsigned long)sp & ~0x3Ful); 380 sf.sf_uc.uc_mcontext.mc_xfpustate = (register_t)sp; 381 } 382 sp -= sizeof(struct sigframe); 383 /* Align to 16 bytes. */ 384 sfp = (struct sigframe *)((unsigned long)sp & ~0xFul); 385 386 /* Translate the signal if appropriate. */ 387 if (p->p_sysent->sv_sigtbl && sig <= p->p_sysent->sv_sigsize) 388 sig = p->p_sysent->sv_sigtbl[_SIG_IDX(sig)]; 389 390 /* Build the argument list for the signal handler. */ 391 regs->tf_rdi = sig; /* arg 1 in %rdi */ 392 regs->tf_rdx = (register_t)&sfp->sf_uc; /* arg 3 in %rdx */ 393 bzero(&sf.sf_si, sizeof(sf.sf_si)); 394 if (SIGISMEMBER(psp->ps_siginfo, sig)) { 395 /* Signal handler installed with SA_SIGINFO. */ 396 regs->tf_rsi = (register_t)&sfp->sf_si; /* arg 2 in %rsi */ 397 sf.sf_ahu.sf_action = (__siginfohandler_t *)catcher; 398 399 /* Fill in POSIX parts */ 400 sf.sf_si = ksi->ksi_info; 401 sf.sf_si.si_signo = sig; /* maybe a translated signal */ 402 regs->tf_rcx = (register_t)ksi->ksi_addr; /* arg 4 in %rcx */ 403 } else { 404 /* Old FreeBSD-style arguments. */ 405 regs->tf_rsi = ksi->ksi_code; /* arg 2 in %rsi */ 406 regs->tf_rcx = (register_t)ksi->ksi_addr; /* arg 4 in %rcx */ 407 sf.sf_ahu.sf_handler = catcher; 408 } 409 mtx_unlock(&psp->ps_mtx); 410 PROC_UNLOCK(p); 411 412 /* 413 * Copy the sigframe out to the user's stack. 414 */ 415 if (copyout(&sf, sfp, sizeof(*sfp)) != 0 || 416 (xfpusave != NULL && copyout(xfpusave, 417 (void *)sf.sf_uc.uc_mcontext.mc_xfpustate, xfpusave_len) 418 != 0)) { 419 #ifdef DEBUG 420 printf("process %ld has trashed its stack\n", (long)p->p_pid); 421 #endif 422 PROC_LOCK(p); 423 sigexit(td, SIGILL); 424 } 425 426 regs->tf_rsp = (long)sfp; 427 regs->tf_rip = p->p_sysent->sv_sigcode_base; 428 regs->tf_rflags &= ~(PSL_T | PSL_D); 429 regs->tf_cs = _ucodesel; 430 regs->tf_ds = _udatasel; 431 regs->tf_es = _udatasel; 432 regs->tf_fs = _ufssel; 433 regs->tf_gs = _ugssel; 434 regs->tf_flags = TF_HASSEGS; 435 set_pcb_flags(pcb, PCB_FULL_IRET); 436 PROC_LOCK(p); 437 mtx_lock(&psp->ps_mtx); 438 } 439 440 /* 441 * System call to cleanup state after a signal 442 * has been taken. Reset signal mask and 443 * stack state from context left by sendsig (above). 444 * Return to previous pc and psl as specified by 445 * context left by sendsig. Check carefully to 446 * make sure that the user has not modified the 447 * state to gain improper privileges. 448 * 449 * MPSAFE 450 */ 451 int 452 sys_sigreturn(td, uap) 453 struct thread *td; 454 struct sigreturn_args /* { 455 const struct __ucontext *sigcntxp; 456 } */ *uap; 457 { 458 ucontext_t uc; 459 struct pcb *pcb; 460 struct proc *p; 461 struct trapframe *regs; 462 ucontext_t *ucp; 463 char *xfpustate; 464 size_t xfpustate_len; 465 long rflags; 466 int cs, error, ret; 467 ksiginfo_t ksi; 468 469 pcb = td->td_pcb; 470 p = td->td_proc; 471 472 error = copyin(uap->sigcntxp, &uc, sizeof(uc)); 473 if (error != 0) { 474 uprintf("pid %d (%s): sigreturn copyin failed\n", 475 p->p_pid, td->td_name); 476 return (error); 477 } 478 ucp = &uc; 479 if ((ucp->uc_mcontext.mc_flags & ~_MC_FLAG_MASK) != 0) { 480 uprintf("pid %d (%s): sigreturn mc_flags %x\n", p->p_pid, 481 td->td_name, ucp->uc_mcontext.mc_flags); 482 return (EINVAL); 483 } 484 regs = td->td_frame; 485 rflags = ucp->uc_mcontext.mc_rflags; 486 /* 487 * Don't allow users to change privileged or reserved flags. 488 */ 489 /* 490 * XXX do allow users to change the privileged flag PSL_RF. 491 * The cpu sets PSL_RF in tf_rflags for faults. Debuggers 492 * should sometimes set it there too. tf_rflags is kept in 493 * the signal context during signal handling and there is no 494 * other place to remember it, so the PSL_RF bit may be 495 * corrupted by the signal handler without us knowing. 496 * Corruption of the PSL_RF bit at worst causes one more or 497 * one less debugger trap, so allowing it is fairly harmless. 498 */ 499 if (!EFL_SECURE(rflags & ~PSL_RF, regs->tf_rflags & ~PSL_RF)) { 500 uprintf("pid %d (%s): sigreturn rflags = 0x%lx\n", p->p_pid, 501 td->td_name, rflags); 502 return (EINVAL); 503 } 504 505 /* 506 * Don't allow users to load a valid privileged %cs. Let the 507 * hardware check for invalid selectors, excess privilege in 508 * other selectors, invalid %eip's and invalid %esp's. 509 */ 510 cs = ucp->uc_mcontext.mc_cs; 511 if (!CS_SECURE(cs)) { 512 uprintf("pid %d (%s): sigreturn cs = 0x%x\n", p->p_pid, 513 td->td_name, cs); 514 ksiginfo_init_trap(&ksi); 515 ksi.ksi_signo = SIGBUS; 516 ksi.ksi_code = BUS_OBJERR; 517 ksi.ksi_trapno = T_PROTFLT; 518 ksi.ksi_addr = (void *)regs->tf_rip; 519 trapsignal(td, &ksi); 520 return (EINVAL); 521 } 522 523 if ((uc.uc_mcontext.mc_flags & _MC_HASFPXSTATE) != 0) { 524 xfpustate_len = uc.uc_mcontext.mc_xfpustate_len; 525 if (xfpustate_len > cpu_max_ext_state_size - 526 sizeof(struct savefpu)) { 527 uprintf("pid %d (%s): sigreturn xfpusave_len = 0x%zx\n", 528 p->p_pid, td->td_name, xfpustate_len); 529 return (EINVAL); 530 } 531 xfpustate = __builtin_alloca(xfpustate_len); 532 error = copyin((const void *)uc.uc_mcontext.mc_xfpustate, 533 xfpustate, xfpustate_len); 534 if (error != 0) { 535 uprintf( 536 "pid %d (%s): sigreturn copying xfpustate failed\n", 537 p->p_pid, td->td_name); 538 return (error); 539 } 540 } else { 541 xfpustate = NULL; 542 xfpustate_len = 0; 543 } 544 ret = set_fpcontext(td, &ucp->uc_mcontext, xfpustate, xfpustate_len); 545 if (ret != 0) { 546 uprintf("pid %d (%s): sigreturn set_fpcontext err %d\n", 547 p->p_pid, td->td_name, ret); 548 return (ret); 549 } 550 bcopy(&ucp->uc_mcontext.mc_rdi, regs, sizeof(*regs)); 551 pcb->pcb_fsbase = ucp->uc_mcontext.mc_fsbase; 552 pcb->pcb_gsbase = ucp->uc_mcontext.mc_gsbase; 553 554 #if defined(COMPAT_43) 555 if (ucp->uc_mcontext.mc_onstack & 1) 556 td->td_sigstk.ss_flags |= SS_ONSTACK; 557 else 558 td->td_sigstk.ss_flags &= ~SS_ONSTACK; 559 #endif 560 561 kern_sigprocmask(td, SIG_SETMASK, &ucp->uc_sigmask, NULL, 0); 562 set_pcb_flags(pcb, PCB_FULL_IRET); 563 return (EJUSTRETURN); 564 } 565 566 #ifdef COMPAT_FREEBSD4 567 int 568 freebsd4_sigreturn(struct thread *td, struct freebsd4_sigreturn_args *uap) 569 { 570 571 return sys_sigreturn(td, (struct sigreturn_args *)uap); 572 } 573 #endif 574 575 576 /* 577 * Machine dependent boot() routine 578 * 579 * I haven't seen anything to put here yet 580 * Possibly some stuff might be grafted back here from boot() 581 */ 582 void 583 cpu_boot(int howto) 584 { 585 } 586 587 /* 588 * Flush the D-cache for non-DMA I/O so that the I-cache can 589 * be made coherent later. 590 */ 591 void 592 cpu_flush_dcache(void *ptr, size_t len) 593 { 594 /* Not applicable */ 595 } 596 597 /* Get current clock frequency for the given cpu id. */ 598 int 599 cpu_est_clockrate(int cpu_id, uint64_t *rate) 600 { 601 uint64_t tsc1, tsc2; 602 uint64_t acnt, mcnt, perf; 603 register_t reg; 604 605 if (pcpu_find(cpu_id) == NULL || rate == NULL) 606 return (EINVAL); 607 608 /* 609 * If TSC is P-state invariant and APERF/MPERF MSRs do not exist, 610 * DELAY(9) based logic fails. 611 */ 612 if (tsc_is_invariant && !tsc_perf_stat) 613 return (EOPNOTSUPP); 614 615 #ifdef SMP 616 if (smp_cpus > 1) { 617 /* Schedule ourselves on the indicated cpu. */ 618 thread_lock(curthread); 619 sched_bind(curthread, cpu_id); 620 thread_unlock(curthread); 621 } 622 #endif 623 624 /* Calibrate by measuring a short delay. */ 625 reg = intr_disable(); 626 if (tsc_is_invariant) { 627 wrmsr(MSR_MPERF, 0); 628 wrmsr(MSR_APERF, 0); 629 tsc1 = rdtsc(); 630 DELAY(1000); 631 mcnt = rdmsr(MSR_MPERF); 632 acnt = rdmsr(MSR_APERF); 633 tsc2 = rdtsc(); 634 intr_restore(reg); 635 perf = 1000 * acnt / mcnt; 636 *rate = (tsc2 - tsc1) * perf; 637 } else { 638 tsc1 = rdtsc(); 639 DELAY(1000); 640 tsc2 = rdtsc(); 641 intr_restore(reg); 642 *rate = (tsc2 - tsc1) * 1000; 643 } 644 645 #ifdef SMP 646 if (smp_cpus > 1) { 647 thread_lock(curthread); 648 sched_unbind(curthread); 649 thread_unlock(curthread); 650 } 651 #endif 652 653 return (0); 654 } 655 656 /* 657 * Shutdown the CPU as much as possible 658 */ 659 void 660 cpu_halt(void) 661 { 662 for (;;) 663 halt(); 664 } 665 666 void (*cpu_idle_hook)(sbintime_t) = NULL; /* ACPI idle hook. */ 667 static int cpu_ident_amdc1e = 0; /* AMD C1E supported. */ 668 static int idle_mwait = 1; /* Use MONITOR/MWAIT for short idle. */ 669 TUNABLE_INT("machdep.idle_mwait", &idle_mwait); 670 SYSCTL_INT(_machdep, OID_AUTO, idle_mwait, CTLFLAG_RW, &idle_mwait, 671 0, "Use MONITOR/MWAIT for short idle"); 672 673 #define STATE_RUNNING 0x0 674 #define STATE_MWAIT 0x1 675 #define STATE_SLEEPING 0x2 676 677 static void 678 cpu_idle_acpi(sbintime_t sbt) 679 { 680 int *state; 681 682 state = (int *)PCPU_PTR(monitorbuf); 683 *state = STATE_SLEEPING; 684 685 /* See comments in cpu_idle_hlt(). */ 686 disable_intr(); 687 if (sched_runnable()) 688 enable_intr(); 689 else if (cpu_idle_hook) 690 cpu_idle_hook(sbt); 691 else 692 __asm __volatile("sti; hlt"); 693 *state = STATE_RUNNING; 694 } 695 696 static void 697 cpu_idle_hlt(sbintime_t sbt) 698 { 699 int *state; 700 701 state = (int *)PCPU_PTR(monitorbuf); 702 *state = STATE_SLEEPING; 703 704 /* 705 * Since we may be in a critical section from cpu_idle(), if 706 * an interrupt fires during that critical section we may have 707 * a pending preemption. If the CPU halts, then that thread 708 * may not execute until a later interrupt awakens the CPU. 709 * To handle this race, check for a runnable thread after 710 * disabling interrupts and immediately return if one is 711 * found. Also, we must absolutely guarentee that hlt is 712 * the next instruction after sti. This ensures that any 713 * interrupt that fires after the call to disable_intr() will 714 * immediately awaken the CPU from hlt. Finally, please note 715 * that on x86 this works fine because of interrupts enabled only 716 * after the instruction following sti takes place, while IF is set 717 * to 1 immediately, allowing hlt instruction to acknowledge the 718 * interrupt. 719 */ 720 disable_intr(); 721 if (sched_runnable()) 722 enable_intr(); 723 else 724 __asm __volatile("sti; hlt"); 725 *state = STATE_RUNNING; 726 } 727 728 /* 729 * MWAIT cpu power states. Lower 4 bits are sub-states. 730 */ 731 #define MWAIT_C0 0xf0 732 #define MWAIT_C1 0x00 733 #define MWAIT_C2 0x10 734 #define MWAIT_C3 0x20 735 #define MWAIT_C4 0x30 736 737 static void 738 cpu_idle_mwait(sbintime_t sbt) 739 { 740 int *state; 741 742 state = (int *)PCPU_PTR(monitorbuf); 743 *state = STATE_MWAIT; 744 745 /* See comments in cpu_idle_hlt(). */ 746 disable_intr(); 747 if (sched_runnable()) { 748 enable_intr(); 749 *state = STATE_RUNNING; 750 return; 751 } 752 cpu_monitor(state, 0, 0); 753 if (*state == STATE_MWAIT) 754 __asm __volatile("sti; mwait" : : "a" (MWAIT_C1), "c" (0)); 755 else 756 enable_intr(); 757 *state = STATE_RUNNING; 758 } 759 760 static void 761 cpu_idle_spin(sbintime_t sbt) 762 { 763 int *state; 764 int i; 765 766 state = (int *)PCPU_PTR(monitorbuf); 767 *state = STATE_RUNNING; 768 769 /* 770 * The sched_runnable() call is racy but as long as there is 771 * a loop missing it one time will have just a little impact if any 772 * (and it is much better than missing the check at all). 773 */ 774 for (i = 0; i < 1000; i++) { 775 if (sched_runnable()) 776 return; 777 cpu_spinwait(); 778 } 779 } 780 781 /* 782 * C1E renders the local APIC timer dead, so we disable it by 783 * reading the Interrupt Pending Message register and clearing 784 * both C1eOnCmpHalt (bit 28) and SmiOnCmpHalt (bit 27). 785 * 786 * Reference: 787 * "BIOS and Kernel Developer's Guide for AMD NPT Family 0Fh Processors" 788 * #32559 revision 3.00+ 789 */ 790 #define MSR_AMDK8_IPM 0xc0010055 791 #define AMDK8_SMIONCMPHALT (1ULL << 27) 792 #define AMDK8_C1EONCMPHALT (1ULL << 28) 793 #define AMDK8_CMPHALT (AMDK8_SMIONCMPHALT | AMDK8_C1EONCMPHALT) 794 795 static void 796 cpu_probe_amdc1e(void) 797 { 798 799 /* 800 * Detect the presence of C1E capability mostly on latest 801 * dual-cores (or future) k8 family. 802 */ 803 if (cpu_vendor_id == CPU_VENDOR_AMD && 804 (cpu_id & 0x00000f00) == 0x00000f00 && 805 (cpu_id & 0x0fff0000) >= 0x00040000) { 806 cpu_ident_amdc1e = 1; 807 } 808 } 809 810 void (*cpu_idle_fn)(sbintime_t) = cpu_idle_acpi; 811 812 void 813 cpu_idle(int busy) 814 { 815 uint64_t msr; 816 sbintime_t sbt = -1; 817 818 CTR2(KTR_SPARE2, "cpu_idle(%d) at %d", 819 busy, curcpu); 820 #ifdef MP_WATCHDOG 821 ap_watchdog(PCPU_GET(cpuid)); 822 #endif 823 /* If we are busy - try to use fast methods. */ 824 if (busy) { 825 if ((cpu_feature2 & CPUID2_MON) && idle_mwait) { 826 cpu_idle_mwait(busy); 827 goto out; 828 } 829 } 830 831 /* If we have time - switch timers into idle mode. */ 832 if (!busy) { 833 critical_enter(); 834 sbt = cpu_idleclock(); 835 } 836 837 /* Apply AMD APIC timer C1E workaround. */ 838 if (cpu_ident_amdc1e && cpu_disable_deep_sleep) { 839 msr = rdmsr(MSR_AMDK8_IPM); 840 if (msr & AMDK8_CMPHALT) 841 wrmsr(MSR_AMDK8_IPM, msr & ~AMDK8_CMPHALT); 842 } 843 844 /* Call main idle method. */ 845 cpu_idle_fn(sbt); 846 847 /* Switch timers mack into active mode. */ 848 if (!busy) { 849 cpu_activeclock(); 850 critical_exit(); 851 } 852 out: 853 CTR2(KTR_SPARE2, "cpu_idle(%d) at %d done", 854 busy, curcpu); 855 } 856 857 int 858 cpu_idle_wakeup(int cpu) 859 { 860 struct pcpu *pcpu; 861 int *state; 862 863 pcpu = pcpu_find(cpu); 864 state = (int *)pcpu->pc_monitorbuf; 865 /* 866 * This doesn't need to be atomic since missing the race will 867 * simply result in unnecessary IPIs. 868 */ 869 if (*state == STATE_SLEEPING) 870 return (0); 871 if (*state == STATE_MWAIT) 872 *state = STATE_RUNNING; 873 return (1); 874 } 875 876 /* 877 * Ordered by speed/power consumption. 878 */ 879 struct { 880 void *id_fn; 881 char *id_name; 882 } idle_tbl[] = { 883 { cpu_idle_spin, "spin" }, 884 { cpu_idle_mwait, "mwait" }, 885 { cpu_idle_hlt, "hlt" }, 886 { cpu_idle_acpi, "acpi" }, 887 { NULL, NULL } 888 }; 889 890 static int 891 idle_sysctl_available(SYSCTL_HANDLER_ARGS) 892 { 893 char *avail, *p; 894 int error; 895 int i; 896 897 avail = malloc(256, M_TEMP, M_WAITOK); 898 p = avail; 899 for (i = 0; idle_tbl[i].id_name != NULL; i++) { 900 if (strstr(idle_tbl[i].id_name, "mwait") && 901 (cpu_feature2 & CPUID2_MON) == 0) 902 continue; 903 if (strcmp(idle_tbl[i].id_name, "acpi") == 0 && 904 cpu_idle_hook == NULL) 905 continue; 906 p += sprintf(p, "%s%s", p != avail ? ", " : "", 907 idle_tbl[i].id_name); 908 } 909 error = sysctl_handle_string(oidp, avail, 0, req); 910 free(avail, M_TEMP); 911 return (error); 912 } 913 914 SYSCTL_PROC(_machdep, OID_AUTO, idle_available, CTLTYPE_STRING | CTLFLAG_RD, 915 0, 0, idle_sysctl_available, "A", "list of available idle functions"); 916 917 static int 918 idle_sysctl(SYSCTL_HANDLER_ARGS) 919 { 920 char buf[16]; 921 int error; 922 char *p; 923 int i; 924 925 p = "unknown"; 926 for (i = 0; idle_tbl[i].id_name != NULL; i++) { 927 if (idle_tbl[i].id_fn == cpu_idle_fn) { 928 p = idle_tbl[i].id_name; 929 break; 930 } 931 } 932 strncpy(buf, p, sizeof(buf)); 933 error = sysctl_handle_string(oidp, buf, sizeof(buf), req); 934 if (error != 0 || req->newptr == NULL) 935 return (error); 936 for (i = 0; idle_tbl[i].id_name != NULL; i++) { 937 if (strstr(idle_tbl[i].id_name, "mwait") && 938 (cpu_feature2 & CPUID2_MON) == 0) 939 continue; 940 if (strcmp(idle_tbl[i].id_name, "acpi") == 0 && 941 cpu_idle_hook == NULL) 942 continue; 943 if (strcmp(idle_tbl[i].id_name, buf)) 944 continue; 945 cpu_idle_fn = idle_tbl[i].id_fn; 946 return (0); 947 } 948 return (EINVAL); 949 } 950 951 SYSCTL_PROC(_machdep, OID_AUTO, idle, CTLTYPE_STRING | CTLFLAG_RW, 0, 0, 952 idle_sysctl, "A", "currently selected idle function"); 953 954 /* 955 * Reset registers to default values on exec. 956 */ 957 void 958 exec_setregs(struct thread *td, struct image_params *imgp, u_long stack) 959 { 960 struct trapframe *regs = td->td_frame; 961 struct pcb *pcb = td->td_pcb; 962 963 mtx_lock(&dt_lock); 964 if (td->td_proc->p_md.md_ldt != NULL) 965 user_ldt_free(td); 966 else 967 mtx_unlock(&dt_lock); 968 969 pcb->pcb_fsbase = 0; 970 pcb->pcb_gsbase = 0; 971 clear_pcb_flags(pcb, PCB_32BIT); 972 pcb->pcb_initial_fpucw = __INITIAL_FPUCW__; 973 set_pcb_flags(pcb, PCB_FULL_IRET); 974 975 bzero((char *)regs, sizeof(struct trapframe)); 976 regs->tf_rip = imgp->entry_addr; 977 regs->tf_rsp = ((stack - 8) & ~0xFul) + 8; 978 regs->tf_rdi = stack; /* argv */ 979 regs->tf_rflags = PSL_USER | (regs->tf_rflags & PSL_T); 980 regs->tf_ss = _udatasel; 981 regs->tf_cs = _ucodesel; 982 regs->tf_ds = _udatasel; 983 regs->tf_es = _udatasel; 984 regs->tf_fs = _ufssel; 985 regs->tf_gs = _ugssel; 986 regs->tf_flags = TF_HASSEGS; 987 td->td_retval[1] = 0; 988 989 /* 990 * Reset the hardware debug registers if they were in use. 991 * They won't have any meaning for the newly exec'd process. 992 */ 993 if (pcb->pcb_flags & PCB_DBREGS) { 994 pcb->pcb_dr0 = 0; 995 pcb->pcb_dr1 = 0; 996 pcb->pcb_dr2 = 0; 997 pcb->pcb_dr3 = 0; 998 pcb->pcb_dr6 = 0; 999 pcb->pcb_dr7 = 0; 1000 if (pcb == curpcb) { 1001 /* 1002 * Clear the debug registers on the running 1003 * CPU, otherwise they will end up affecting 1004 * the next process we switch to. 1005 */ 1006 reset_dbregs(); 1007 } 1008 clear_pcb_flags(pcb, PCB_DBREGS); 1009 } 1010 1011 /* 1012 * Drop the FP state if we hold it, so that the process gets a 1013 * clean FP state if it uses the FPU again. 1014 */ 1015 fpstate_drop(td); 1016 } 1017 1018 void 1019 cpu_setregs(void) 1020 { 1021 register_t cr0; 1022 1023 cr0 = rcr0(); 1024 /* 1025 * CR0_MP, CR0_NE and CR0_TS are also set by npx_probe() for the 1026 * BSP. See the comments there about why we set them. 1027 */ 1028 cr0 |= CR0_MP | CR0_NE | CR0_TS | CR0_WP | CR0_AM; 1029 load_cr0(cr0); 1030 } 1031 1032 /* 1033 * Initialize amd64 and configure to run kernel 1034 */ 1035 1036 /* 1037 * Initialize segments & interrupt table 1038 */ 1039 1040 struct user_segment_descriptor gdt[NGDT * MAXCPU];/* global descriptor tables */ 1041 static struct gate_descriptor idt0[NIDT]; 1042 struct gate_descriptor *idt = &idt0[0]; /* interrupt descriptor table */ 1043 1044 static char dblfault_stack[PAGE_SIZE] __aligned(16); 1045 1046 static char nmi0_stack[PAGE_SIZE] __aligned(16); 1047 CTASSERT(sizeof(struct nmi_pcpu) == 16); 1048 1049 struct amd64tss common_tss[MAXCPU]; 1050 1051 /* 1052 * Software prototypes -- in more palatable form. 1053 * 1054 * Keep GUFS32, GUGS32, GUCODE32 and GUDATA at the same 1055 * slots as corresponding segments for i386 kernel. 1056 */ 1057 struct soft_segment_descriptor gdt_segs[] = { 1058 /* GNULL_SEL 0 Null Descriptor */ 1059 { .ssd_base = 0x0, 1060 .ssd_limit = 0x0, 1061 .ssd_type = 0, 1062 .ssd_dpl = 0, 1063 .ssd_p = 0, 1064 .ssd_long = 0, 1065 .ssd_def32 = 0, 1066 .ssd_gran = 0 }, 1067 /* GNULL2_SEL 1 Null Descriptor */ 1068 { .ssd_base = 0x0, 1069 .ssd_limit = 0x0, 1070 .ssd_type = 0, 1071 .ssd_dpl = 0, 1072 .ssd_p = 0, 1073 .ssd_long = 0, 1074 .ssd_def32 = 0, 1075 .ssd_gran = 0 }, 1076 /* GUFS32_SEL 2 32 bit %gs Descriptor for user */ 1077 { .ssd_base = 0x0, 1078 .ssd_limit = 0xfffff, 1079 .ssd_type = SDT_MEMRWA, 1080 .ssd_dpl = SEL_UPL, 1081 .ssd_p = 1, 1082 .ssd_long = 0, 1083 .ssd_def32 = 1, 1084 .ssd_gran = 1 }, 1085 /* GUGS32_SEL 3 32 bit %fs Descriptor for user */ 1086 { .ssd_base = 0x0, 1087 .ssd_limit = 0xfffff, 1088 .ssd_type = SDT_MEMRWA, 1089 .ssd_dpl = SEL_UPL, 1090 .ssd_p = 1, 1091 .ssd_long = 0, 1092 .ssd_def32 = 1, 1093 .ssd_gran = 1 }, 1094 /* GCODE_SEL 4 Code Descriptor for kernel */ 1095 { .ssd_base = 0x0, 1096 .ssd_limit = 0xfffff, 1097 .ssd_type = SDT_MEMERA, 1098 .ssd_dpl = SEL_KPL, 1099 .ssd_p = 1, 1100 .ssd_long = 1, 1101 .ssd_def32 = 0, 1102 .ssd_gran = 1 }, 1103 /* GDATA_SEL 5 Data Descriptor for kernel */ 1104 { .ssd_base = 0x0, 1105 .ssd_limit = 0xfffff, 1106 .ssd_type = SDT_MEMRWA, 1107 .ssd_dpl = SEL_KPL, 1108 .ssd_p = 1, 1109 .ssd_long = 1, 1110 .ssd_def32 = 0, 1111 .ssd_gran = 1 }, 1112 /* GUCODE32_SEL 6 32 bit Code Descriptor for user */ 1113 { .ssd_base = 0x0, 1114 .ssd_limit = 0xfffff, 1115 .ssd_type = SDT_MEMERA, 1116 .ssd_dpl = SEL_UPL, 1117 .ssd_p = 1, 1118 .ssd_long = 0, 1119 .ssd_def32 = 1, 1120 .ssd_gran = 1 }, 1121 /* GUDATA_SEL 7 32/64 bit Data Descriptor for user */ 1122 { .ssd_base = 0x0, 1123 .ssd_limit = 0xfffff, 1124 .ssd_type = SDT_MEMRWA, 1125 .ssd_dpl = SEL_UPL, 1126 .ssd_p = 1, 1127 .ssd_long = 0, 1128 .ssd_def32 = 1, 1129 .ssd_gran = 1 }, 1130 /* GUCODE_SEL 8 64 bit Code Descriptor for user */ 1131 { .ssd_base = 0x0, 1132 .ssd_limit = 0xfffff, 1133 .ssd_type = SDT_MEMERA, 1134 .ssd_dpl = SEL_UPL, 1135 .ssd_p = 1, 1136 .ssd_long = 1, 1137 .ssd_def32 = 0, 1138 .ssd_gran = 1 }, 1139 /* GPROC0_SEL 9 Proc 0 Tss Descriptor */ 1140 { .ssd_base = 0x0, 1141 .ssd_limit = sizeof(struct amd64tss) + IOPAGES * PAGE_SIZE - 1, 1142 .ssd_type = SDT_SYSTSS, 1143 .ssd_dpl = SEL_KPL, 1144 .ssd_p = 1, 1145 .ssd_long = 0, 1146 .ssd_def32 = 0, 1147 .ssd_gran = 0 }, 1148 /* Actually, the TSS is a system descriptor which is double size */ 1149 { .ssd_base = 0x0, 1150 .ssd_limit = 0x0, 1151 .ssd_type = 0, 1152 .ssd_dpl = 0, 1153 .ssd_p = 0, 1154 .ssd_long = 0, 1155 .ssd_def32 = 0, 1156 .ssd_gran = 0 }, 1157 /* GUSERLDT_SEL 11 LDT Descriptor */ 1158 { .ssd_base = 0x0, 1159 .ssd_limit = 0x0, 1160 .ssd_type = 0, 1161 .ssd_dpl = 0, 1162 .ssd_p = 0, 1163 .ssd_long = 0, 1164 .ssd_def32 = 0, 1165 .ssd_gran = 0 }, 1166 /* GUSERLDT_SEL 12 LDT Descriptor, double size */ 1167 { .ssd_base = 0x0, 1168 .ssd_limit = 0x0, 1169 .ssd_type = 0, 1170 .ssd_dpl = 0, 1171 .ssd_p = 0, 1172 .ssd_long = 0, 1173 .ssd_def32 = 0, 1174 .ssd_gran = 0 }, 1175 }; 1176 1177 void 1178 setidt(idx, func, typ, dpl, ist) 1179 int idx; 1180 inthand_t *func; 1181 int typ; 1182 int dpl; 1183 int ist; 1184 { 1185 struct gate_descriptor *ip; 1186 1187 ip = idt + idx; 1188 ip->gd_looffset = (uintptr_t)func; 1189 ip->gd_selector = GSEL(GCODE_SEL, SEL_KPL); 1190 ip->gd_ist = ist; 1191 ip->gd_xx = 0; 1192 ip->gd_type = typ; 1193 ip->gd_dpl = dpl; 1194 ip->gd_p = 1; 1195 ip->gd_hioffset = ((uintptr_t)func)>>16 ; 1196 } 1197 1198 extern inthand_t 1199 IDTVEC(div), IDTVEC(dbg), IDTVEC(nmi), IDTVEC(bpt), IDTVEC(ofl), 1200 IDTVEC(bnd), IDTVEC(ill), IDTVEC(dna), IDTVEC(fpusegm), 1201 IDTVEC(tss), IDTVEC(missing), IDTVEC(stk), IDTVEC(prot), 1202 IDTVEC(page), IDTVEC(mchk), IDTVEC(rsvd), IDTVEC(fpu), IDTVEC(align), 1203 IDTVEC(xmm), IDTVEC(dblfault), 1204 #ifdef KDTRACE_HOOKS 1205 IDTVEC(dtrace_ret), 1206 #endif 1207 IDTVEC(fast_syscall), IDTVEC(fast_syscall32); 1208 1209 #ifdef DDB 1210 /* 1211 * Display the index and function name of any IDT entries that don't use 1212 * the default 'rsvd' entry point. 1213 */ 1214 DB_SHOW_COMMAND(idt, db_show_idt) 1215 { 1216 struct gate_descriptor *ip; 1217 int idx; 1218 uintptr_t func; 1219 1220 ip = idt; 1221 for (idx = 0; idx < NIDT && !db_pager_quit; idx++) { 1222 func = ((long)ip->gd_hioffset << 16 | ip->gd_looffset); 1223 if (func != (uintptr_t)&IDTVEC(rsvd)) { 1224 db_printf("%3d\t", idx); 1225 db_printsym(func, DB_STGY_PROC); 1226 db_printf("\n"); 1227 } 1228 ip++; 1229 } 1230 } 1231 #endif 1232 1233 void 1234 sdtossd(sd, ssd) 1235 struct user_segment_descriptor *sd; 1236 struct soft_segment_descriptor *ssd; 1237 { 1238 1239 ssd->ssd_base = (sd->sd_hibase << 24) | sd->sd_lobase; 1240 ssd->ssd_limit = (sd->sd_hilimit << 16) | sd->sd_lolimit; 1241 ssd->ssd_type = sd->sd_type; 1242 ssd->ssd_dpl = sd->sd_dpl; 1243 ssd->ssd_p = sd->sd_p; 1244 ssd->ssd_long = sd->sd_long; 1245 ssd->ssd_def32 = sd->sd_def32; 1246 ssd->ssd_gran = sd->sd_gran; 1247 } 1248 1249 void 1250 ssdtosd(ssd, sd) 1251 struct soft_segment_descriptor *ssd; 1252 struct user_segment_descriptor *sd; 1253 { 1254 1255 sd->sd_lobase = (ssd->ssd_base) & 0xffffff; 1256 sd->sd_hibase = (ssd->ssd_base >> 24) & 0xff; 1257 sd->sd_lolimit = (ssd->ssd_limit) & 0xffff; 1258 sd->sd_hilimit = (ssd->ssd_limit >> 16) & 0xf; 1259 sd->sd_type = ssd->ssd_type; 1260 sd->sd_dpl = ssd->ssd_dpl; 1261 sd->sd_p = ssd->ssd_p; 1262 sd->sd_long = ssd->ssd_long; 1263 sd->sd_def32 = ssd->ssd_def32; 1264 sd->sd_gran = ssd->ssd_gran; 1265 } 1266 1267 void 1268 ssdtosyssd(ssd, sd) 1269 struct soft_segment_descriptor *ssd; 1270 struct system_segment_descriptor *sd; 1271 { 1272 1273 sd->sd_lobase = (ssd->ssd_base) & 0xffffff; 1274 sd->sd_hibase = (ssd->ssd_base >> 24) & 0xfffffffffful; 1275 sd->sd_lolimit = (ssd->ssd_limit) & 0xffff; 1276 sd->sd_hilimit = (ssd->ssd_limit >> 16) & 0xf; 1277 sd->sd_type = ssd->ssd_type; 1278 sd->sd_dpl = ssd->ssd_dpl; 1279 sd->sd_p = ssd->ssd_p; 1280 sd->sd_gran = ssd->ssd_gran; 1281 } 1282 1283 #if !defined(DEV_ATPIC) && defined(DEV_ISA) 1284 #include <isa/isavar.h> 1285 #include <isa/isareg.h> 1286 /* 1287 * Return a bitmap of the current interrupt requests. This is 8259-specific 1288 * and is only suitable for use at probe time. 1289 * This is only here to pacify sio. It is NOT FATAL if this doesn't work. 1290 * It shouldn't be here. There should probably be an APIC centric 1291 * implementation in the apic driver code, if at all. 1292 */ 1293 intrmask_t 1294 isa_irq_pending(void) 1295 { 1296 u_char irr1; 1297 u_char irr2; 1298 1299 irr1 = inb(IO_ICU1); 1300 irr2 = inb(IO_ICU2); 1301 return ((irr2 << 8) | irr1); 1302 } 1303 #endif 1304 1305 u_int basemem; 1306 1307 static int 1308 add_smap_entry(struct bios_smap *smap, vm_paddr_t *physmap, int *physmap_idxp) 1309 { 1310 int i, insert_idx, physmap_idx; 1311 1312 physmap_idx = *physmap_idxp; 1313 1314 if (boothowto & RB_VERBOSE) 1315 printf("SMAP type=%02x base=%016lx len=%016lx\n", 1316 smap->type, smap->base, smap->length); 1317 1318 if (smap->type != SMAP_TYPE_MEMORY) 1319 return (1); 1320 1321 if (smap->length == 0) 1322 return (0); 1323 1324 /* 1325 * Find insertion point while checking for overlap. Start off by 1326 * assuming the new entry will be added to the end. 1327 */ 1328 insert_idx = physmap_idx + 2; 1329 for (i = 0; i <= physmap_idx; i += 2) { 1330 if (smap->base < physmap[i + 1]) { 1331 if (smap->base + smap->length <= physmap[i]) { 1332 insert_idx = i; 1333 break; 1334 } 1335 if (boothowto & RB_VERBOSE) 1336 printf( 1337 "Overlapping memory regions, ignoring second region\n"); 1338 return (1); 1339 } 1340 } 1341 1342 /* See if we can prepend to the next entry. */ 1343 if (insert_idx <= physmap_idx && 1344 smap->base + smap->length == physmap[insert_idx]) { 1345 physmap[insert_idx] = smap->base; 1346 return (1); 1347 } 1348 1349 /* See if we can append to the previous entry. */ 1350 if (insert_idx > 0 && smap->base == physmap[insert_idx - 1]) { 1351 physmap[insert_idx - 1] += smap->length; 1352 return (1); 1353 } 1354 1355 physmap_idx += 2; 1356 *physmap_idxp = physmap_idx; 1357 if (physmap_idx == PHYSMAP_SIZE) { 1358 printf( 1359 "Too many segments in the physical address map, giving up\n"); 1360 return (0); 1361 } 1362 1363 /* 1364 * Move the last 'N' entries down to make room for the new 1365 * entry if needed. 1366 */ 1367 for (i = physmap_idx; i > insert_idx; i -= 2) { 1368 physmap[i] = physmap[i - 2]; 1369 physmap[i + 1] = physmap[i - 1]; 1370 } 1371 1372 /* Insert the new entry. */ 1373 physmap[insert_idx] = smap->base; 1374 physmap[insert_idx + 1] = smap->base + smap->length; 1375 return (1); 1376 } 1377 1378 /* 1379 * Populate the (physmap) array with base/bound pairs describing the 1380 * available physical memory in the system, then test this memory and 1381 * build the phys_avail array describing the actually-available memory. 1382 * 1383 * Total memory size may be set by the kernel environment variable 1384 * hw.physmem or the compile-time define MAXMEM. 1385 * 1386 * XXX first should be vm_paddr_t. 1387 */ 1388 static void 1389 getmemsize(caddr_t kmdp, u_int64_t first) 1390 { 1391 int i, physmap_idx, pa_indx, da_indx; 1392 vm_paddr_t pa, physmap[PHYSMAP_SIZE]; 1393 u_long physmem_start, physmem_tunable, memtest; 1394 pt_entry_t *pte; 1395 struct bios_smap *smapbase, *smap, *smapend; 1396 u_int32_t smapsize; 1397 quad_t dcons_addr, dcons_size; 1398 1399 bzero(physmap, sizeof(physmap)); 1400 basemem = 0; 1401 physmap_idx = 0; 1402 1403 /* 1404 * get memory map from INT 15:E820, kindly supplied by the loader. 1405 * 1406 * subr_module.c says: 1407 * "Consumer may safely assume that size value precedes data." 1408 * ie: an int32_t immediately precedes smap. 1409 */ 1410 smapbase = (struct bios_smap *)preload_search_info(kmdp, 1411 MODINFO_METADATA | MODINFOMD_SMAP); 1412 if (smapbase == NULL) 1413 panic("No BIOS smap info from loader!"); 1414 1415 smapsize = *((u_int32_t *)smapbase - 1); 1416 smapend = (struct bios_smap *)((uintptr_t)smapbase + smapsize); 1417 1418 for (smap = smapbase; smap < smapend; smap++) 1419 if (!add_smap_entry(smap, physmap, &physmap_idx)) 1420 break; 1421 1422 /* 1423 * Find the 'base memory' segment for SMP 1424 */ 1425 basemem = 0; 1426 for (i = 0; i <= physmap_idx; i += 2) { 1427 if (physmap[i] == 0x00000000) { 1428 basemem = physmap[i + 1] / 1024; 1429 break; 1430 } 1431 } 1432 if (basemem == 0) 1433 panic("BIOS smap did not include a basemem segment!"); 1434 1435 #ifdef SMP 1436 /* make hole for AP bootstrap code */ 1437 physmap[1] = mp_bootaddress(physmap[1] / 1024); 1438 #endif 1439 1440 /* 1441 * Maxmem isn't the "maximum memory", it's one larger than the 1442 * highest page of the physical address space. It should be 1443 * called something like "Maxphyspage". We may adjust this 1444 * based on ``hw.physmem'' and the results of the memory test. 1445 */ 1446 Maxmem = atop(physmap[physmap_idx + 1]); 1447 1448 #ifdef MAXMEM 1449 Maxmem = MAXMEM / 4; 1450 #endif 1451 1452 if (TUNABLE_ULONG_FETCH("hw.physmem", &physmem_tunable)) 1453 Maxmem = atop(physmem_tunable); 1454 1455 /* 1456 * By default enable the memory test on real hardware, and disable 1457 * it if we appear to be running in a VM. This avoids touching all 1458 * pages unnecessarily, which doesn't matter on real hardware but is 1459 * bad for shared VM hosts. Use a general name so that 1460 * one could eventually do more with the code than just disable it. 1461 */ 1462 memtest = (vm_guest > VM_GUEST_NO) ? 0 : 1; 1463 TUNABLE_ULONG_FETCH("hw.memtest.tests", &memtest); 1464 1465 /* 1466 * Don't allow MAXMEM or hw.physmem to extend the amount of memory 1467 * in the system. 1468 */ 1469 if (Maxmem > atop(physmap[physmap_idx + 1])) 1470 Maxmem = atop(physmap[physmap_idx + 1]); 1471 1472 if (atop(physmap[physmap_idx + 1]) != Maxmem && 1473 (boothowto & RB_VERBOSE)) 1474 printf("Physical memory use set to %ldK\n", Maxmem * 4); 1475 1476 /* call pmap initialization to make new kernel address space */ 1477 pmap_bootstrap(&first); 1478 1479 /* 1480 * Size up each available chunk of physical memory. 1481 * 1482 * XXX Some BIOSes corrupt low 64KB between suspend and resume. 1483 * By default, mask off the first 16 pages unless we appear to be 1484 * running in a VM. 1485 */ 1486 physmem_start = (vm_guest > VM_GUEST_NO ? 1 : 16) << PAGE_SHIFT; 1487 TUNABLE_ULONG_FETCH("hw.physmem.start", &physmem_start); 1488 if (physmem_start < PAGE_SIZE) 1489 physmap[0] = PAGE_SIZE; 1490 else if (physmem_start >= physmap[1]) 1491 physmap[0] = round_page(physmap[1] - PAGE_SIZE); 1492 else 1493 physmap[0] = round_page(physmem_start); 1494 pa_indx = 0; 1495 da_indx = 1; 1496 phys_avail[pa_indx++] = physmap[0]; 1497 phys_avail[pa_indx] = physmap[0]; 1498 dump_avail[da_indx] = physmap[0]; 1499 pte = CMAP1; 1500 1501 /* 1502 * Get dcons buffer address 1503 */ 1504 if (getenv_quad("dcons.addr", &dcons_addr) == 0 || 1505 getenv_quad("dcons.size", &dcons_size) == 0) 1506 dcons_addr = 0; 1507 1508 /* 1509 * physmap is in bytes, so when converting to page boundaries, 1510 * round up the start address and round down the end address. 1511 */ 1512 for (i = 0; i <= physmap_idx; i += 2) { 1513 vm_paddr_t end; 1514 1515 end = ptoa((vm_paddr_t)Maxmem); 1516 if (physmap[i + 1] < end) 1517 end = trunc_page(physmap[i + 1]); 1518 for (pa = round_page(physmap[i]); pa < end; pa += PAGE_SIZE) { 1519 int tmp, page_bad, full; 1520 int *ptr = (int *)CADDR1; 1521 1522 full = FALSE; 1523 /* 1524 * block out kernel memory as not available. 1525 */ 1526 if (pa >= (vm_paddr_t)kernphys && pa < first) 1527 goto do_dump_avail; 1528 1529 /* 1530 * block out dcons buffer 1531 */ 1532 if (dcons_addr > 0 1533 && pa >= trunc_page(dcons_addr) 1534 && pa < dcons_addr + dcons_size) 1535 goto do_dump_avail; 1536 1537 page_bad = FALSE; 1538 if (memtest == 0) 1539 goto skip_memtest; 1540 1541 /* 1542 * map page into kernel: valid, read/write,non-cacheable 1543 */ 1544 *pte = pa | PG_V | PG_RW | PG_N; 1545 invltlb(); 1546 1547 tmp = *(int *)ptr; 1548 /* 1549 * Test for alternating 1's and 0's 1550 */ 1551 *(volatile int *)ptr = 0xaaaaaaaa; 1552 if (*(volatile int *)ptr != 0xaaaaaaaa) 1553 page_bad = TRUE; 1554 /* 1555 * Test for alternating 0's and 1's 1556 */ 1557 *(volatile int *)ptr = 0x55555555; 1558 if (*(volatile int *)ptr != 0x55555555) 1559 page_bad = TRUE; 1560 /* 1561 * Test for all 1's 1562 */ 1563 *(volatile int *)ptr = 0xffffffff; 1564 if (*(volatile int *)ptr != 0xffffffff) 1565 page_bad = TRUE; 1566 /* 1567 * Test for all 0's 1568 */ 1569 *(volatile int *)ptr = 0x0; 1570 if (*(volatile int *)ptr != 0x0) 1571 page_bad = TRUE; 1572 /* 1573 * Restore original value. 1574 */ 1575 *(int *)ptr = tmp; 1576 1577 skip_memtest: 1578 /* 1579 * Adjust array of valid/good pages. 1580 */ 1581 if (page_bad == TRUE) 1582 continue; 1583 /* 1584 * If this good page is a continuation of the 1585 * previous set of good pages, then just increase 1586 * the end pointer. Otherwise start a new chunk. 1587 * Note that "end" points one higher than end, 1588 * making the range >= start and < end. 1589 * If we're also doing a speculative memory 1590 * test and we at or past the end, bump up Maxmem 1591 * so that we keep going. The first bad page 1592 * will terminate the loop. 1593 */ 1594 if (phys_avail[pa_indx] == pa) { 1595 phys_avail[pa_indx] += PAGE_SIZE; 1596 } else { 1597 pa_indx++; 1598 if (pa_indx == PHYS_AVAIL_ARRAY_END) { 1599 printf( 1600 "Too many holes in the physical address space, giving up\n"); 1601 pa_indx--; 1602 full = TRUE; 1603 goto do_dump_avail; 1604 } 1605 phys_avail[pa_indx++] = pa; /* start */ 1606 phys_avail[pa_indx] = pa + PAGE_SIZE; /* end */ 1607 } 1608 physmem++; 1609 do_dump_avail: 1610 if (dump_avail[da_indx] == pa) { 1611 dump_avail[da_indx] += PAGE_SIZE; 1612 } else { 1613 da_indx++; 1614 if (da_indx == DUMP_AVAIL_ARRAY_END) { 1615 da_indx--; 1616 goto do_next; 1617 } 1618 dump_avail[da_indx++] = pa; /* start */ 1619 dump_avail[da_indx] = pa + PAGE_SIZE; /* end */ 1620 } 1621 do_next: 1622 if (full) 1623 break; 1624 } 1625 } 1626 *pte = 0; 1627 invltlb(); 1628 1629 /* 1630 * XXX 1631 * The last chunk must contain at least one page plus the message 1632 * buffer to avoid complicating other code (message buffer address 1633 * calculation, etc.). 1634 */ 1635 while (phys_avail[pa_indx - 1] + PAGE_SIZE + 1636 round_page(msgbufsize) >= phys_avail[pa_indx]) { 1637 physmem -= atop(phys_avail[pa_indx] - phys_avail[pa_indx - 1]); 1638 phys_avail[pa_indx--] = 0; 1639 phys_avail[pa_indx--] = 0; 1640 } 1641 1642 Maxmem = atop(phys_avail[pa_indx]); 1643 1644 /* Trim off space for the message buffer. */ 1645 phys_avail[pa_indx] -= round_page(msgbufsize); 1646 1647 /* Map the message buffer. */ 1648 msgbufp = (struct msgbuf *)PHYS_TO_DMAP(phys_avail[pa_indx]); 1649 } 1650 1651 u_int64_t 1652 hammer_time(u_int64_t modulep, u_int64_t physfree) 1653 { 1654 caddr_t kmdp; 1655 int gsel_tss, x; 1656 struct pcpu *pc; 1657 struct nmi_pcpu *np; 1658 struct xstate_hdr *xhdr; 1659 u_int64_t msr; 1660 char *env; 1661 size_t kstack0_sz; 1662 1663 thread0.td_kstack = physfree + KERNBASE; 1664 thread0.td_kstack_pages = KSTACK_PAGES; 1665 kstack0_sz = thread0.td_kstack_pages * PAGE_SIZE; 1666 bzero((void *)thread0.td_kstack, kstack0_sz); 1667 physfree += kstack0_sz; 1668 1669 /* 1670 * This may be done better later if it gets more high level 1671 * components in it. If so just link td->td_proc here. 1672 */ 1673 proc_linkup0(&proc0, &thread0); 1674 1675 preload_metadata = (caddr_t)(uintptr_t)(modulep + KERNBASE); 1676 preload_bootstrap_relocate(KERNBASE); 1677 kmdp = preload_search_by_type("elf kernel"); 1678 if (kmdp == NULL) 1679 kmdp = preload_search_by_type("elf64 kernel"); 1680 boothowto = MD_FETCH(kmdp, MODINFOMD_HOWTO, int); 1681 kern_envp = MD_FETCH(kmdp, MODINFOMD_ENVP, char *) + KERNBASE; 1682 #ifdef DDB 1683 ksym_start = MD_FETCH(kmdp, MODINFOMD_SSYM, uintptr_t); 1684 ksym_end = MD_FETCH(kmdp, MODINFOMD_ESYM, uintptr_t); 1685 #endif 1686 1687 /* Init basic tunables, hz etc */ 1688 init_param1(); 1689 1690 /* 1691 * make gdt memory segments 1692 */ 1693 for (x = 0; x < NGDT; x++) { 1694 if (x != GPROC0_SEL && x != (GPROC0_SEL + 1) && 1695 x != GUSERLDT_SEL && x != (GUSERLDT_SEL) + 1) 1696 ssdtosd(&gdt_segs[x], &gdt[x]); 1697 } 1698 gdt_segs[GPROC0_SEL].ssd_base = (uintptr_t)&common_tss[0]; 1699 ssdtosyssd(&gdt_segs[GPROC0_SEL], 1700 (struct system_segment_descriptor *)&gdt[GPROC0_SEL]); 1701 1702 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1; 1703 r_gdt.rd_base = (long) gdt; 1704 lgdt(&r_gdt); 1705 pc = &__pcpu[0]; 1706 1707 wrmsr(MSR_FSBASE, 0); /* User value */ 1708 wrmsr(MSR_GSBASE, (u_int64_t)pc); 1709 wrmsr(MSR_KGSBASE, 0); /* User value while in the kernel */ 1710 1711 pcpu_init(pc, 0, sizeof(struct pcpu)); 1712 dpcpu_init((void *)(physfree + KERNBASE), 0); 1713 physfree += DPCPU_SIZE; 1714 PCPU_SET(prvspace, pc); 1715 PCPU_SET(curthread, &thread0); 1716 PCPU_SET(tssp, &common_tss[0]); 1717 PCPU_SET(commontssp, &common_tss[0]); 1718 PCPU_SET(tss, (struct system_segment_descriptor *)&gdt[GPROC0_SEL]); 1719 PCPU_SET(ldt, (struct system_segment_descriptor *)&gdt[GUSERLDT_SEL]); 1720 PCPU_SET(fs32p, &gdt[GUFS32_SEL]); 1721 PCPU_SET(gs32p, &gdt[GUGS32_SEL]); 1722 1723 /* 1724 * Initialize mutexes. 1725 * 1726 * icu_lock: in order to allow an interrupt to occur in a critical 1727 * section, to set pcpu->ipending (etc...) properly, we 1728 * must be able to get the icu lock, so it can't be 1729 * under witness. 1730 */ 1731 mutex_init(); 1732 mtx_init(&icu_lock, "icu", NULL, MTX_SPIN | MTX_NOWITNESS); 1733 mtx_init(&dt_lock, "descriptor tables", NULL, MTX_DEF); 1734 1735 /* exceptions */ 1736 for (x = 0; x < NIDT; x++) 1737 setidt(x, &IDTVEC(rsvd), SDT_SYSIGT, SEL_KPL, 0); 1738 setidt(IDT_DE, &IDTVEC(div), SDT_SYSIGT, SEL_KPL, 0); 1739 setidt(IDT_DB, &IDTVEC(dbg), SDT_SYSIGT, SEL_KPL, 0); 1740 setidt(IDT_NMI, &IDTVEC(nmi), SDT_SYSIGT, SEL_KPL, 2); 1741 setidt(IDT_BP, &IDTVEC(bpt), SDT_SYSIGT, SEL_UPL, 0); 1742 setidt(IDT_OF, &IDTVEC(ofl), SDT_SYSIGT, SEL_KPL, 0); 1743 setidt(IDT_BR, &IDTVEC(bnd), SDT_SYSIGT, SEL_KPL, 0); 1744 setidt(IDT_UD, &IDTVEC(ill), SDT_SYSIGT, SEL_KPL, 0); 1745 setidt(IDT_NM, &IDTVEC(dna), SDT_SYSIGT, SEL_KPL, 0); 1746 setidt(IDT_DF, &IDTVEC(dblfault), SDT_SYSIGT, SEL_KPL, 1); 1747 setidt(IDT_FPUGP, &IDTVEC(fpusegm), SDT_SYSIGT, SEL_KPL, 0); 1748 setidt(IDT_TS, &IDTVEC(tss), SDT_SYSIGT, SEL_KPL, 0); 1749 setidt(IDT_NP, &IDTVEC(missing), SDT_SYSIGT, SEL_KPL, 0); 1750 setidt(IDT_SS, &IDTVEC(stk), SDT_SYSIGT, SEL_KPL, 0); 1751 setidt(IDT_GP, &IDTVEC(prot), SDT_SYSIGT, SEL_KPL, 0); 1752 setidt(IDT_PF, &IDTVEC(page), SDT_SYSIGT, SEL_KPL, 0); 1753 setidt(IDT_MF, &IDTVEC(fpu), SDT_SYSIGT, SEL_KPL, 0); 1754 setidt(IDT_AC, &IDTVEC(align), SDT_SYSIGT, SEL_KPL, 0); 1755 setidt(IDT_MC, &IDTVEC(mchk), SDT_SYSIGT, SEL_KPL, 0); 1756 setidt(IDT_XF, &IDTVEC(xmm), SDT_SYSIGT, SEL_KPL, 0); 1757 #ifdef KDTRACE_HOOKS 1758 setidt(IDT_DTRACE_RET, &IDTVEC(dtrace_ret), SDT_SYSIGT, SEL_UPL, 0); 1759 #endif 1760 1761 r_idt.rd_limit = sizeof(idt0) - 1; 1762 r_idt.rd_base = (long) idt; 1763 lidt(&r_idt); 1764 1765 /* 1766 * Initialize the i8254 before the console so that console 1767 * initialization can use DELAY(). 1768 */ 1769 i8254_init(); 1770 1771 /* 1772 * Initialize the console before we print anything out. 1773 */ 1774 cninit(); 1775 1776 #ifdef DEV_ISA 1777 #ifdef DEV_ATPIC 1778 elcr_probe(); 1779 atpic_startup(); 1780 #else 1781 /* Reset and mask the atpics and leave them shut down. */ 1782 atpic_reset(); 1783 1784 /* 1785 * Point the ICU spurious interrupt vectors at the APIC spurious 1786 * interrupt handler. 1787 */ 1788 setidt(IDT_IO_INTS + 7, IDTVEC(spuriousint), SDT_SYSIGT, SEL_KPL, 0); 1789 setidt(IDT_IO_INTS + 15, IDTVEC(spuriousint), SDT_SYSIGT, SEL_KPL, 0); 1790 #endif 1791 #else 1792 #error "have you forgotten the isa device?"; 1793 #endif 1794 1795 kdb_init(); 1796 1797 #ifdef KDB 1798 if (boothowto & RB_KDB) 1799 kdb_enter(KDB_WHY_BOOTFLAGS, 1800 "Boot flags requested debugger"); 1801 #endif 1802 1803 identify_cpu(); /* Final stage of CPU initialization */ 1804 initializecpu(); /* Initialize CPU registers */ 1805 initializecpucache(); 1806 1807 /* doublefault stack space, runs on ist1 */ 1808 common_tss[0].tss_ist1 = (long)&dblfault_stack[sizeof(dblfault_stack)]; 1809 1810 /* 1811 * NMI stack, runs on ist2. The pcpu pointer is stored just 1812 * above the start of the ist2 stack. 1813 */ 1814 np = ((struct nmi_pcpu *) &nmi0_stack[sizeof(nmi0_stack)]) - 1; 1815 np->np_pcpu = (register_t) pc; 1816 common_tss[0].tss_ist2 = (long) np; 1817 1818 /* Set the IO permission bitmap (empty due to tss seg limit) */ 1819 common_tss[0].tss_iobase = sizeof(struct amd64tss) + 1820 IOPAGES * PAGE_SIZE; 1821 1822 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL); 1823 ltr(gsel_tss); 1824 1825 /* Set up the fast syscall stuff */ 1826 msr = rdmsr(MSR_EFER) | EFER_SCE; 1827 wrmsr(MSR_EFER, msr); 1828 wrmsr(MSR_LSTAR, (u_int64_t)IDTVEC(fast_syscall)); 1829 wrmsr(MSR_CSTAR, (u_int64_t)IDTVEC(fast_syscall32)); 1830 msr = ((u_int64_t)GSEL(GCODE_SEL, SEL_KPL) << 32) | 1831 ((u_int64_t)GSEL(GUCODE32_SEL, SEL_UPL) << 48); 1832 wrmsr(MSR_STAR, msr); 1833 wrmsr(MSR_SF_MASK, PSL_NT|PSL_T|PSL_I|PSL_C|PSL_D); 1834 1835 getmemsize(kmdp, physfree); 1836 init_param2(physmem); 1837 1838 /* now running on new page tables, configured,and u/iom is accessible */ 1839 1840 msgbufinit(msgbufp, msgbufsize); 1841 fpuinit(); 1842 1843 /* 1844 * Set up thread0 pcb after fpuinit calculated pcb + fpu save 1845 * area size. Zero out the extended state header in fpu save 1846 * area. 1847 */ 1848 thread0.td_pcb = get_pcb_td(&thread0); 1849 bzero(get_pcb_user_save_td(&thread0), cpu_max_ext_state_size); 1850 if (use_xsave) { 1851 xhdr = (struct xstate_hdr *)(get_pcb_user_save_td(&thread0) + 1852 1); 1853 xhdr->xstate_bv = xsave_mask; 1854 } 1855 /* make an initial tss so cpu can get interrupt stack on syscall! */ 1856 common_tss[0].tss_rsp0 = (vm_offset_t)thread0.td_pcb; 1857 /* Ensure the stack is aligned to 16 bytes */ 1858 common_tss[0].tss_rsp0 &= ~0xFul; 1859 PCPU_SET(rsp0, common_tss[0].tss_rsp0); 1860 PCPU_SET(curpcb, thread0.td_pcb); 1861 1862 /* transfer to user mode */ 1863 1864 _ucodesel = GSEL(GUCODE_SEL, SEL_UPL); 1865 _udatasel = GSEL(GUDATA_SEL, SEL_UPL); 1866 _ucode32sel = GSEL(GUCODE32_SEL, SEL_UPL); 1867 _ufssel = GSEL(GUFS32_SEL, SEL_UPL); 1868 _ugssel = GSEL(GUGS32_SEL, SEL_UPL); 1869 1870 load_ds(_udatasel); 1871 load_es(_udatasel); 1872 load_fs(_ufssel); 1873 1874 /* setup proc 0's pcb */ 1875 thread0.td_pcb->pcb_flags = 0; 1876 thread0.td_pcb->pcb_cr3 = KPML4phys; 1877 thread0.td_frame = &proc0_tf; 1878 1879 env = getenv("kernelname"); 1880 if (env != NULL) 1881 strlcpy(kernelname, env, sizeof(kernelname)); 1882 1883 #ifdef XENHVM 1884 if (inw(0x10) == 0x49d2) { 1885 if (bootverbose) 1886 printf("Xen detected: disabling emulated block and network devices\n"); 1887 outw(0x10, 3); 1888 } 1889 #endif 1890 1891 cpu_probe_amdc1e(); 1892 1893 #ifdef FDT 1894 x86_init_fdt(); 1895 #endif 1896 1897 /* Location of kernel stack for locore */ 1898 return ((u_int64_t)thread0.td_pcb); 1899 } 1900 1901 void 1902 cpu_pcpu_init(struct pcpu *pcpu, int cpuid, size_t size) 1903 { 1904 1905 pcpu->pc_acpi_id = 0xffffffff; 1906 } 1907 1908 void 1909 spinlock_enter(void) 1910 { 1911 struct thread *td; 1912 register_t flags; 1913 1914 td = curthread; 1915 if (td->td_md.md_spinlock_count == 0) { 1916 flags = intr_disable(); 1917 td->td_md.md_spinlock_count = 1; 1918 td->td_md.md_saved_flags = flags; 1919 } else 1920 td->td_md.md_spinlock_count++; 1921 critical_enter(); 1922 } 1923 1924 void 1925 spinlock_exit(void) 1926 { 1927 struct thread *td; 1928 register_t flags; 1929 1930 td = curthread; 1931 critical_exit(); 1932 flags = td->td_md.md_saved_flags; 1933 td->td_md.md_spinlock_count--; 1934 if (td->td_md.md_spinlock_count == 0) 1935 intr_restore(flags); 1936 } 1937 1938 /* 1939 * Construct a PCB from a trapframe. This is called from kdb_trap() where 1940 * we want to start a backtrace from the function that caused us to enter 1941 * the debugger. We have the context in the trapframe, but base the trace 1942 * on the PCB. The PCB doesn't have to be perfect, as long as it contains 1943 * enough for a backtrace. 1944 */ 1945 void 1946 makectx(struct trapframe *tf, struct pcb *pcb) 1947 { 1948 1949 pcb->pcb_r12 = tf->tf_r12; 1950 pcb->pcb_r13 = tf->tf_r13; 1951 pcb->pcb_r14 = tf->tf_r14; 1952 pcb->pcb_r15 = tf->tf_r15; 1953 pcb->pcb_rbp = tf->tf_rbp; 1954 pcb->pcb_rbx = tf->tf_rbx; 1955 pcb->pcb_rip = tf->tf_rip; 1956 pcb->pcb_rsp = tf->tf_rsp; 1957 } 1958 1959 int 1960 ptrace_set_pc(struct thread *td, unsigned long addr) 1961 { 1962 td->td_frame->tf_rip = addr; 1963 return (0); 1964 } 1965 1966 int 1967 ptrace_single_step(struct thread *td) 1968 { 1969 td->td_frame->tf_rflags |= PSL_T; 1970 return (0); 1971 } 1972 1973 int 1974 ptrace_clear_single_step(struct thread *td) 1975 { 1976 td->td_frame->tf_rflags &= ~PSL_T; 1977 return (0); 1978 } 1979 1980 int 1981 fill_regs(struct thread *td, struct reg *regs) 1982 { 1983 struct trapframe *tp; 1984 1985 tp = td->td_frame; 1986 return (fill_frame_regs(tp, regs)); 1987 } 1988 1989 int 1990 fill_frame_regs(struct trapframe *tp, struct reg *regs) 1991 { 1992 regs->r_r15 = tp->tf_r15; 1993 regs->r_r14 = tp->tf_r14; 1994 regs->r_r13 = tp->tf_r13; 1995 regs->r_r12 = tp->tf_r12; 1996 regs->r_r11 = tp->tf_r11; 1997 regs->r_r10 = tp->tf_r10; 1998 regs->r_r9 = tp->tf_r9; 1999 regs->r_r8 = tp->tf_r8; 2000 regs->r_rdi = tp->tf_rdi; 2001 regs->r_rsi = tp->tf_rsi; 2002 regs->r_rbp = tp->tf_rbp; 2003 regs->r_rbx = tp->tf_rbx; 2004 regs->r_rdx = tp->tf_rdx; 2005 regs->r_rcx = tp->tf_rcx; 2006 regs->r_rax = tp->tf_rax; 2007 regs->r_rip = tp->tf_rip; 2008 regs->r_cs = tp->tf_cs; 2009 regs->r_rflags = tp->tf_rflags; 2010 regs->r_rsp = tp->tf_rsp; 2011 regs->r_ss = tp->tf_ss; 2012 if (tp->tf_flags & TF_HASSEGS) { 2013 regs->r_ds = tp->tf_ds; 2014 regs->r_es = tp->tf_es; 2015 regs->r_fs = tp->tf_fs; 2016 regs->r_gs = tp->tf_gs; 2017 } else { 2018 regs->r_ds = 0; 2019 regs->r_es = 0; 2020 regs->r_fs = 0; 2021 regs->r_gs = 0; 2022 } 2023 return (0); 2024 } 2025 2026 int 2027 set_regs(struct thread *td, struct reg *regs) 2028 { 2029 struct trapframe *tp; 2030 register_t rflags; 2031 2032 tp = td->td_frame; 2033 rflags = regs->r_rflags & 0xffffffff; 2034 if (!EFL_SECURE(rflags, tp->tf_rflags) || !CS_SECURE(regs->r_cs)) 2035 return (EINVAL); 2036 tp->tf_r15 = regs->r_r15; 2037 tp->tf_r14 = regs->r_r14; 2038 tp->tf_r13 = regs->r_r13; 2039 tp->tf_r12 = regs->r_r12; 2040 tp->tf_r11 = regs->r_r11; 2041 tp->tf_r10 = regs->r_r10; 2042 tp->tf_r9 = regs->r_r9; 2043 tp->tf_r8 = regs->r_r8; 2044 tp->tf_rdi = regs->r_rdi; 2045 tp->tf_rsi = regs->r_rsi; 2046 tp->tf_rbp = regs->r_rbp; 2047 tp->tf_rbx = regs->r_rbx; 2048 tp->tf_rdx = regs->r_rdx; 2049 tp->tf_rcx = regs->r_rcx; 2050 tp->tf_rax = regs->r_rax; 2051 tp->tf_rip = regs->r_rip; 2052 tp->tf_cs = regs->r_cs; 2053 tp->tf_rflags = rflags; 2054 tp->tf_rsp = regs->r_rsp; 2055 tp->tf_ss = regs->r_ss; 2056 if (0) { /* XXXKIB */ 2057 tp->tf_ds = regs->r_ds; 2058 tp->tf_es = regs->r_es; 2059 tp->tf_fs = regs->r_fs; 2060 tp->tf_gs = regs->r_gs; 2061 tp->tf_flags = TF_HASSEGS; 2062 set_pcb_flags(td->td_pcb, PCB_FULL_IRET); 2063 } 2064 return (0); 2065 } 2066 2067 /* XXX check all this stuff! */ 2068 /* externalize from sv_xmm */ 2069 static void 2070 fill_fpregs_xmm(struct savefpu *sv_xmm, struct fpreg *fpregs) 2071 { 2072 struct envxmm *penv_fpreg = (struct envxmm *)&fpregs->fpr_env; 2073 struct envxmm *penv_xmm = &sv_xmm->sv_env; 2074 int i; 2075 2076 /* pcb -> fpregs */ 2077 bzero(fpregs, sizeof(*fpregs)); 2078 2079 /* FPU control/status */ 2080 penv_fpreg->en_cw = penv_xmm->en_cw; 2081 penv_fpreg->en_sw = penv_xmm->en_sw; 2082 penv_fpreg->en_tw = penv_xmm->en_tw; 2083 penv_fpreg->en_opcode = penv_xmm->en_opcode; 2084 penv_fpreg->en_rip = penv_xmm->en_rip; 2085 penv_fpreg->en_rdp = penv_xmm->en_rdp; 2086 penv_fpreg->en_mxcsr = penv_xmm->en_mxcsr; 2087 penv_fpreg->en_mxcsr_mask = penv_xmm->en_mxcsr_mask; 2088 2089 /* FPU registers */ 2090 for (i = 0; i < 8; ++i) 2091 bcopy(sv_xmm->sv_fp[i].fp_acc.fp_bytes, fpregs->fpr_acc[i], 10); 2092 2093 /* SSE registers */ 2094 for (i = 0; i < 16; ++i) 2095 bcopy(sv_xmm->sv_xmm[i].xmm_bytes, fpregs->fpr_xacc[i], 16); 2096 } 2097 2098 /* internalize from fpregs into sv_xmm */ 2099 static void 2100 set_fpregs_xmm(struct fpreg *fpregs, struct savefpu *sv_xmm) 2101 { 2102 struct envxmm *penv_xmm = &sv_xmm->sv_env; 2103 struct envxmm *penv_fpreg = (struct envxmm *)&fpregs->fpr_env; 2104 int i; 2105 2106 /* fpregs -> pcb */ 2107 /* FPU control/status */ 2108 penv_xmm->en_cw = penv_fpreg->en_cw; 2109 penv_xmm->en_sw = penv_fpreg->en_sw; 2110 penv_xmm->en_tw = penv_fpreg->en_tw; 2111 penv_xmm->en_opcode = penv_fpreg->en_opcode; 2112 penv_xmm->en_rip = penv_fpreg->en_rip; 2113 penv_xmm->en_rdp = penv_fpreg->en_rdp; 2114 penv_xmm->en_mxcsr = penv_fpreg->en_mxcsr; 2115 penv_xmm->en_mxcsr_mask = penv_fpreg->en_mxcsr_mask & cpu_mxcsr_mask; 2116 2117 /* FPU registers */ 2118 for (i = 0; i < 8; ++i) 2119 bcopy(fpregs->fpr_acc[i], sv_xmm->sv_fp[i].fp_acc.fp_bytes, 10); 2120 2121 /* SSE registers */ 2122 for (i = 0; i < 16; ++i) 2123 bcopy(fpregs->fpr_xacc[i], sv_xmm->sv_xmm[i].xmm_bytes, 16); 2124 } 2125 2126 /* externalize from td->pcb */ 2127 int 2128 fill_fpregs(struct thread *td, struct fpreg *fpregs) 2129 { 2130 2131 KASSERT(td == curthread || TD_IS_SUSPENDED(td) || 2132 P_SHOULDSTOP(td->td_proc), 2133 ("not suspended thread %p", td)); 2134 fpugetregs(td); 2135 fill_fpregs_xmm(get_pcb_user_save_td(td), fpregs); 2136 return (0); 2137 } 2138 2139 /* internalize to td->pcb */ 2140 int 2141 set_fpregs(struct thread *td, struct fpreg *fpregs) 2142 { 2143 2144 set_fpregs_xmm(fpregs, get_pcb_user_save_td(td)); 2145 fpuuserinited(td); 2146 return (0); 2147 } 2148 2149 /* 2150 * Get machine context. 2151 */ 2152 int 2153 get_mcontext(struct thread *td, mcontext_t *mcp, int flags) 2154 { 2155 struct pcb *pcb; 2156 struct trapframe *tp; 2157 2158 pcb = td->td_pcb; 2159 tp = td->td_frame; 2160 PROC_LOCK(curthread->td_proc); 2161 mcp->mc_onstack = sigonstack(tp->tf_rsp); 2162 PROC_UNLOCK(curthread->td_proc); 2163 mcp->mc_r15 = tp->tf_r15; 2164 mcp->mc_r14 = tp->tf_r14; 2165 mcp->mc_r13 = tp->tf_r13; 2166 mcp->mc_r12 = tp->tf_r12; 2167 mcp->mc_r11 = tp->tf_r11; 2168 mcp->mc_r10 = tp->tf_r10; 2169 mcp->mc_r9 = tp->tf_r9; 2170 mcp->mc_r8 = tp->tf_r8; 2171 mcp->mc_rdi = tp->tf_rdi; 2172 mcp->mc_rsi = tp->tf_rsi; 2173 mcp->mc_rbp = tp->tf_rbp; 2174 mcp->mc_rbx = tp->tf_rbx; 2175 mcp->mc_rcx = tp->tf_rcx; 2176 mcp->mc_rflags = tp->tf_rflags; 2177 if (flags & GET_MC_CLEAR_RET) { 2178 mcp->mc_rax = 0; 2179 mcp->mc_rdx = 0; 2180 mcp->mc_rflags &= ~PSL_C; 2181 } else { 2182 mcp->mc_rax = tp->tf_rax; 2183 mcp->mc_rdx = tp->tf_rdx; 2184 } 2185 mcp->mc_rip = tp->tf_rip; 2186 mcp->mc_cs = tp->tf_cs; 2187 mcp->mc_rsp = tp->tf_rsp; 2188 mcp->mc_ss = tp->tf_ss; 2189 mcp->mc_ds = tp->tf_ds; 2190 mcp->mc_es = tp->tf_es; 2191 mcp->mc_fs = tp->tf_fs; 2192 mcp->mc_gs = tp->tf_gs; 2193 mcp->mc_flags = tp->tf_flags; 2194 mcp->mc_len = sizeof(*mcp); 2195 get_fpcontext(td, mcp, NULL, 0); 2196 mcp->mc_fsbase = pcb->pcb_fsbase; 2197 mcp->mc_gsbase = pcb->pcb_gsbase; 2198 mcp->mc_xfpustate = 0; 2199 mcp->mc_xfpustate_len = 0; 2200 bzero(mcp->mc_spare, sizeof(mcp->mc_spare)); 2201 return (0); 2202 } 2203 2204 /* 2205 * Set machine context. 2206 * 2207 * However, we don't set any but the user modifiable flags, and we won't 2208 * touch the cs selector. 2209 */ 2210 int 2211 set_mcontext(struct thread *td, const mcontext_t *mcp) 2212 { 2213 struct pcb *pcb; 2214 struct trapframe *tp; 2215 char *xfpustate; 2216 long rflags; 2217 int ret; 2218 2219 pcb = td->td_pcb; 2220 tp = td->td_frame; 2221 if (mcp->mc_len != sizeof(*mcp) || 2222 (mcp->mc_flags & ~_MC_FLAG_MASK) != 0) 2223 return (EINVAL); 2224 rflags = (mcp->mc_rflags & PSL_USERCHANGE) | 2225 (tp->tf_rflags & ~PSL_USERCHANGE); 2226 if (mcp->mc_flags & _MC_HASFPXSTATE) { 2227 if (mcp->mc_xfpustate_len > cpu_max_ext_state_size - 2228 sizeof(struct savefpu)) 2229 return (EINVAL); 2230 xfpustate = __builtin_alloca(mcp->mc_xfpustate_len); 2231 ret = copyin((void *)mcp->mc_xfpustate, xfpustate, 2232 mcp->mc_xfpustate_len); 2233 if (ret != 0) 2234 return (ret); 2235 } else 2236 xfpustate = NULL; 2237 ret = set_fpcontext(td, mcp, xfpustate, mcp->mc_xfpustate_len); 2238 if (ret != 0) 2239 return (ret); 2240 tp->tf_r15 = mcp->mc_r15; 2241 tp->tf_r14 = mcp->mc_r14; 2242 tp->tf_r13 = mcp->mc_r13; 2243 tp->tf_r12 = mcp->mc_r12; 2244 tp->tf_r11 = mcp->mc_r11; 2245 tp->tf_r10 = mcp->mc_r10; 2246 tp->tf_r9 = mcp->mc_r9; 2247 tp->tf_r8 = mcp->mc_r8; 2248 tp->tf_rdi = mcp->mc_rdi; 2249 tp->tf_rsi = mcp->mc_rsi; 2250 tp->tf_rbp = mcp->mc_rbp; 2251 tp->tf_rbx = mcp->mc_rbx; 2252 tp->tf_rdx = mcp->mc_rdx; 2253 tp->tf_rcx = mcp->mc_rcx; 2254 tp->tf_rax = mcp->mc_rax; 2255 tp->tf_rip = mcp->mc_rip; 2256 tp->tf_rflags = rflags; 2257 tp->tf_rsp = mcp->mc_rsp; 2258 tp->tf_ss = mcp->mc_ss; 2259 tp->tf_flags = mcp->mc_flags; 2260 if (tp->tf_flags & TF_HASSEGS) { 2261 tp->tf_ds = mcp->mc_ds; 2262 tp->tf_es = mcp->mc_es; 2263 tp->tf_fs = mcp->mc_fs; 2264 tp->tf_gs = mcp->mc_gs; 2265 } 2266 if (mcp->mc_flags & _MC_HASBASES) { 2267 pcb->pcb_fsbase = mcp->mc_fsbase; 2268 pcb->pcb_gsbase = mcp->mc_gsbase; 2269 } 2270 set_pcb_flags(pcb, PCB_FULL_IRET); 2271 return (0); 2272 } 2273 2274 static void 2275 get_fpcontext(struct thread *td, mcontext_t *mcp, char *xfpusave, 2276 size_t xfpusave_len) 2277 { 2278 size_t max_len, len; 2279 2280 mcp->mc_ownedfp = fpugetregs(td); 2281 bcopy(get_pcb_user_save_td(td), &mcp->mc_fpstate[0], 2282 sizeof(mcp->mc_fpstate)); 2283 mcp->mc_fpformat = fpuformat(); 2284 if (!use_xsave || xfpusave_len == 0) 2285 return; 2286 max_len = cpu_max_ext_state_size - sizeof(struct savefpu); 2287 len = xfpusave_len; 2288 if (len > max_len) { 2289 len = max_len; 2290 bzero(xfpusave + max_len, len - max_len); 2291 } 2292 mcp->mc_flags |= _MC_HASFPXSTATE; 2293 mcp->mc_xfpustate_len = len; 2294 bcopy(get_pcb_user_save_td(td) + 1, xfpusave, len); 2295 } 2296 2297 static int 2298 set_fpcontext(struct thread *td, const mcontext_t *mcp, char *xfpustate, 2299 size_t xfpustate_len) 2300 { 2301 struct savefpu *fpstate; 2302 int error; 2303 2304 if (mcp->mc_fpformat == _MC_FPFMT_NODEV) 2305 return (0); 2306 else if (mcp->mc_fpformat != _MC_FPFMT_XMM) 2307 return (EINVAL); 2308 else if (mcp->mc_ownedfp == _MC_FPOWNED_NONE) { 2309 /* We don't care what state is left in the FPU or PCB. */ 2310 fpstate_drop(td); 2311 error = 0; 2312 } else if (mcp->mc_ownedfp == _MC_FPOWNED_FPU || 2313 mcp->mc_ownedfp == _MC_FPOWNED_PCB) { 2314 fpstate = (struct savefpu *)&mcp->mc_fpstate; 2315 fpstate->sv_env.en_mxcsr &= cpu_mxcsr_mask; 2316 error = fpusetregs(td, fpstate, xfpustate, xfpustate_len); 2317 } else 2318 return (EINVAL); 2319 return (error); 2320 } 2321 2322 void 2323 fpstate_drop(struct thread *td) 2324 { 2325 2326 KASSERT(PCB_USER_FPU(td->td_pcb), ("fpstate_drop: kernel-owned fpu")); 2327 critical_enter(); 2328 if (PCPU_GET(fpcurthread) == td) 2329 fpudrop(); 2330 /* 2331 * XXX force a full drop of the fpu. The above only drops it if we 2332 * owned it. 2333 * 2334 * XXX I don't much like fpugetuserregs()'s semantics of doing a full 2335 * drop. Dropping only to the pcb matches fnsave's behaviour. 2336 * We only need to drop to !PCB_INITDONE in sendsig(). But 2337 * sendsig() is the only caller of fpugetuserregs()... perhaps we just 2338 * have too many layers. 2339 */ 2340 clear_pcb_flags(curthread->td_pcb, 2341 PCB_FPUINITDONE | PCB_USERFPUINITDONE); 2342 critical_exit(); 2343 } 2344 2345 int 2346 fill_dbregs(struct thread *td, struct dbreg *dbregs) 2347 { 2348 struct pcb *pcb; 2349 2350 if (td == NULL) { 2351 dbregs->dr[0] = rdr0(); 2352 dbregs->dr[1] = rdr1(); 2353 dbregs->dr[2] = rdr2(); 2354 dbregs->dr[3] = rdr3(); 2355 dbregs->dr[6] = rdr6(); 2356 dbregs->dr[7] = rdr7(); 2357 } else { 2358 pcb = td->td_pcb; 2359 dbregs->dr[0] = pcb->pcb_dr0; 2360 dbregs->dr[1] = pcb->pcb_dr1; 2361 dbregs->dr[2] = pcb->pcb_dr2; 2362 dbregs->dr[3] = pcb->pcb_dr3; 2363 dbregs->dr[6] = pcb->pcb_dr6; 2364 dbregs->dr[7] = pcb->pcb_dr7; 2365 } 2366 dbregs->dr[4] = 0; 2367 dbregs->dr[5] = 0; 2368 dbregs->dr[8] = 0; 2369 dbregs->dr[9] = 0; 2370 dbregs->dr[10] = 0; 2371 dbregs->dr[11] = 0; 2372 dbregs->dr[12] = 0; 2373 dbregs->dr[13] = 0; 2374 dbregs->dr[14] = 0; 2375 dbregs->dr[15] = 0; 2376 return (0); 2377 } 2378 2379 int 2380 set_dbregs(struct thread *td, struct dbreg *dbregs) 2381 { 2382 struct pcb *pcb; 2383 int i; 2384 2385 if (td == NULL) { 2386 load_dr0(dbregs->dr[0]); 2387 load_dr1(dbregs->dr[1]); 2388 load_dr2(dbregs->dr[2]); 2389 load_dr3(dbregs->dr[3]); 2390 load_dr6(dbregs->dr[6]); 2391 load_dr7(dbregs->dr[7]); 2392 } else { 2393 /* 2394 * Don't let an illegal value for dr7 get set. Specifically, 2395 * check for undefined settings. Setting these bit patterns 2396 * result in undefined behaviour and can lead to an unexpected 2397 * TRCTRAP or a general protection fault right here. 2398 * Upper bits of dr6 and dr7 must not be set 2399 */ 2400 for (i = 0; i < 4; i++) { 2401 if (DBREG_DR7_ACCESS(dbregs->dr[7], i) == 0x02) 2402 return (EINVAL); 2403 if (td->td_frame->tf_cs == _ucode32sel && 2404 DBREG_DR7_LEN(dbregs->dr[7], i) == DBREG_DR7_LEN_8) 2405 return (EINVAL); 2406 } 2407 if ((dbregs->dr[6] & 0xffffffff00000000ul) != 0 || 2408 (dbregs->dr[7] & 0xffffffff00000000ul) != 0) 2409 return (EINVAL); 2410 2411 pcb = td->td_pcb; 2412 2413 /* 2414 * Don't let a process set a breakpoint that is not within the 2415 * process's address space. If a process could do this, it 2416 * could halt the system by setting a breakpoint in the kernel 2417 * (if ddb was enabled). Thus, we need to check to make sure 2418 * that no breakpoints are being enabled for addresses outside 2419 * process's address space. 2420 * 2421 * XXX - what about when the watched area of the user's 2422 * address space is written into from within the kernel 2423 * ... wouldn't that still cause a breakpoint to be generated 2424 * from within kernel mode? 2425 */ 2426 2427 if (DBREG_DR7_ENABLED(dbregs->dr[7], 0)) { 2428 /* dr0 is enabled */ 2429 if (dbregs->dr[0] >= VM_MAXUSER_ADDRESS) 2430 return (EINVAL); 2431 } 2432 if (DBREG_DR7_ENABLED(dbregs->dr[7], 1)) { 2433 /* dr1 is enabled */ 2434 if (dbregs->dr[1] >= VM_MAXUSER_ADDRESS) 2435 return (EINVAL); 2436 } 2437 if (DBREG_DR7_ENABLED(dbregs->dr[7], 2)) { 2438 /* dr2 is enabled */ 2439 if (dbregs->dr[2] >= VM_MAXUSER_ADDRESS) 2440 return (EINVAL); 2441 } 2442 if (DBREG_DR7_ENABLED(dbregs->dr[7], 3)) { 2443 /* dr3 is enabled */ 2444 if (dbregs->dr[3] >= VM_MAXUSER_ADDRESS) 2445 return (EINVAL); 2446 } 2447 2448 pcb->pcb_dr0 = dbregs->dr[0]; 2449 pcb->pcb_dr1 = dbregs->dr[1]; 2450 pcb->pcb_dr2 = dbregs->dr[2]; 2451 pcb->pcb_dr3 = dbregs->dr[3]; 2452 pcb->pcb_dr6 = dbregs->dr[6]; 2453 pcb->pcb_dr7 = dbregs->dr[7]; 2454 2455 set_pcb_flags(pcb, PCB_DBREGS); 2456 } 2457 2458 return (0); 2459 } 2460 2461 void 2462 reset_dbregs(void) 2463 { 2464 2465 load_dr7(0); /* Turn off the control bits first */ 2466 load_dr0(0); 2467 load_dr1(0); 2468 load_dr2(0); 2469 load_dr3(0); 2470 load_dr6(0); 2471 } 2472 2473 /* 2474 * Return > 0 if a hardware breakpoint has been hit, and the 2475 * breakpoint was in user space. Return 0, otherwise. 2476 */ 2477 int 2478 user_dbreg_trap(void) 2479 { 2480 u_int64_t dr7, dr6; /* debug registers dr6 and dr7 */ 2481 u_int64_t bp; /* breakpoint bits extracted from dr6 */ 2482 int nbp; /* number of breakpoints that triggered */ 2483 caddr_t addr[4]; /* breakpoint addresses */ 2484 int i; 2485 2486 dr7 = rdr7(); 2487 if ((dr7 & 0x000000ff) == 0) { 2488 /* 2489 * all GE and LE bits in the dr7 register are zero, 2490 * thus the trap couldn't have been caused by the 2491 * hardware debug registers 2492 */ 2493 return 0; 2494 } 2495 2496 nbp = 0; 2497 dr6 = rdr6(); 2498 bp = dr6 & 0x0000000f; 2499 2500 if (!bp) { 2501 /* 2502 * None of the breakpoint bits are set meaning this 2503 * trap was not caused by any of the debug registers 2504 */ 2505 return 0; 2506 } 2507 2508 /* 2509 * at least one of the breakpoints were hit, check to see 2510 * which ones and if any of them are user space addresses 2511 */ 2512 2513 if (bp & 0x01) { 2514 addr[nbp++] = (caddr_t)rdr0(); 2515 } 2516 if (bp & 0x02) { 2517 addr[nbp++] = (caddr_t)rdr1(); 2518 } 2519 if (bp & 0x04) { 2520 addr[nbp++] = (caddr_t)rdr2(); 2521 } 2522 if (bp & 0x08) { 2523 addr[nbp++] = (caddr_t)rdr3(); 2524 } 2525 2526 for (i = 0; i < nbp; i++) { 2527 if (addr[i] < (caddr_t)VM_MAXUSER_ADDRESS) { 2528 /* 2529 * addr[i] is in user space 2530 */ 2531 return nbp; 2532 } 2533 } 2534 2535 /* 2536 * None of the breakpoints are in user space. 2537 */ 2538 return 0; 2539 } 2540 2541 #ifdef KDB 2542 2543 /* 2544 * Provide inb() and outb() as functions. They are normally only available as 2545 * inline functions, thus cannot be called from the debugger. 2546 */ 2547 2548 /* silence compiler warnings */ 2549 u_char inb_(u_short); 2550 void outb_(u_short, u_char); 2551 2552 u_char 2553 inb_(u_short port) 2554 { 2555 return inb(port); 2556 } 2557 2558 void 2559 outb_(u_short port, u_char data) 2560 { 2561 outb(port, data); 2562 } 2563 2564 #endif /* KDB */ 2565