1 /*- 2 * Copyright (c) 2003 Peter Wemm. 3 * Copyright (c) 1993 The Regents of the University of California. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 4. Neither the name of the University nor the names of its contributors 15 * may be used to endorse or promote products derived from this software 16 * without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 * $FreeBSD$ 31 */ 32 33 /* 34 * Functions to provide access to special i386 instructions. 35 * This in included in sys/systm.h, and that file should be 36 * used in preference to this. 37 */ 38 39 #ifndef _MACHINE_CPUFUNC_H_ 40 #define _MACHINE_CPUFUNC_H_ 41 42 #ifndef _SYS_CDEFS_H_ 43 #error this file needs sys/cdefs.h as a prerequisite 44 #endif 45 46 struct region_descriptor; 47 48 #define readb(va) (*(volatile uint8_t *) (va)) 49 #define readw(va) (*(volatile uint16_t *) (va)) 50 #define readl(va) (*(volatile uint32_t *) (va)) 51 #define readq(va) (*(volatile uint64_t *) (va)) 52 53 #define writeb(va, d) (*(volatile uint8_t *) (va) = (d)) 54 #define writew(va, d) (*(volatile uint16_t *) (va) = (d)) 55 #define writel(va, d) (*(volatile uint32_t *) (va) = (d)) 56 #define writeq(va, d) (*(volatile uint64_t *) (va) = (d)) 57 58 #if defined(__GNUCLIKE_ASM) && defined(__CC_SUPPORTS___INLINE) 59 60 static __inline void 61 breakpoint(void) 62 { 63 __asm __volatile("int $3"); 64 } 65 66 static __inline u_int 67 bsfl(u_int mask) 68 { 69 u_int result; 70 71 __asm __volatile("bsfl %1,%0" : "=r" (result) : "rm" (mask)); 72 return (result); 73 } 74 75 static __inline u_long 76 bsfq(u_long mask) 77 { 78 u_long result; 79 80 __asm __volatile("bsfq %1,%0" : "=r" (result) : "rm" (mask)); 81 return (result); 82 } 83 84 static __inline u_int 85 bsrl(u_int mask) 86 { 87 u_int result; 88 89 __asm __volatile("bsrl %1,%0" : "=r" (result) : "rm" (mask)); 90 return (result); 91 } 92 93 static __inline u_long 94 bsrq(u_long mask) 95 { 96 u_long result; 97 98 __asm __volatile("bsrq %1,%0" : "=r" (result) : "rm" (mask)); 99 return (result); 100 } 101 102 static __inline void 103 clflush(u_long addr) 104 { 105 106 __asm __volatile("clflush %0" : : "m" (*(char *)addr)); 107 } 108 109 static __inline void 110 clts(void) 111 { 112 113 __asm __volatile("clts"); 114 } 115 116 static __inline void 117 disable_intr(void) 118 { 119 __asm __volatile("cli" : : : "memory"); 120 } 121 122 static __inline void 123 do_cpuid(u_int ax, u_int *p) 124 { 125 __asm __volatile("cpuid" 126 : "=a" (p[0]), "=b" (p[1]), "=c" (p[2]), "=d" (p[3]) 127 : "0" (ax)); 128 } 129 130 static __inline void 131 cpuid_count(u_int ax, u_int cx, u_int *p) 132 { 133 __asm __volatile("cpuid" 134 : "=a" (p[0]), "=b" (p[1]), "=c" (p[2]), "=d" (p[3]) 135 : "0" (ax), "c" (cx)); 136 } 137 138 static __inline void 139 enable_intr(void) 140 { 141 __asm __volatile("sti"); 142 } 143 144 #ifdef _KERNEL 145 146 #define HAVE_INLINE_FFS 147 #define ffs(x) __builtin_ffs(x) 148 149 #define HAVE_INLINE_FFSL 150 151 static __inline int 152 ffsl(long mask) 153 { 154 return (mask == 0 ? mask : (int)bsfq((u_long)mask) + 1); 155 } 156 157 #define HAVE_INLINE_FFSLL 158 159 static __inline int 160 ffsll(long long mask) 161 { 162 return (ffsl((long)mask)); 163 } 164 165 #define HAVE_INLINE_FLS 166 167 static __inline int 168 fls(int mask) 169 { 170 return (mask == 0 ? mask : (int)bsrl((u_int)mask) + 1); 171 } 172 173 #define HAVE_INLINE_FLSL 174 175 static __inline int 176 flsl(long mask) 177 { 178 return (mask == 0 ? mask : (int)bsrq((u_long)mask) + 1); 179 } 180 181 #define HAVE_INLINE_FLSLL 182 183 static __inline int 184 flsll(long long mask) 185 { 186 return (flsl((long)mask)); 187 } 188 189 #endif /* _KERNEL */ 190 191 static __inline void 192 halt(void) 193 { 194 __asm __volatile("hlt"); 195 } 196 197 static __inline u_char 198 inb(u_int port) 199 { 200 u_char data; 201 202 __asm __volatile("inb %w1, %0" : "=a" (data) : "Nd" (port)); 203 return (data); 204 } 205 206 static __inline u_int 207 inl(u_int port) 208 { 209 u_int data; 210 211 __asm __volatile("inl %w1, %0" : "=a" (data) : "Nd" (port)); 212 return (data); 213 } 214 215 static __inline void 216 insb(u_int port, void *addr, size_t count) 217 { 218 __asm __volatile("cld; rep; insb" 219 : "+D" (addr), "+c" (count) 220 : "d" (port) 221 : "memory"); 222 } 223 224 static __inline void 225 insw(u_int port, void *addr, size_t count) 226 { 227 __asm __volatile("cld; rep; insw" 228 : "+D" (addr), "+c" (count) 229 : "d" (port) 230 : "memory"); 231 } 232 233 static __inline void 234 insl(u_int port, void *addr, size_t count) 235 { 236 __asm __volatile("cld; rep; insl" 237 : "+D" (addr), "+c" (count) 238 : "d" (port) 239 : "memory"); 240 } 241 242 static __inline void 243 invd(void) 244 { 245 __asm __volatile("invd"); 246 } 247 248 static __inline u_short 249 inw(u_int port) 250 { 251 u_short data; 252 253 __asm __volatile("inw %w1, %0" : "=a" (data) : "Nd" (port)); 254 return (data); 255 } 256 257 static __inline void 258 outb(u_int port, u_char data) 259 { 260 __asm __volatile("outb %0, %w1" : : "a" (data), "Nd" (port)); 261 } 262 263 static __inline void 264 outl(u_int port, u_int data) 265 { 266 __asm __volatile("outl %0, %w1" : : "a" (data), "Nd" (port)); 267 } 268 269 static __inline void 270 outsb(u_int port, const void *addr, size_t count) 271 { 272 __asm __volatile("cld; rep; outsb" 273 : "+S" (addr), "+c" (count) 274 : "d" (port)); 275 } 276 277 static __inline void 278 outsw(u_int port, const void *addr, size_t count) 279 { 280 __asm __volatile("cld; rep; outsw" 281 : "+S" (addr), "+c" (count) 282 : "d" (port)); 283 } 284 285 static __inline void 286 outsl(u_int port, const void *addr, size_t count) 287 { 288 __asm __volatile("cld; rep; outsl" 289 : "+S" (addr), "+c" (count) 290 : "d" (port)); 291 } 292 293 static __inline void 294 outw(u_int port, u_short data) 295 { 296 __asm __volatile("outw %0, %w1" : : "a" (data), "Nd" (port)); 297 } 298 299 static __inline u_long 300 popcntq(u_long mask) 301 { 302 u_long result; 303 304 __asm __volatile("popcntq %1,%0" : "=r" (result) : "rm" (mask)); 305 return (result); 306 } 307 308 static __inline void 309 lfence(void) 310 { 311 312 __asm __volatile("lfence" : : : "memory"); 313 } 314 315 static __inline void 316 mfence(void) 317 { 318 319 __asm __volatile("mfence" : : : "memory"); 320 } 321 322 static __inline void 323 ia32_pause(void) 324 { 325 __asm __volatile("pause"); 326 } 327 328 static __inline u_long 329 read_rflags(void) 330 { 331 u_long rf; 332 333 __asm __volatile("pushfq; popq %0" : "=r" (rf)); 334 return (rf); 335 } 336 337 static __inline uint64_t 338 rdmsr(u_int msr) 339 { 340 uint32_t low, high; 341 342 __asm __volatile("rdmsr" : "=a" (low), "=d" (high) : "c" (msr)); 343 return (low | ((uint64_t)high << 32)); 344 } 345 346 static __inline uint32_t 347 rdmsr32(u_int msr) 348 { 349 uint32_t low; 350 351 __asm __volatile("rdmsr" : "=a" (low) : "c" (msr) : "rdx"); 352 return (low); 353 } 354 355 static __inline uint64_t 356 rdpmc(u_int pmc) 357 { 358 uint32_t low, high; 359 360 __asm __volatile("rdpmc" : "=a" (low), "=d" (high) : "c" (pmc)); 361 return (low | ((uint64_t)high << 32)); 362 } 363 364 static __inline uint64_t 365 rdtsc(void) 366 { 367 uint32_t low, high; 368 369 __asm __volatile("rdtsc" : "=a" (low), "=d" (high)); 370 return (low | ((uint64_t)high << 32)); 371 } 372 373 static __inline uint32_t 374 rdtsc32(void) 375 { 376 uint32_t rv; 377 378 __asm __volatile("rdtsc" : "=a" (rv) : : "edx"); 379 return (rv); 380 } 381 382 static __inline void 383 wbinvd(void) 384 { 385 __asm __volatile("wbinvd"); 386 } 387 388 static __inline void 389 write_rflags(u_long rf) 390 { 391 __asm __volatile("pushq %0; popfq" : : "r" (rf)); 392 } 393 394 static __inline void 395 wrmsr(u_int msr, uint64_t newval) 396 { 397 uint32_t low, high; 398 399 low = newval; 400 high = newval >> 32; 401 __asm __volatile("wrmsr" : : "a" (low), "d" (high), "c" (msr)); 402 } 403 404 static __inline void 405 load_cr0(u_long data) 406 { 407 408 __asm __volatile("movq %0,%%cr0" : : "r" (data)); 409 } 410 411 static __inline u_long 412 rcr0(void) 413 { 414 u_long data; 415 416 __asm __volatile("movq %%cr0,%0" : "=r" (data)); 417 return (data); 418 } 419 420 static __inline u_long 421 rcr2(void) 422 { 423 u_long data; 424 425 __asm __volatile("movq %%cr2,%0" : "=r" (data)); 426 return (data); 427 } 428 429 static __inline void 430 load_cr3(u_long data) 431 { 432 433 __asm __volatile("movq %0,%%cr3" : : "r" (data) : "memory"); 434 } 435 436 static __inline u_long 437 rcr3(void) 438 { 439 u_long data; 440 441 __asm __volatile("movq %%cr3,%0" : "=r" (data)); 442 return (data); 443 } 444 445 static __inline void 446 load_cr4(u_long data) 447 { 448 __asm __volatile("movq %0,%%cr4" : : "r" (data)); 449 } 450 451 static __inline u_long 452 rcr4(void) 453 { 454 u_long data; 455 456 __asm __volatile("movq %%cr4,%0" : "=r" (data)); 457 return (data); 458 } 459 460 static __inline u_long 461 rxcr(u_int reg) 462 { 463 u_int low, high; 464 465 __asm __volatile("xgetbv" : "=a" (low), "=d" (high) : "c" (reg)); 466 return (low | ((uint64_t)high << 32)); 467 } 468 469 static __inline void 470 load_xcr(u_int reg, u_long val) 471 { 472 u_int low, high; 473 474 low = val; 475 high = val >> 32; 476 __asm __volatile("xsetbv" : : "c" (reg), "a" (low), "d" (high)); 477 } 478 479 /* 480 * Global TLB flush (except for thise for pages marked PG_G) 481 */ 482 static __inline void 483 invltlb(void) 484 { 485 486 load_cr3(rcr3()); 487 } 488 489 #ifndef CR4_PGE 490 #define CR4_PGE 0x00000080 /* Page global enable */ 491 #endif 492 493 /* 494 * Perform the guaranteed invalidation of all TLB entries. This 495 * includes the global entries, and entries in all PCIDs, not only the 496 * current context. The function works both on non-PCID CPUs and CPUs 497 * with the PCID turned off or on. See IA-32 SDM Vol. 3a 4.10.4.1 498 * Operations that Invalidate TLBs and Paging-Structure Caches. 499 */ 500 static __inline void 501 invltlb_globpcid(void) 502 { 503 uint64_t cr4; 504 505 cr4 = rcr4(); 506 load_cr4(cr4 & ~CR4_PGE); 507 /* 508 * Although preemption at this point could be detrimental to 509 * performance, it would not lead to an error. PG_G is simply 510 * ignored if CR4.PGE is clear. Moreover, in case this block 511 * is re-entered, the load_cr4() either above or below will 512 * modify CR4.PGE flushing the TLB. 513 */ 514 load_cr4(cr4 | CR4_PGE); 515 } 516 517 /* 518 * TLB flush for an individual page (even if it has PG_G). 519 * Only works on 486+ CPUs (i386 does not have PG_G). 520 */ 521 static __inline void 522 invlpg(u_long addr) 523 { 524 525 __asm __volatile("invlpg %0" : : "m" (*(char *)addr) : "memory"); 526 } 527 528 #define INVPCID_ADDR 0 529 #define INVPCID_CTX 1 530 #define INVPCID_CTXGLOB 2 531 #define INVPCID_ALLCTX 3 532 533 struct invpcid_descr { 534 uint64_t pcid:12 __packed; 535 uint64_t pad:52 __packed; 536 uint64_t addr; 537 } __packed; 538 539 static __inline void 540 invpcid(struct invpcid_descr *d, int type) 541 { 542 543 /* invpcid (%rdx),%rax */ 544 __asm __volatile(".byte 0x66,0x0f,0x38,0x82,0x02" 545 : : "d" (d), "a" ((u_long)type) : "memory"); 546 } 547 548 static __inline u_short 549 rfs(void) 550 { 551 u_short sel; 552 __asm __volatile("movw %%fs,%0" : "=rm" (sel)); 553 return (sel); 554 } 555 556 static __inline u_short 557 rgs(void) 558 { 559 u_short sel; 560 __asm __volatile("movw %%gs,%0" : "=rm" (sel)); 561 return (sel); 562 } 563 564 static __inline u_short 565 rss(void) 566 { 567 u_short sel; 568 __asm __volatile("movw %%ss,%0" : "=rm" (sel)); 569 return (sel); 570 } 571 572 static __inline void 573 load_ds(u_short sel) 574 { 575 __asm __volatile("movw %0,%%ds" : : "rm" (sel)); 576 } 577 578 static __inline void 579 load_es(u_short sel) 580 { 581 __asm __volatile("movw %0,%%es" : : "rm" (sel)); 582 } 583 584 static __inline void 585 cpu_monitor(const void *addr, u_long extensions, u_int hints) 586 { 587 588 __asm __volatile("monitor" 589 : : "a" (addr), "c" (extensions), "d" (hints)); 590 } 591 592 static __inline void 593 cpu_mwait(u_long extensions, u_int hints) 594 { 595 596 __asm __volatile("mwait" : : "a" (hints), "c" (extensions)); 597 } 598 599 #ifdef _KERNEL 600 /* This is defined in <machine/specialreg.h> but is too painful to get to */ 601 #ifndef MSR_FSBASE 602 #define MSR_FSBASE 0xc0000100 603 #endif 604 static __inline void 605 load_fs(u_short sel) 606 { 607 /* Preserve the fsbase value across the selector load */ 608 __asm __volatile("rdmsr; movw %0,%%fs; wrmsr" 609 : : "rm" (sel), "c" (MSR_FSBASE) : "eax", "edx"); 610 } 611 612 #ifndef MSR_GSBASE 613 #define MSR_GSBASE 0xc0000101 614 #endif 615 static __inline void 616 load_gs(u_short sel) 617 { 618 /* 619 * Preserve the gsbase value across the selector load. 620 * Note that we have to disable interrupts because the gsbase 621 * being trashed happens to be the kernel gsbase at the time. 622 */ 623 __asm __volatile("pushfq; cli; rdmsr; movw %0,%%gs; wrmsr; popfq" 624 : : "rm" (sel), "c" (MSR_GSBASE) : "eax", "edx"); 625 } 626 #else 627 /* Usable by userland */ 628 static __inline void 629 load_fs(u_short sel) 630 { 631 __asm __volatile("movw %0,%%fs" : : "rm" (sel)); 632 } 633 634 static __inline void 635 load_gs(u_short sel) 636 { 637 __asm __volatile("movw %0,%%gs" : : "rm" (sel)); 638 } 639 #endif 640 641 static __inline void 642 lidt(struct region_descriptor *addr) 643 { 644 __asm __volatile("lidt (%0)" : : "r" (addr)); 645 } 646 647 static __inline void 648 lldt(u_short sel) 649 { 650 __asm __volatile("lldt %0" : : "r" (sel)); 651 } 652 653 static __inline void 654 ltr(u_short sel) 655 { 656 __asm __volatile("ltr %0" : : "r" (sel)); 657 } 658 659 static __inline uint64_t 660 rdr0(void) 661 { 662 uint64_t data; 663 __asm __volatile("movq %%dr0,%0" : "=r" (data)); 664 return (data); 665 } 666 667 static __inline void 668 load_dr0(uint64_t dr0) 669 { 670 __asm __volatile("movq %0,%%dr0" : : "r" (dr0)); 671 } 672 673 static __inline uint64_t 674 rdr1(void) 675 { 676 uint64_t data; 677 __asm __volatile("movq %%dr1,%0" : "=r" (data)); 678 return (data); 679 } 680 681 static __inline void 682 load_dr1(uint64_t dr1) 683 { 684 __asm __volatile("movq %0,%%dr1" : : "r" (dr1)); 685 } 686 687 static __inline uint64_t 688 rdr2(void) 689 { 690 uint64_t data; 691 __asm __volatile("movq %%dr2,%0" : "=r" (data)); 692 return (data); 693 } 694 695 static __inline void 696 load_dr2(uint64_t dr2) 697 { 698 __asm __volatile("movq %0,%%dr2" : : "r" (dr2)); 699 } 700 701 static __inline uint64_t 702 rdr3(void) 703 { 704 uint64_t data; 705 __asm __volatile("movq %%dr3,%0" : "=r" (data)); 706 return (data); 707 } 708 709 static __inline void 710 load_dr3(uint64_t dr3) 711 { 712 __asm __volatile("movq %0,%%dr3" : : "r" (dr3)); 713 } 714 715 static __inline uint64_t 716 rdr4(void) 717 { 718 uint64_t data; 719 __asm __volatile("movq %%dr4,%0" : "=r" (data)); 720 return (data); 721 } 722 723 static __inline void 724 load_dr4(uint64_t dr4) 725 { 726 __asm __volatile("movq %0,%%dr4" : : "r" (dr4)); 727 } 728 729 static __inline uint64_t 730 rdr5(void) 731 { 732 uint64_t data; 733 __asm __volatile("movq %%dr5,%0" : "=r" (data)); 734 return (data); 735 } 736 737 static __inline void 738 load_dr5(uint64_t dr5) 739 { 740 __asm __volatile("movq %0,%%dr5" : : "r" (dr5)); 741 } 742 743 static __inline uint64_t 744 rdr6(void) 745 { 746 uint64_t data; 747 __asm __volatile("movq %%dr6,%0" : "=r" (data)); 748 return (data); 749 } 750 751 static __inline void 752 load_dr6(uint64_t dr6) 753 { 754 __asm __volatile("movq %0,%%dr6" : : "r" (dr6)); 755 } 756 757 static __inline uint64_t 758 rdr7(void) 759 { 760 uint64_t data; 761 __asm __volatile("movq %%dr7,%0" : "=r" (data)); 762 return (data); 763 } 764 765 static __inline void 766 load_dr7(uint64_t dr7) 767 { 768 __asm __volatile("movq %0,%%dr7" : : "r" (dr7)); 769 } 770 771 static __inline register_t 772 intr_disable(void) 773 { 774 register_t rflags; 775 776 rflags = read_rflags(); 777 disable_intr(); 778 return (rflags); 779 } 780 781 static __inline void 782 intr_restore(register_t rflags) 783 { 784 write_rflags(rflags); 785 } 786 787 #else /* !(__GNUCLIKE_ASM && __CC_SUPPORTS___INLINE) */ 788 789 int breakpoint(void); 790 u_int bsfl(u_int mask); 791 u_int bsrl(u_int mask); 792 void clflush(u_long addr); 793 void clts(void); 794 void cpuid_count(u_int ax, u_int cx, u_int *p); 795 void disable_intr(void); 796 void do_cpuid(u_int ax, u_int *p); 797 void enable_intr(void); 798 void halt(void); 799 void ia32_pause(void); 800 u_char inb(u_int port); 801 u_int inl(u_int port); 802 void insb(u_int port, void *addr, size_t count); 803 void insl(u_int port, void *addr, size_t count); 804 void insw(u_int port, void *addr, size_t count); 805 register_t intr_disable(void); 806 void intr_restore(register_t rf); 807 void invd(void); 808 void invlpg(u_int addr); 809 void invltlb(void); 810 u_short inw(u_int port); 811 void lidt(struct region_descriptor *addr); 812 void lldt(u_short sel); 813 void load_cr0(u_long cr0); 814 void load_cr3(u_long cr3); 815 void load_cr4(u_long cr4); 816 void load_dr0(uint64_t dr0); 817 void load_dr1(uint64_t dr1); 818 void load_dr2(uint64_t dr2); 819 void load_dr3(uint64_t dr3); 820 void load_dr4(uint64_t dr4); 821 void load_dr5(uint64_t dr5); 822 void load_dr6(uint64_t dr6); 823 void load_dr7(uint64_t dr7); 824 void load_fs(u_short sel); 825 void load_gs(u_short sel); 826 void ltr(u_short sel); 827 void outb(u_int port, u_char data); 828 void outl(u_int port, u_int data); 829 void outsb(u_int port, const void *addr, size_t count); 830 void outsl(u_int port, const void *addr, size_t count); 831 void outsw(u_int port, const void *addr, size_t count); 832 void outw(u_int port, u_short data); 833 u_long rcr0(void); 834 u_long rcr2(void); 835 u_long rcr3(void); 836 u_long rcr4(void); 837 uint64_t rdmsr(u_int msr); 838 uint32_t rdmsr32(u_int msr); 839 uint64_t rdpmc(u_int pmc); 840 uint64_t rdr0(void); 841 uint64_t rdr1(void); 842 uint64_t rdr2(void); 843 uint64_t rdr3(void); 844 uint64_t rdr4(void); 845 uint64_t rdr5(void); 846 uint64_t rdr6(void); 847 uint64_t rdr7(void); 848 uint64_t rdtsc(void); 849 u_long read_rflags(void); 850 u_int rfs(void); 851 u_int rgs(void); 852 void wbinvd(void); 853 void write_rflags(u_int rf); 854 void wrmsr(u_int msr, uint64_t newval); 855 856 #endif /* __GNUCLIKE_ASM && __CC_SUPPORTS___INLINE */ 857 858 void reset_dbregs(void); 859 860 #ifdef _KERNEL 861 int rdmsr_safe(u_int msr, uint64_t *val); 862 int wrmsr_safe(u_int msr, uint64_t newval); 863 #endif 864 865 #endif /* !_MACHINE_CPUFUNC_H_ */ 866