1 /*- 2 * SPDX-License-Identifier: BSD-3-Clause 3 * 4 * Copyright (c) 2003 Peter Wemm. 5 * Copyright (c) 1991 Regents of the University of California. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to Berkeley by 9 * the Systems Programming Group of the University of Utah Computer 10 * Science Department and William Jolitz of UUNET Technologies Inc. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 3. Neither the name of the University nor the names of its contributors 21 * may be used to endorse or promote products derived from this software 22 * without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 27 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 * 36 * Derived from hp300 version by Mike Hibler, this version by William 37 * Jolitz uses a recursive map [a pde points to the page directory] to 38 * map the page tables using the pagetables themselves. This is done to 39 * reduce the impact on kernel virtual memory for lots of sparse address 40 * space, and to reduce the cost of memory to each process. 41 * 42 * from: hp300: @(#)pmap.h 7.2 (Berkeley) 12/16/90 43 * from: @(#)pmap.h 7.4 (Berkeley) 5/12/91 44 */ 45 46 #ifdef __i386__ 47 #include <i386/pmap.h> 48 #else /* !__i386__ */ 49 50 #ifndef _MACHINE_PMAP_H_ 51 #define _MACHINE_PMAP_H_ 52 53 /* 54 * Page-directory and page-table entries follow this format, with a few 55 * of the fields not present here and there, depending on a lot of things. 56 */ 57 /* ---- Intel Nomenclature ---- */ 58 #define X86_PG_V 0x001 /* P Valid */ 59 #define X86_PG_RW 0x002 /* R/W Read/Write */ 60 #define X86_PG_U 0x004 /* U/S User/Supervisor */ 61 #define X86_PG_NC_PWT 0x008 /* PWT Write through */ 62 #define X86_PG_NC_PCD 0x010 /* PCD Cache disable */ 63 #define X86_PG_A 0x020 /* A Accessed */ 64 #define X86_PG_M 0x040 /* D Dirty */ 65 #define X86_PG_PS 0x080 /* PS Page size (0=4k,1=2M) */ 66 #define X86_PG_PTE_PAT 0x080 /* PAT PAT index */ 67 #define X86_PG_G 0x100 /* G Global */ 68 #define X86_PG_AVAIL1 0x200 /* / Available for system */ 69 #define X86_PG_AVAIL2 0x400 /* < programmers use */ 70 #define X86_PG_AVAIL3 0x800 /* \ */ 71 #define X86_PG_PDE_PAT 0x1000 /* PAT PAT index */ 72 #define X86_PG_PKU(idx) ((pt_entry_t)idx << 59) 73 #define X86_PG_NX (1ul<<63) /* No-execute */ 74 #define X86_PG_AVAIL(x) (1ul << (x)) 75 76 /* Page level cache control fields used to determine the PAT type */ 77 #define X86_PG_PDE_CACHE (X86_PG_PDE_PAT | X86_PG_NC_PWT | X86_PG_NC_PCD) 78 #define X86_PG_PTE_CACHE (X86_PG_PTE_PAT | X86_PG_NC_PWT | X86_PG_NC_PCD) 79 80 /* Protection keys indexes */ 81 #define PMAP_MAX_PKRU_IDX 0xf 82 #define X86_PG_PKU_MASK X86_PG_PKU(PMAP_MAX_PKRU_IDX) 83 84 /* 85 * Intel extended page table (EPT) bit definitions. 86 */ 87 #define EPT_PG_READ 0x001 /* R Read */ 88 #define EPT_PG_WRITE 0x002 /* W Write */ 89 #define EPT_PG_EXECUTE 0x004 /* X Execute */ 90 #define EPT_PG_IGNORE_PAT 0x040 /* IPAT Ignore PAT */ 91 #define EPT_PG_PS 0x080 /* PS Page size */ 92 #define EPT_PG_A 0x100 /* A Accessed */ 93 #define EPT_PG_M 0x200 /* D Dirty */ 94 #define EPT_PG_MEMORY_TYPE(x) ((x) << 3) /* MT Memory Type */ 95 96 /* 97 * Define the PG_xx macros in terms of the bits on x86 PTEs. 98 */ 99 #define PG_V X86_PG_V 100 #define PG_RW X86_PG_RW 101 #define PG_U X86_PG_U 102 #define PG_NC_PWT X86_PG_NC_PWT 103 #define PG_NC_PCD X86_PG_NC_PCD 104 #define PG_A X86_PG_A 105 #define PG_M X86_PG_M 106 #define PG_PS X86_PG_PS 107 #define PG_PTE_PAT X86_PG_PTE_PAT 108 #define PG_G X86_PG_G 109 #define PG_AVAIL1 X86_PG_AVAIL1 110 #define PG_AVAIL2 X86_PG_AVAIL2 111 #define PG_AVAIL3 X86_PG_AVAIL3 112 #define PG_PDE_PAT X86_PG_PDE_PAT 113 #define PG_NX X86_PG_NX 114 #define PG_PDE_CACHE X86_PG_PDE_CACHE 115 #define PG_PTE_CACHE X86_PG_PTE_CACHE 116 117 /* Our various interpretations of the above */ 118 #define PG_W X86_PG_AVAIL3 /* "Wired" pseudoflag */ 119 #define PG_MANAGED X86_PG_AVAIL2 120 #define EPT_PG_EMUL_V X86_PG_AVAIL(52) 121 #define EPT_PG_EMUL_RW X86_PG_AVAIL(53) 122 #define PG_PROMOTED X86_PG_AVAIL(54) /* PDE only */ 123 #define PG_FRAME (0x000ffffffffff000ul) 124 #define PG_PS_FRAME (0x000fffffffe00000ul) 125 #define PG_PS_PDP_FRAME (0x000fffffc0000000ul) 126 127 /* 128 * Promotion to a 2MB (PDE) page mapping requires that the corresponding 4KB 129 * (PTE) page mappings have identical settings for the following fields: 130 */ 131 #define PG_PTE_PROMOTE (PG_NX | PG_MANAGED | PG_W | PG_G | PG_PTE_CACHE | \ 132 PG_M | PG_U | PG_RW | PG_V | PG_PKU_MASK) 133 134 /* 135 * Page Protection Exception bits 136 */ 137 138 #define PGEX_P 0x01 /* Protection violation vs. not present */ 139 #define PGEX_W 0x02 /* during a Write cycle */ 140 #define PGEX_U 0x04 /* access from User mode (UPL) */ 141 #define PGEX_RSV 0x08 /* reserved PTE field is non-zero */ 142 #define PGEX_I 0x10 /* during an instruction fetch */ 143 #define PGEX_PK 0x20 /* protection key violation */ 144 #define PGEX_SGX 0x8000 /* SGX-related */ 145 146 /* 147 * undef the PG_xx macros that define bits in the regular x86 PTEs that 148 * have a different position in nested PTEs. This is done when compiling 149 * code that needs to be aware of the differences between regular x86 and 150 * nested PTEs. 151 * 152 * The appropriate bitmask will be calculated at runtime based on the pmap 153 * type. 154 */ 155 #ifdef AMD64_NPT_AWARE 156 #undef PG_AVAIL1 /* X86_PG_AVAIL1 aliases with EPT_PG_M */ 157 #undef PG_G 158 #undef PG_A 159 #undef PG_M 160 #undef PG_PDE_PAT 161 #undef PG_PDE_CACHE 162 #undef PG_PTE_PAT 163 #undef PG_PTE_CACHE 164 #undef PG_RW 165 #undef PG_V 166 #endif 167 168 /* 169 * Pte related macros. This is complicated by having to deal with 170 * the sign extension of the 48th bit. 171 */ 172 #define KV4ADDR(l4, l3, l2, l1) ( \ 173 ((unsigned long)-1 << 47) | \ 174 ((unsigned long)(l4) << PML4SHIFT) | \ 175 ((unsigned long)(l3) << PDPSHIFT) | \ 176 ((unsigned long)(l2) << PDRSHIFT) | \ 177 ((unsigned long)(l1) << PAGE_SHIFT)) 178 #define KV5ADDR(l5, l4, l3, l2, l1) ( \ 179 ((unsigned long)-1 << 56) | \ 180 ((unsigned long)(l5) << PML5SHIFT) | \ 181 ((unsigned long)(l4) << PML4SHIFT) | \ 182 ((unsigned long)(l3) << PDPSHIFT) | \ 183 ((unsigned long)(l2) << PDRSHIFT) | \ 184 ((unsigned long)(l1) << PAGE_SHIFT)) 185 186 #define UVADDR(l5, l4, l3, l2, l1) ( \ 187 ((unsigned long)(l5) << PML5SHIFT) | \ 188 ((unsigned long)(l4) << PML4SHIFT) | \ 189 ((unsigned long)(l3) << PDPSHIFT) | \ 190 ((unsigned long)(l2) << PDRSHIFT) | \ 191 ((unsigned long)(l1) << PAGE_SHIFT)) 192 193 /* 194 * Number of kernel PML4 slots. Can be anywhere from 1 to 64 or so, 195 * but setting it larger than NDMPML4E makes no sense. 196 * 197 * Each slot provides .5 TB of kernel virtual space. 198 */ 199 #define NKPML4E 4 200 201 /* 202 * Number of PML4 slots for the KASAN shadow map. It requires 1 byte of memory 203 * for every 8 bytes of the kernel address space. 204 */ 205 #define NKASANPML4E ((NKPML4E + 7) / 8) 206 207 /* 208 * Number of PML4 slots for the KMSAN shadow and origin maps. These are 209 * one-to-one with the kernel map. 210 */ 211 #define NKMSANSHADPML4E NKPML4E 212 #define NKMSANORIGPML4E NKPML4E 213 214 /* 215 * We use the same numbering of the page table pages for 5-level and 216 * 4-level paging structures. 217 */ 218 #define NUPML5E (NPML5EPG / 2) /* number of userland PML5 219 pages */ 220 #define NUPML4E (NUPML5E * NPML4EPG) /* number of userland PML4 221 pages */ 222 #define NUPDPE (NUPML4E * NPDPEPG) /* number of userland PDP 223 pages */ 224 #define NUPDE (NUPDPE * NPDEPG) /* number of userland PD 225 entries */ 226 #define NUP4ML4E (NPML4EPG / 2) 227 228 /* 229 * NDMPML4E is the maximum number of PML4 entries that will be 230 * used to implement the direct map. It must be a power of two, 231 * and should generally exceed NKPML4E. The maximum possible 232 * value is 64; using 128 will make the direct map intrude into 233 * the recursive page table map. 234 */ 235 #define NDMPML4E 8 236 237 /* 238 * These values control the layout of virtual memory. The starting address 239 * of the direct map, which is controlled by DMPML4I, must be a multiple of 240 * its size. (See the PHYS_TO_DMAP() and DMAP_TO_PHYS() macros.) 241 * 242 * Note: KPML4I is the index of the (single) level 4 page that maps 243 * the KVA that holds KERNBASE, while KPML4BASE is the index of the 244 * first level 4 page that maps VM_MIN_KERNEL_ADDRESS. If NKPML4E 245 * is 1, these are the same, otherwise KPML4BASE < KPML4I and extra 246 * level 4 PDEs are needed to map from VM_MIN_KERNEL_ADDRESS up to 247 * KERNBASE. 248 * 249 * (KPML4I combines with KPDPI to choose where KERNBASE starts. 250 * Or, in other words, KPML4I provides bits 39..47 of KERNBASE, 251 * and KPDPI provides bits 30..38.) 252 */ 253 #define PML4PML4I (NPML4EPG / 2) /* Index of recursive pml4 mapping */ 254 #define PML5PML5I (NPML5EPG / 2) /* Index of recursive pml5 mapping */ 255 256 #define KPML4BASE (NPML4EPG-NKPML4E) /* KVM at highest addresses */ 257 #define DMPML4I rounddown(KPML4BASE-NDMPML4E, NDMPML4E) /* Below KVM */ 258 259 #define KPML4I (NPML4EPG-1) 260 #define KPDPI (NPDPEPG-2) /* kernbase at -2GB */ 261 262 #define KASANPML4I (DMPML4I - NKASANPML4E) /* Below the direct map */ 263 264 #define KMSANSHADPML4I (KPML4BASE - NKMSANSHADPML4E) 265 #define KMSANORIGPML4I (DMPML4I - NKMSANORIGPML4E) 266 267 /* Large map: index of the first and max last pml4 entry */ 268 #define LMSPML4I (PML4PML4I + 1) 269 #define LMEPML4I (KASANPML4I - 1) 270 271 /* 272 * XXX doesn't really belong here I guess... 273 */ 274 #define ISA_HOLE_START 0xa0000 275 #define ISA_HOLE_LENGTH (0x100000-ISA_HOLE_START) 276 277 #define PMAP_PCID_NONE 0xffffffff 278 #define PMAP_PCID_KERN 0 279 #define PMAP_PCID_OVERMAX 0x1000 280 #define PMAP_PCID_OVERMAX_KERN 0x800 281 #define PMAP_PCID_USER_PT 0x800 282 283 #define PMAP_NO_CR3 0xffffffffffffffff 284 #define PMAP_UCR3_NOMASK 0xffffffffffffffff 285 286 #ifndef LOCORE 287 288 #include <sys/kassert.h> 289 #include <sys/queue.h> 290 #include <sys/_cpuset.h> 291 #include <sys/_lock.h> 292 #include <sys/_mutex.h> 293 #include <sys/_pctrie.h> 294 #include <machine/_pmap.h> 295 #include <sys/_pv_entry.h> 296 #include <sys/_rangeset.h> 297 #include <sys/_smr.h> 298 299 #include <vm/_vm_radix.h> 300 301 typedef u_int64_t pd_entry_t; 302 typedef u_int64_t pt_entry_t; 303 typedef u_int64_t pdp_entry_t; 304 typedef u_int64_t pml4_entry_t; 305 typedef u_int64_t pml5_entry_t; 306 307 /* 308 * Address of current address space page table maps and directories. 309 */ 310 #ifdef _KERNEL 311 #define addr_P4Tmap (KV4ADDR(PML4PML4I, 0, 0, 0)) 312 #define addr_P4Dmap (KV4ADDR(PML4PML4I, PML4PML4I, 0, 0)) 313 #define addr_P4DPmap (KV4ADDR(PML4PML4I, PML4PML4I, PML4PML4I, 0)) 314 #define addr_P4ML4map (KV4ADDR(PML4PML4I, PML4PML4I, PML4PML4I, PML4PML4I)) 315 #define addr_P4ML4pml4e (addr_PML4map + (PML4PML4I * sizeof(pml4_entry_t))) 316 #define P4Tmap ((pt_entry_t *)(addr_P4Tmap)) 317 #define P4Dmap ((pd_entry_t *)(addr_P4Dmap)) 318 319 #define addr_P5Tmap (KV5ADDR(PML5PML5I, 0, 0, 0, 0)) 320 #define addr_P5Dmap (KV5ADDR(PML5PML5I, PML5PML5I, 0, 0, 0)) 321 #define addr_P5DPmap (KV5ADDR(PML5PML5I, PML5PML5I, PML5PML5I, 0, 0)) 322 #define addr_P5ML4map (KV5ADDR(PML5PML5I, PML5PML5I, PML5PML5I, PML5PML5I, 0)) 323 #define addr_P5ML5map \ 324 (KVADDR(PML5PML5I, PML5PML5I, PML5PML5I, PML5PML5I, PML5PML5I)) 325 #define addr_P5ML5pml5e (addr_P5ML5map + (PML5PML5I * sizeof(pml5_entry_t))) 326 #define P5Tmap ((pt_entry_t *)(addr_P5Tmap)) 327 #define P5Dmap ((pd_entry_t *)(addr_P5Dmap)) 328 329 extern int nkpt; /* Initial number of kernel page tables */ 330 extern u_int64_t KPML4phys; /* physical address of kernel level 4 */ 331 extern u_int64_t KPML5phys; /* physical address of kernel level 5 */ 332 333 /* 334 * virtual address to page table entry and 335 * to physical address. 336 * Note: these work recursively, thus vtopte of a pte will give 337 * the corresponding pde that in turn maps it. 338 */ 339 pt_entry_t *vtopte(vm_offset_t); 340 #define vtophys(va) pmap_kextract(((vm_offset_t) (va))) 341 342 #define pte_load_store(ptep, pte) atomic_swap_long(ptep, pte) 343 #define pte_load_clear(ptep) atomic_swap_long(ptep, 0) 344 #define pte_store(ptep, pte) do { \ 345 *(u_long *)(ptep) = (u_long)(pte); \ 346 } while (0) 347 #define pte_clear(ptep) pte_store(ptep, 0) 348 349 #define pde_store(pdep, pde) pte_store(pdep, pde) 350 351 extern pt_entry_t pg_nx; 352 353 #endif /* _KERNEL */ 354 355 /* 356 * Pmap stuff 357 */ 358 359 /* 360 * Locks 361 * (p) PV list lock 362 */ 363 struct md_page { 364 TAILQ_HEAD(, pv_entry) pv_list; /* (p) */ 365 int pv_gen; /* (p) */ 366 int pat_mode; 367 }; 368 369 enum pmap_type { 370 PT_X86, /* regular x86 page tables */ 371 PT_EPT, /* Intel's nested page tables */ 372 PT_RVI, /* AMD's nested page tables */ 373 }; 374 375 /* 376 * The kernel virtual address (KVA) of the level 4 page table page is always 377 * within the direct map (DMAP) region. 378 */ 379 struct pmap { 380 struct mtx pm_mtx; 381 pml4_entry_t *pm_pmltop; /* KVA of top level page table */ 382 pml4_entry_t *pm_pmltopu; /* KVA of user top page table */ 383 uint64_t pm_cr3; 384 uint64_t pm_ucr3; 385 TAILQ_HEAD(,pv_chunk) pm_pvchunk; /* list of mappings in pmap */ 386 cpuset_t pm_active; /* active on cpus */ 387 enum pmap_type pm_type; /* regular or nested tables */ 388 struct pmap_statistics pm_stats; /* pmap statistics */ 389 struct vm_radix pm_root; /* spare page table pages */ 390 long pm_eptgen; /* EPT pmap generation id */ 391 smr_t pm_eptsmr; 392 int pm_flags; 393 struct pmap_pcid *pm_pcidp; 394 struct rangeset pm_pkru; 395 }; 396 397 /* flags */ 398 #define PMAP_NESTED_IPIMASK 0xff 399 #define PMAP_PDE_SUPERPAGE (1 << 8) /* supports 2MB superpages */ 400 #define PMAP_EMULATE_AD_BITS (1 << 9) /* needs A/D bits emulation */ 401 #define PMAP_SUPPORTS_EXEC_ONLY (1 << 10) /* execute only mappings ok */ 402 403 typedef struct pmap *pmap_t; 404 405 #ifdef _KERNEL 406 extern struct pmap kernel_pmap_store; 407 #define kernel_pmap (&kernel_pmap_store) 408 409 #define PMAP_LOCK(pmap) mtx_lock(&(pmap)->pm_mtx) 410 #define PMAP_LOCK_ASSERT(pmap, type) \ 411 mtx_assert(&(pmap)->pm_mtx, (type)) 412 #define PMAP_LOCK_DESTROY(pmap) mtx_destroy(&(pmap)->pm_mtx) 413 #define PMAP_LOCK_INIT(pmap) mtx_init(&(pmap)->pm_mtx, "pmap", \ 414 NULL, MTX_DEF | MTX_DUPOK) 415 #define PMAP_LOCKED(pmap) mtx_owned(&(pmap)->pm_mtx) 416 #define PMAP_MTX(pmap) (&(pmap)->pm_mtx) 417 #define PMAP_TRYLOCK(pmap) mtx_trylock(&(pmap)->pm_mtx) 418 #define PMAP_UNLOCK(pmap) mtx_unlock(&(pmap)->pm_mtx) 419 420 int pmap_pinit_type(pmap_t pmap, enum pmap_type pm_type, int flags); 421 int pmap_emulate_accessed_dirty(pmap_t pmap, vm_offset_t va, int ftype); 422 423 extern caddr_t CADDR1; 424 extern pt_entry_t *CMAP1; 425 extern vm_offset_t virtual_avail; 426 extern vm_offset_t virtual_end; 427 extern vm_paddr_t dmaplimit; 428 extern int pmap_pcid_enabled; 429 extern int invpcid_works; 430 extern int pmap_pcid_invlpg_workaround; 431 extern int pmap_pcid_invlpg_workaround_uena; 432 433 #define pmap_page_get_memattr(m) ((vm_memattr_t)(m)->md.pat_mode) 434 #define pmap_page_is_write_mapped(m) (((m)->a.flags & PGA_WRITEABLE) != 0) 435 #define pmap_unmapbios(va, sz) pmap_unmapdev((va), (sz)) 436 437 #define pmap_vm_page_alloc_check(m) \ 438 KASSERT(m->phys_addr < kernphys || \ 439 m->phys_addr >= kernphys + (vm_offset_t)&_end - KERNSTART, \ 440 ("allocating kernel page %p pa %#lx kernphys %#lx end %p", \ 441 m, m->phys_addr, kernphys, &_end)); 442 443 struct thread; 444 445 void pmap_activate_boot(pmap_t pmap); 446 void pmap_activate_sw(struct thread *); 447 void pmap_allow_2m_x_ept_recalculate(void); 448 void pmap_bootstrap(vm_paddr_t *); 449 int pmap_cache_bits(pmap_t pmap, int mode, boolean_t is_pde); 450 int pmap_change_attr(vm_offset_t, vm_size_t, int); 451 int pmap_change_prot(vm_offset_t, vm_size_t, vm_prot_t); 452 void pmap_demote_DMAP(vm_paddr_t base, vm_size_t len, boolean_t invalidate); 453 void pmap_flush_cache_range(vm_offset_t, vm_offset_t); 454 void pmap_flush_cache_phys_range(vm_paddr_t, vm_paddr_t, vm_memattr_t); 455 void pmap_init_pat(void); 456 void pmap_kenter(vm_offset_t va, vm_paddr_t pa); 457 void *pmap_kenter_temporary(vm_paddr_t pa, int i); 458 vm_paddr_t pmap_kextract(vm_offset_t); 459 void pmap_kremove(vm_offset_t); 460 int pmap_large_map(vm_paddr_t, vm_size_t, void **, vm_memattr_t); 461 void pmap_large_map_wb(void *sva, vm_size_t len); 462 void pmap_large_unmap(void *sva, vm_size_t len); 463 void *pmap_mapbios(vm_paddr_t, vm_size_t); 464 void *pmap_mapdev(vm_paddr_t, vm_size_t); 465 void *pmap_mapdev_attr(vm_paddr_t, vm_size_t, int); 466 void *pmap_mapdev_pciecfg(vm_paddr_t pa, vm_size_t size); 467 bool pmap_not_in_di(void); 468 boolean_t pmap_page_is_mapped(vm_page_t m); 469 void pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma); 470 void pmap_page_set_memattr_noflush(vm_page_t m, vm_memattr_t ma); 471 void pmap_pinit_pml4(vm_page_t); 472 void pmap_pinit_pml5(vm_page_t); 473 bool pmap_ps_enabled(pmap_t pmap); 474 void pmap_unmapdev(void *, vm_size_t); 475 void pmap_invalidate_page(pmap_t, vm_offset_t); 476 void pmap_invalidate_range(pmap_t, vm_offset_t, vm_offset_t); 477 void pmap_invalidate_all(pmap_t); 478 void pmap_invalidate_cache(void); 479 void pmap_invalidate_cache_pages(vm_page_t *pages, int count); 480 void pmap_invalidate_cache_range(vm_offset_t sva, vm_offset_t eva); 481 void pmap_force_invalidate_cache_range(vm_offset_t sva, vm_offset_t eva); 482 void pmap_get_mapping(pmap_t pmap, vm_offset_t va, uint64_t *ptr, int *num); 483 bool pmap_map_io_transient(vm_page_t *, vm_offset_t *, int, bool); 484 void pmap_unmap_io_transient(vm_page_t *, vm_offset_t *, int, bool); 485 void pmap_map_delete(pmap_t, vm_offset_t, vm_offset_t); 486 void pmap_pti_add_kva(vm_offset_t sva, vm_offset_t eva, bool exec); 487 void pmap_pti_remove_kva(vm_offset_t sva, vm_offset_t eva); 488 void pmap_pti_pcid_invalidate(uint64_t ucr3, uint64_t kcr3); 489 void pmap_pti_pcid_invlpg(uint64_t ucr3, uint64_t kcr3, vm_offset_t va); 490 void pmap_pti_pcid_invlrng(uint64_t ucr3, uint64_t kcr3, vm_offset_t sva, 491 vm_offset_t eva); 492 int pmap_pkru_clear(pmap_t pmap, vm_offset_t sva, vm_offset_t eva); 493 int pmap_pkru_set(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, 494 u_int keyidx, int flags); 495 void pmap_thread_init_invl_gen(struct thread *td); 496 int pmap_vmspace_copy(pmap_t dst_pmap, pmap_t src_pmap); 497 void pmap_page_array_startup(long count); 498 vm_page_t pmap_page_alloc_below_4g(bool zeroed); 499 500 #if defined(KASAN) || defined(KMSAN) 501 void pmap_san_bootstrap(void); 502 void pmap_san_enter(vm_offset_t); 503 #endif 504 505 /* 506 * Returns a pointer to a set of CPUs on which the pmap is currently active. 507 * Note that the set can be modified without any mutual exclusion, so a copy 508 * must be made if a stable value is required. 509 */ 510 static __inline volatile cpuset_t * 511 pmap_invalidate_cpu_mask(pmap_t pmap) 512 { 513 return (&pmap->pm_active); 514 } 515 516 #if defined(_SYS_PCPU_H_) && defined(_MACHINE_CPUFUNC_H_) 517 /* 518 * It seems that AlderLake+ small cores have some microarchitectural 519 * bug, which results in the INVLPG instruction failing to flush all 520 * global TLB entries when PCID is enabled. Work around it for now, 521 * by doing global invalidation on small cores instead of INVLPG. 522 */ 523 static __inline void 524 pmap_invlpg(pmap_t pmap, vm_offset_t va) 525 { 526 if (pmap == kernel_pmap && PCPU_GET(pcid_invlpg_workaround)) { 527 struct invpcid_descr d = { 0 }; 528 529 invpcid(&d, INVPCID_CTXGLOB); 530 } else { 531 invlpg(va); 532 } 533 } 534 #endif /* sys/pcpu.h && machine/cpufunc.h */ 535 536 #if defined(_SYS_PCPU_H_) 537 /* Return pcid for the pmap pmap on current cpu */ 538 static __inline uint32_t 539 pmap_get_pcid(pmap_t pmap) 540 { 541 struct pmap_pcid *pcidp; 542 543 MPASS(pmap_pcid_enabled); 544 pcidp = zpcpu_get(pmap->pm_pcidp); 545 return (pcidp->pm_pcid); 546 } 547 #endif /* sys/pcpu.h */ 548 549 #endif /* _KERNEL */ 550 551 /* Return various clipped indexes for a given VA */ 552 static __inline vm_pindex_t 553 pmap_pte_index(vm_offset_t va) 554 { 555 556 return ((va >> PAGE_SHIFT) & ((1ul << NPTEPGSHIFT) - 1)); 557 } 558 559 static __inline vm_pindex_t 560 pmap_pde_index(vm_offset_t va) 561 { 562 563 return ((va >> PDRSHIFT) & ((1ul << NPDEPGSHIFT) - 1)); 564 } 565 566 static __inline vm_pindex_t 567 pmap_pdpe_index(vm_offset_t va) 568 { 569 570 return ((va >> PDPSHIFT) & ((1ul << NPDPEPGSHIFT) - 1)); 571 } 572 573 static __inline vm_pindex_t 574 pmap_pml4e_index(vm_offset_t va) 575 { 576 577 return ((va >> PML4SHIFT) & ((1ul << NPML4EPGSHIFT) - 1)); 578 } 579 580 static __inline vm_pindex_t 581 pmap_pml5e_index(vm_offset_t va) 582 { 583 584 return ((va >> PML5SHIFT) & ((1ul << NPML5EPGSHIFT) - 1)); 585 } 586 587 #endif /* !LOCORE */ 588 589 #endif /* !_MACHINE_PMAP_H_ */ 590 591 #endif /* __i386__ */ 592