1 /*- 2 * Copyright (c) 1991 The Regents of the University of California. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 4. Neither the name of the University nor the names of its contributors 14 * may be used to endorse or promote products derived from this software 15 * without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * from: @(#)specialreg.h 7.1 (Berkeley) 5/9/91 30 * $FreeBSD$ 31 */ 32 33 #ifndef _MACHINE_SPECIALREG_H_ 34 #define _MACHINE_SPECIALREG_H_ 35 36 /* 37 * Bits in 386 special registers: 38 */ 39 #define CR0_PE 0x00000001 /* Protected mode Enable */ 40 #define CR0_MP 0x00000002 /* "Math" (fpu) Present */ 41 #define CR0_EM 0x00000004 /* EMulate FPU instructions. (trap ESC only) */ 42 #define CR0_TS 0x00000008 /* Task Switched (if MP, trap ESC and WAIT) */ 43 #define CR0_PG 0x80000000 /* PaGing enable */ 44 45 /* 46 * Bits in 486 special registers: 47 */ 48 #define CR0_NE 0x00000020 /* Numeric Error enable (EX16 vs IRQ13) */ 49 #define CR0_WP 0x00010000 /* Write Protect (honor page protect in 50 all modes) */ 51 #define CR0_AM 0x00040000 /* Alignment Mask (set to enable AC flag) */ 52 #define CR0_NW 0x20000000 /* Not Write-through */ 53 #define CR0_CD 0x40000000 /* Cache Disable */ 54 55 /* 56 * Bits in PPro special registers 57 */ 58 #define CR4_VME 0x00000001 /* Virtual 8086 mode extensions */ 59 #define CR4_PVI 0x00000002 /* Protected-mode virtual interrupts */ 60 #define CR4_TSD 0x00000004 /* Time stamp disable */ 61 #define CR4_DE 0x00000008 /* Debugging extensions */ 62 #define CR4_PSE 0x00000010 /* Page size extensions */ 63 #define CR4_PAE 0x00000020 /* Physical address extension */ 64 #define CR4_MCE 0x00000040 /* Machine check enable */ 65 #define CR4_PGE 0x00000080 /* Page global enable */ 66 #define CR4_PCE 0x00000100 /* Performance monitoring counter enable */ 67 #define CR4_FXSR 0x00000200 /* Fast FPU save/restore used by OS */ 68 #define CR4_XMM 0x00000400 /* enable SIMD/MMX2 to use except 16 */ 69 70 /* 71 * Bits in AMD64 special registers. EFER is 64 bits wide. 72 */ 73 #define EFER_SCE 0x000000001 /* System Call Extensions (R/W) */ 74 #define EFER_LME 0x000000100 /* Long mode enable (R/W) */ 75 #define EFER_LMA 0x000000400 /* Long mode active (R) */ 76 #define EFER_NXE 0x000000800 /* PTE No-Execute bit enable (R/W) */ 77 78 /* 79 * CPUID instruction features register 80 */ 81 #define CPUID_FPU 0x00000001 82 #define CPUID_VME 0x00000002 83 #define CPUID_DE 0x00000004 84 #define CPUID_PSE 0x00000008 85 #define CPUID_TSC 0x00000010 86 #define CPUID_MSR 0x00000020 87 #define CPUID_PAE 0x00000040 88 #define CPUID_MCE 0x00000080 89 #define CPUID_CX8 0x00000100 90 #define CPUID_APIC 0x00000200 91 #define CPUID_B10 0x00000400 92 #define CPUID_SEP 0x00000800 93 #define CPUID_MTRR 0x00001000 94 #define CPUID_PGE 0x00002000 95 #define CPUID_MCA 0x00004000 96 #define CPUID_CMOV 0x00008000 97 #define CPUID_PAT 0x00010000 98 #define CPUID_PSE36 0x00020000 99 #define CPUID_PSN 0x00040000 100 #define CPUID_CLFSH 0x00080000 101 #define CPUID_B20 0x00100000 102 #define CPUID_DS 0x00200000 103 #define CPUID_ACPI 0x00400000 104 #define CPUID_MMX 0x00800000 105 #define CPUID_FXSR 0x01000000 106 #define CPUID_SSE 0x02000000 107 #define CPUID_XMM 0x02000000 108 #define CPUID_SSE2 0x04000000 109 #define CPUID_SS 0x08000000 110 #define CPUID_HTT 0x10000000 111 #define CPUID_TM 0x20000000 112 #define CPUID_IA64 0x40000000 113 #define CPUID_PBE 0x80000000 114 115 #define CPUID2_SSE3 0x00000001 116 #define CPUID2_DTES64 0x00000004 117 #define CPUID2_MON 0x00000008 118 #define CPUID2_DS_CPL 0x00000010 119 #define CPUID2_VMX 0x00000020 120 #define CPUID2_SMX 0x00000040 121 #define CPUID2_EST 0x00000080 122 #define CPUID2_TM2 0x00000100 123 #define CPUID2_SSSE3 0x00000200 124 #define CPUID2_CNXTID 0x00000400 125 #define CPUID2_CX16 0x00002000 126 #define CPUID2_XTPR 0x00004000 127 #define CPUID2_PDCM 0x00008000 128 #define CPUID2_DCA 0x00040000 129 #define CPUID2_SSE41 0x00080000 130 #define CPUID2_SSE42 0x00100000 131 #define CPUID2_X2APIC 0x00200000 132 #define CPUID2_POPCNT 0x00800000 133 134 /* 135 * Important bits in the AMD extended cpuid flags 136 */ 137 #define AMDID_SYSCALL 0x00000800 138 #define AMDID_MP 0x00080000 139 #define AMDID_NX 0x00100000 140 #define AMDID_EXT_MMX 0x00400000 141 #define AMDID_FFXSR 0x01000000 142 #define AMDID_PAGE1GB 0x04000000 143 #define AMDID_RDTSCP 0x08000000 144 #define AMDID_LM 0x20000000 145 #define AMDID_EXT_3DNOW 0x40000000 146 #define AMDID_3DNOW 0x80000000 147 148 #define AMDID2_LAHF 0x00000001 149 #define AMDID2_CMP 0x00000002 150 #define AMDID2_SVM 0x00000004 151 #define AMDID2_EXT_APIC 0x00000008 152 #define AMDID2_CR8 0x00000010 153 #define AMDID2_PREFETCH 0x00000100 154 155 /* 156 * CPUID instruction 1 eax info 157 */ 158 #define CPUID_STEPPING 0x0000000f 159 #define CPUID_MODEL 0x000000f0 160 #define CPUID_FAMILY 0x00000f00 161 #define CPUID_EXT_MODEL 0x000f0000 162 #define CPUID_EXT_FAMILY 0x0ff00000 163 #define AMD64_CPU_MODEL(id) \ 164 ((((id) & CPUID_MODEL) >> 4) | \ 165 (((id) & CPUID_EXT_MODEL) >> 12)) 166 #define AMD64_CPU_FAMILY(id) \ 167 ((((id) & CPUID_FAMILY) >> 8) + \ 168 (((id) & CPUID_EXT_FAMILY) >> 20)) 169 170 /* 171 * CPUID instruction 1 ebx info 172 */ 173 #define CPUID_BRAND_INDEX 0x000000ff 174 #define CPUID_CLFUSH_SIZE 0x0000ff00 175 #define CPUID_HTT_CORES 0x00ff0000 176 #define CPUID_LOCAL_APIC_ID 0xff000000 177 178 /* 179 * AMD extended function 8000_0007h edx info 180 */ 181 #define AMDPM_TS 0x00000001 182 #define AMDPM_FID 0x00000002 183 #define AMDPM_VID 0x00000004 184 #define AMDPM_TTP 0x00000008 185 #define AMDPM_TM 0x00000010 186 #define AMDPM_STC 0x00000020 187 #define AMDPM_100MHZ_STEPS 0x00000040 188 #define AMDPM_HW_PSTATE 0x00000080 189 #define AMDPM_TSC_INVARIANT 0x00000100 190 191 /* 192 * AMD extended function 8000_0008h ecx info 193 */ 194 #define AMDID_CMP_CORES 0x000000ff 195 196 /* 197 * CPUID manufacturers identifiers 198 */ 199 #define AMD_VENDOR_ID "AuthenticAMD" 200 #define INTEL_VENDOR_ID "GenuineIntel" 201 202 /* 203 * Model-specific registers for the i386 family 204 */ 205 #define MSR_P5_MC_ADDR 0x000 206 #define MSR_P5_MC_TYPE 0x001 207 #define MSR_TSC 0x010 208 #define MSR_P5_CESR 0x011 209 #define MSR_P5_CTR0 0x012 210 #define MSR_P5_CTR1 0x013 211 #define MSR_IA32_PLATFORM_ID 0x017 212 #define MSR_APICBASE 0x01b 213 #define MSR_EBL_CR_POWERON 0x02a 214 #define MSR_TEST_CTL 0x033 215 #define MSR_BIOS_UPDT_TRIG 0x079 216 #define MSR_BBL_CR_D0 0x088 217 #define MSR_BBL_CR_D1 0x089 218 #define MSR_BBL_CR_D2 0x08a 219 #define MSR_BIOS_SIGN 0x08b 220 #define MSR_PERFCTR0 0x0c1 221 #define MSR_PERFCTR1 0x0c2 222 #define MSR_IA32_EXT_CONFIG 0x0ee /* Undocumented. Core Solo/Duo only */ 223 #define MSR_MTRRcap 0x0fe 224 #define MSR_BBL_CR_ADDR 0x116 225 #define MSR_BBL_CR_DECC 0x118 226 #define MSR_BBL_CR_CTL 0x119 227 #define MSR_BBL_CR_TRIG 0x11a 228 #define MSR_BBL_CR_BUSY 0x11b 229 #define MSR_BBL_CR_CTL3 0x11e 230 #define MSR_SYSENTER_CS_MSR 0x174 231 #define MSR_SYSENTER_ESP_MSR 0x175 232 #define MSR_SYSENTER_EIP_MSR 0x176 233 #define MSR_MCG_CAP 0x179 234 #define MSR_MCG_STATUS 0x17a 235 #define MSR_MCG_CTL 0x17b 236 #define MSR_EVNTSEL0 0x186 237 #define MSR_EVNTSEL1 0x187 238 #define MSR_THERM_CONTROL 0x19a 239 #define MSR_THERM_INTERRUPT 0x19b 240 #define MSR_THERM_STATUS 0x19c 241 #define MSR_IA32_MISC_ENABLE 0x1a0 242 #define MSR_DEBUGCTLMSR 0x1d9 243 #define MSR_LASTBRANCHFROMIP 0x1db 244 #define MSR_LASTBRANCHTOIP 0x1dc 245 #define MSR_LASTINTFROMIP 0x1dd 246 #define MSR_LASTINTTOIP 0x1de 247 #define MSR_ROB_CR_BKUPTMPDR6 0x1e0 248 #define MSR_MTRRVarBase 0x200 249 #define MSR_MTRR64kBase 0x250 250 #define MSR_MTRR16kBase 0x258 251 #define MSR_MTRR4kBase 0x268 252 #define MSR_PAT 0x277 253 #define MSR_MTRRdefType 0x2ff 254 #define MSR_MC0_CTL 0x400 255 #define MSR_MC0_STATUS 0x401 256 #define MSR_MC0_ADDR 0x402 257 #define MSR_MC0_MISC 0x403 258 #define MSR_MC1_CTL 0x404 259 #define MSR_MC1_STATUS 0x405 260 #define MSR_MC1_ADDR 0x406 261 #define MSR_MC1_MISC 0x407 262 #define MSR_MC2_CTL 0x408 263 #define MSR_MC2_STATUS 0x409 264 #define MSR_MC2_ADDR 0x40a 265 #define MSR_MC2_MISC 0x40b 266 #define MSR_MC3_CTL 0x40c 267 #define MSR_MC3_STATUS 0x40d 268 #define MSR_MC3_ADDR 0x40e 269 #define MSR_MC3_MISC 0x40f 270 #define MSR_MC4_CTL 0x410 271 #define MSR_MC4_STATUS 0x411 272 #define MSR_MC4_ADDR 0x412 273 #define MSR_MC4_MISC 0x413 274 275 /* 276 * Constants related to MSR's. 277 */ 278 #define APICBASE_RESERVED 0x000006ff 279 #define APICBASE_BSP 0x00000100 280 #define APICBASE_ENABLED 0x00000800 281 #define APICBASE_ADDRESS 0xfffff000 282 283 /* 284 * PAT modes. 285 */ 286 #define PAT_UNCACHEABLE 0x00 287 #define PAT_WRITE_COMBINING 0x01 288 #define PAT_WRITE_THROUGH 0x04 289 #define PAT_WRITE_PROTECTED 0x05 290 #define PAT_WRITE_BACK 0x06 291 #define PAT_UNCACHED 0x07 292 #define PAT_VALUE(i, m) ((long)(m) << (8 * (i))) 293 #define PAT_MASK(i) PAT_VALUE(i, 0xff) 294 295 /* 296 * Constants related to MTRRs 297 */ 298 #define MTRR_UNCACHEABLE 0x00 299 #define MTRR_WRITE_COMBINING 0x01 300 #define MTRR_WRITE_THROUGH 0x04 301 #define MTRR_WRITE_PROTECTED 0x05 302 #define MTRR_WRITE_BACK 0x06 303 #define MTRR_N64K 8 /* numbers of fixed-size entries */ 304 #define MTRR_N16K 16 305 #define MTRR_N4K 64 306 #define MTRR_CAP_WC 0x0000000000000400UL 307 #define MTRR_CAP_FIXED 0x0000000000000100UL 308 #define MTRR_CAP_VCNT 0x00000000000000ffUL 309 #define MTRR_DEF_ENABLE 0x0000000000000800UL 310 #define MTRR_DEF_FIXED_ENABLE 0x0000000000000400UL 311 #define MTRR_DEF_TYPE 0x00000000000000ffUL 312 #define MTRR_PHYSBASE_PHYSBASE 0x000ffffffffff000UL 313 #define MTRR_PHYSBASE_TYPE 0x00000000000000ffUL 314 #define MTRR_PHYSMASK_PHYSMASK 0x000ffffffffff000UL 315 #define MTRR_PHYSMASK_VALID 0x0000000000000800UL 316 317 /* Performance Control Register (5x86 only). */ 318 #define PCR0 0x20 319 #define PCR0_RSTK 0x01 /* Enables return stack */ 320 #define PCR0_BTB 0x02 /* Enables branch target buffer */ 321 #define PCR0_LOOP 0x04 /* Enables loop */ 322 #define PCR0_AIS 0x08 /* Enables all instrcutions stalled to 323 serialize pipe. */ 324 #define PCR0_MLR 0x10 /* Enables reordering of misaligned loads */ 325 #define PCR0_BTBRT 0x40 /* Enables BTB test register. */ 326 #define PCR0_LSSER 0x80 /* Disable reorder */ 327 328 /* Device Identification Registers */ 329 #define DIR0 0xfe 330 #define DIR1 0xff 331 332 /* 333 * The following four 3-byte registers control the non-cacheable regions. 334 * These registers must be written as three separate bytes. 335 * 336 * NCRx+0: A31-A24 of starting address 337 * NCRx+1: A23-A16 of starting address 338 * NCRx+2: A15-A12 of starting address | NCR_SIZE_xx. 339 * 340 * The non-cacheable region's starting address must be aligned to the 341 * size indicated by the NCR_SIZE_xx field. 342 */ 343 #define NCR1 0xc4 344 #define NCR2 0xc7 345 #define NCR3 0xca 346 #define NCR4 0xcd 347 348 #define NCR_SIZE_0K 0 349 #define NCR_SIZE_4K 1 350 #define NCR_SIZE_8K 2 351 #define NCR_SIZE_16K 3 352 #define NCR_SIZE_32K 4 353 #define NCR_SIZE_64K 5 354 #define NCR_SIZE_128K 6 355 #define NCR_SIZE_256K 7 356 #define NCR_SIZE_512K 8 357 #define NCR_SIZE_1M 9 358 #define NCR_SIZE_2M 10 359 #define NCR_SIZE_4M 11 360 #define NCR_SIZE_8M 12 361 #define NCR_SIZE_16M 13 362 #define NCR_SIZE_32M 14 363 #define NCR_SIZE_4G 15 364 365 /* 366 * The address region registers are used to specify the location and 367 * size for the eight address regions. 368 * 369 * ARRx + 0: A31-A24 of start address 370 * ARRx + 1: A23-A16 of start address 371 * ARRx + 2: A15-A12 of start address | ARR_SIZE_xx 372 */ 373 #define ARR0 0xc4 374 #define ARR1 0xc7 375 #define ARR2 0xca 376 #define ARR3 0xcd 377 #define ARR4 0xd0 378 #define ARR5 0xd3 379 #define ARR6 0xd6 380 #define ARR7 0xd9 381 382 #define ARR_SIZE_0K 0 383 #define ARR_SIZE_4K 1 384 #define ARR_SIZE_8K 2 385 #define ARR_SIZE_16K 3 386 #define ARR_SIZE_32K 4 387 #define ARR_SIZE_64K 5 388 #define ARR_SIZE_128K 6 389 #define ARR_SIZE_256K 7 390 #define ARR_SIZE_512K 8 391 #define ARR_SIZE_1M 9 392 #define ARR_SIZE_2M 10 393 #define ARR_SIZE_4M 11 394 #define ARR_SIZE_8M 12 395 #define ARR_SIZE_16M 13 396 #define ARR_SIZE_32M 14 397 #define ARR_SIZE_4G 15 398 399 /* 400 * The region control registers specify the attributes associated with 401 * the ARRx addres regions. 402 */ 403 #define RCR0 0xdc 404 #define RCR1 0xdd 405 #define RCR2 0xde 406 #define RCR3 0xdf 407 #define RCR4 0xe0 408 #define RCR5 0xe1 409 #define RCR6 0xe2 410 #define RCR7 0xe3 411 412 #define RCR_RCD 0x01 /* Disables caching for ARRx (x = 0-6). */ 413 #define RCR_RCE 0x01 /* Enables caching for ARR7. */ 414 #define RCR_WWO 0x02 /* Weak write ordering. */ 415 #define RCR_WL 0x04 /* Weak locking. */ 416 #define RCR_WG 0x08 /* Write gathering. */ 417 #define RCR_WT 0x10 /* Write-through. */ 418 #define RCR_NLB 0x20 /* LBA# pin is not asserted. */ 419 420 /* AMD Write Allocate Top-Of-Memory and Control Register */ 421 #define AMD_WT_ALLOC_TME 0x40000 /* top-of-memory enable */ 422 #define AMD_WT_ALLOC_PRE 0x20000 /* programmable range enable */ 423 #define AMD_WT_ALLOC_FRE 0x10000 /* fixed (A0000-FFFFF) range enable */ 424 425 /* AMD64 MSR's */ 426 #define MSR_EFER 0xc0000080 /* extended features */ 427 #define MSR_STAR 0xc0000081 /* legacy mode SYSCALL target/cs/ss */ 428 #define MSR_LSTAR 0xc0000082 /* long mode SYSCALL target rip */ 429 #define MSR_CSTAR 0xc0000083 /* compat mode SYSCALL target rip */ 430 #define MSR_SF_MASK 0xc0000084 /* syscall flags mask */ 431 #define MSR_FSBASE 0xc0000100 /* base address of the %fs "segment" */ 432 #define MSR_GSBASE 0xc0000101 /* base address of the %gs "segment" */ 433 #define MSR_KGSBASE 0xc0000102 /* base address of the kernel %gs */ 434 #define MSR_PERFEVSEL0 0xc0010000 435 #define MSR_PERFEVSEL1 0xc0010001 436 #define MSR_PERFEVSEL2 0xc0010002 437 #define MSR_PERFEVSEL3 0xc0010003 438 #undef MSR_PERFCTR0 439 #undef MSR_PERFCTR1 440 #define MSR_PERFCTR0 0xc0010004 441 #define MSR_PERFCTR1 0xc0010005 442 #define MSR_PERFCTR2 0xc0010006 443 #define MSR_PERFCTR3 0xc0010007 444 #define MSR_SYSCFG 0xc0010010 445 #define MSR_IORRBASE0 0xc0010016 446 #define MSR_IORRMASK0 0xc0010017 447 #define MSR_IORRBASE1 0xc0010018 448 #define MSR_IORRMASK1 0xc0010019 449 #define MSR_TOP_MEM 0xc001001a /* boundary for ram below 4G */ 450 #define MSR_TOP_MEM2 0xc001001d /* boundary for ram above 4G */ 451 #define MSR_K8_UCODE_UPDATE 0xc0010020 /* update microcode */ 452 453 #endif /* !_MACHINE_SPECIALREG_H_ */ 454