1 /*- 2 * Copyright (c) 2011 NetApp, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 */ 28 29 #include <sys/cdefs.h> 30 __FBSDID("$FreeBSD$"); 31 32 #include <sys/param.h> 33 #include <sys/lock.h> 34 #include <sys/kernel.h> 35 #include <sys/malloc.h> 36 #include <sys/mutex.h> 37 #include <sys/systm.h> 38 #include <sys/smp.h> 39 40 #include <x86/specialreg.h> 41 #include <x86/apicreg.h> 42 43 #include <machine/clock.h> 44 #include <machine/smp.h> 45 46 #include <machine/vmm.h> 47 48 #include "vmm_lapic.h" 49 #include "vmm_ktr.h" 50 #include "vmm_stat.h" 51 52 #include "vlapic.h" 53 #include "vlapic_priv.h" 54 #include "vioapic.h" 55 56 #define PRIO(x) ((x) >> 4) 57 58 #define VLAPIC_VERSION (16) 59 60 #define x2apic(vlapic) (((vlapic)->msr_apicbase & APICBASE_X2APIC) ? 1 : 0) 61 62 /* 63 * The 'vlapic->timer_mtx' is used to provide mutual exclusion between the 64 * vlapic_callout_handler() and vcpu accesses to: 65 * - timer_freq_bt, timer_period_bt, timer_fire_bt 66 * - timer LVT register 67 */ 68 #define VLAPIC_TIMER_LOCK(vlapic) mtx_lock_spin(&((vlapic)->timer_mtx)) 69 #define VLAPIC_TIMER_UNLOCK(vlapic) mtx_unlock_spin(&((vlapic)->timer_mtx)) 70 #define VLAPIC_TIMER_LOCKED(vlapic) mtx_owned(&((vlapic)->timer_mtx)) 71 72 /* 73 * APIC timer frequency: 74 * - arbitrary but chosen to be in the ballpark of contemporary hardware. 75 * - power-of-two to avoid loss of precision when converted to a bintime. 76 */ 77 #define VLAPIC_BUS_FREQ (128 * 1024 * 1024) 78 79 static __inline uint32_t 80 vlapic_get_id(struct vlapic *vlapic) 81 { 82 83 if (x2apic(vlapic)) 84 return (vlapic->vcpuid); 85 else 86 return (vlapic->vcpuid << 24); 87 } 88 89 static uint32_t 90 x2apic_ldr(struct vlapic *vlapic) 91 { 92 int apicid; 93 uint32_t ldr; 94 95 apicid = vlapic_get_id(vlapic); 96 ldr = 1 << (apicid & 0xf); 97 ldr |= (apicid & 0xffff0) << 12; 98 return (ldr); 99 } 100 101 void 102 vlapic_dfr_write_handler(struct vlapic *vlapic) 103 { 104 struct LAPIC *lapic; 105 106 lapic = vlapic->apic_page; 107 if (x2apic(vlapic)) { 108 VM_CTR1(vlapic->vm, "ignoring write to DFR in x2apic mode: %#x", 109 lapic->dfr); 110 lapic->dfr = 0; 111 return; 112 } 113 114 lapic->dfr &= APIC_DFR_MODEL_MASK; 115 lapic->dfr |= APIC_DFR_RESERVED; 116 117 if ((lapic->dfr & APIC_DFR_MODEL_MASK) == APIC_DFR_MODEL_FLAT) 118 VLAPIC_CTR0(vlapic, "vlapic DFR in Flat Model"); 119 else if ((lapic->dfr & APIC_DFR_MODEL_MASK) == APIC_DFR_MODEL_CLUSTER) 120 VLAPIC_CTR0(vlapic, "vlapic DFR in Cluster Model"); 121 else 122 VLAPIC_CTR1(vlapic, "DFR in Unknown Model %#x", lapic->dfr); 123 } 124 125 void 126 vlapic_ldr_write_handler(struct vlapic *vlapic) 127 { 128 struct LAPIC *lapic; 129 130 lapic = vlapic->apic_page; 131 132 /* LDR is read-only in x2apic mode */ 133 if (x2apic(vlapic)) { 134 VLAPIC_CTR1(vlapic, "ignoring write to LDR in x2apic mode: %#x", 135 lapic->ldr); 136 lapic->ldr = x2apic_ldr(vlapic); 137 } else { 138 lapic->ldr &= ~APIC_LDR_RESERVED; 139 VLAPIC_CTR1(vlapic, "vlapic LDR set to %#x", lapic->ldr); 140 } 141 } 142 143 void 144 vlapic_id_write_handler(struct vlapic *vlapic) 145 { 146 struct LAPIC *lapic; 147 148 /* 149 * We don't allow the ID register to be modified so reset it back to 150 * its default value. 151 */ 152 lapic = vlapic->apic_page; 153 lapic->id = vlapic_get_id(vlapic); 154 } 155 156 static int 157 vlapic_timer_divisor(uint32_t dcr) 158 { 159 switch (dcr & 0xB) { 160 case APIC_TDCR_1: 161 return (1); 162 case APIC_TDCR_2: 163 return (2); 164 case APIC_TDCR_4: 165 return (4); 166 case APIC_TDCR_8: 167 return (8); 168 case APIC_TDCR_16: 169 return (16); 170 case APIC_TDCR_32: 171 return (32); 172 case APIC_TDCR_64: 173 return (64); 174 case APIC_TDCR_128: 175 return (128); 176 default: 177 panic("vlapic_timer_divisor: invalid dcr 0x%08x", dcr); 178 } 179 } 180 181 #if 0 182 static inline void 183 vlapic_dump_lvt(uint32_t offset, uint32_t *lvt) 184 { 185 printf("Offset %x: lvt %08x (V:%02x DS:%x M:%x)\n", offset, 186 *lvt, *lvt & APIC_LVTT_VECTOR, *lvt & APIC_LVTT_DS, 187 *lvt & APIC_LVTT_M); 188 } 189 #endif 190 191 static uint32_t 192 vlapic_get_ccr(struct vlapic *vlapic) 193 { 194 struct bintime bt_now, bt_rem; 195 struct LAPIC *lapic; 196 uint32_t ccr; 197 198 ccr = 0; 199 lapic = vlapic->apic_page; 200 201 VLAPIC_TIMER_LOCK(vlapic); 202 if (callout_active(&vlapic->callout)) { 203 /* 204 * If the timer is scheduled to expire in the future then 205 * compute the value of 'ccr' based on the remaining time. 206 */ 207 binuptime(&bt_now); 208 if (bintime_cmp(&vlapic->timer_fire_bt, &bt_now, >)) { 209 bt_rem = vlapic->timer_fire_bt; 210 bintime_sub(&bt_rem, &bt_now); 211 ccr += bt_rem.sec * BT2FREQ(&vlapic->timer_freq_bt); 212 ccr += bt_rem.frac / vlapic->timer_freq_bt.frac; 213 } 214 } 215 KASSERT(ccr <= lapic->icr_timer, ("vlapic_get_ccr: invalid ccr %#x, " 216 "icr_timer is %#x", ccr, lapic->icr_timer)); 217 VLAPIC_CTR2(vlapic, "vlapic ccr_timer = %#x, icr_timer = %#x", 218 ccr, lapic->icr_timer); 219 VLAPIC_TIMER_UNLOCK(vlapic); 220 return (ccr); 221 } 222 223 void 224 vlapic_dcr_write_handler(struct vlapic *vlapic) 225 { 226 struct LAPIC *lapic; 227 int divisor; 228 229 lapic = vlapic->apic_page; 230 VLAPIC_TIMER_LOCK(vlapic); 231 232 divisor = vlapic_timer_divisor(lapic->dcr_timer); 233 VLAPIC_CTR2(vlapic, "vlapic dcr_timer=%#x, divisor=%d", 234 lapic->dcr_timer, divisor); 235 236 /* 237 * Update the timer frequency and the timer period. 238 * 239 * XXX changes to the frequency divider will not take effect until 240 * the timer is reloaded. 241 */ 242 FREQ2BT(VLAPIC_BUS_FREQ / divisor, &vlapic->timer_freq_bt); 243 vlapic->timer_period_bt = vlapic->timer_freq_bt; 244 bintime_mul(&vlapic->timer_period_bt, lapic->icr_timer); 245 246 VLAPIC_TIMER_UNLOCK(vlapic); 247 } 248 249 void 250 vlapic_esr_write_handler(struct vlapic *vlapic) 251 { 252 struct LAPIC *lapic; 253 254 lapic = vlapic->apic_page; 255 lapic->esr = vlapic->esr_pending; 256 vlapic->esr_pending = 0; 257 } 258 259 int 260 vlapic_set_intr_ready(struct vlapic *vlapic, int vector, bool level) 261 { 262 struct LAPIC *lapic; 263 uint32_t *irrptr, *tmrptr, mask; 264 int idx; 265 266 KASSERT(vector >= 0 && vector < 256, ("invalid vector %d", vector)); 267 268 lapic = vlapic->apic_page; 269 if (!(lapic->svr & APIC_SVR_ENABLE)) { 270 VLAPIC_CTR1(vlapic, "vlapic is software disabled, ignoring " 271 "interrupt %d", vector); 272 return (0); 273 } 274 275 if (vector < 16) { 276 vlapic_set_error(vlapic, APIC_ESR_RECEIVE_ILLEGAL_VECTOR); 277 VLAPIC_CTR1(vlapic, "vlapic ignoring interrupt to vector %d", 278 vector); 279 return (1); 280 } 281 282 if (vlapic->ops.set_intr_ready) 283 return ((*vlapic->ops.set_intr_ready)(vlapic, vector, level)); 284 285 idx = (vector / 32) * 4; 286 mask = 1 << (vector % 32); 287 288 irrptr = &lapic->irr0; 289 atomic_set_int(&irrptr[idx], mask); 290 291 /* 292 * Verify that the trigger-mode of the interrupt matches with 293 * the vlapic TMR registers. 294 */ 295 tmrptr = &lapic->tmr0; 296 if ((tmrptr[idx] & mask) != (level ? mask : 0)) { 297 VLAPIC_CTR3(vlapic, "vlapic TMR[%d] is 0x%08x but " 298 "interrupt is %s-triggered", idx / 4, tmrptr[idx], 299 level ? "level" : "edge"); 300 } 301 302 VLAPIC_CTR_IRR(vlapic, "vlapic_set_intr_ready"); 303 return (1); 304 } 305 306 static __inline uint32_t * 307 vlapic_get_lvtptr(struct vlapic *vlapic, uint32_t offset) 308 { 309 struct LAPIC *lapic = vlapic->apic_page; 310 int i; 311 312 switch (offset) { 313 case APIC_OFFSET_CMCI_LVT: 314 return (&lapic->lvt_cmci); 315 case APIC_OFFSET_TIMER_LVT ... APIC_OFFSET_ERROR_LVT: 316 i = (offset - APIC_OFFSET_TIMER_LVT) >> 2; 317 return ((&lapic->lvt_timer) + i);; 318 default: 319 panic("vlapic_get_lvt: invalid LVT\n"); 320 } 321 } 322 323 static __inline int 324 lvt_off_to_idx(uint32_t offset) 325 { 326 int index; 327 328 switch (offset) { 329 case APIC_OFFSET_CMCI_LVT: 330 index = APIC_LVT_CMCI; 331 break; 332 case APIC_OFFSET_TIMER_LVT: 333 index = APIC_LVT_TIMER; 334 break; 335 case APIC_OFFSET_THERM_LVT: 336 index = APIC_LVT_THERMAL; 337 break; 338 case APIC_OFFSET_PERF_LVT: 339 index = APIC_LVT_PMC; 340 break; 341 case APIC_OFFSET_LINT0_LVT: 342 index = APIC_LVT_LINT0; 343 break; 344 case APIC_OFFSET_LINT1_LVT: 345 index = APIC_LVT_LINT1; 346 break; 347 case APIC_OFFSET_ERROR_LVT: 348 index = APIC_LVT_ERROR; 349 break; 350 default: 351 index = -1; 352 break; 353 } 354 KASSERT(index >= 0 && index <= VLAPIC_MAXLVT_INDEX, ("lvt_off_to_idx: " 355 "invalid lvt index %d for offset %#x", index, offset)); 356 357 return (index); 358 } 359 360 static __inline uint32_t 361 vlapic_get_lvt(struct vlapic *vlapic, uint32_t offset) 362 { 363 int idx; 364 uint32_t val; 365 366 idx = lvt_off_to_idx(offset); 367 val = atomic_load_acq_32(&vlapic->lvt_last[idx]); 368 return (val); 369 } 370 371 void 372 vlapic_lvt_write_handler(struct vlapic *vlapic, uint32_t offset) 373 { 374 uint32_t *lvtptr, mask, val; 375 struct LAPIC *lapic; 376 int idx; 377 378 lapic = vlapic->apic_page; 379 lvtptr = vlapic_get_lvtptr(vlapic, offset); 380 val = *lvtptr; 381 idx = lvt_off_to_idx(offset); 382 383 if (!(lapic->svr & APIC_SVR_ENABLE)) 384 val |= APIC_LVT_M; 385 mask = APIC_LVT_M | APIC_LVT_DS | APIC_LVT_VECTOR; 386 switch (offset) { 387 case APIC_OFFSET_TIMER_LVT: 388 mask |= APIC_LVTT_TM; 389 break; 390 case APIC_OFFSET_ERROR_LVT: 391 break; 392 case APIC_OFFSET_LINT0_LVT: 393 case APIC_OFFSET_LINT1_LVT: 394 mask |= APIC_LVT_TM | APIC_LVT_RIRR | APIC_LVT_IIPP; 395 /* FALLTHROUGH */ 396 default: 397 mask |= APIC_LVT_DM; 398 break; 399 } 400 val &= mask; 401 *lvtptr = val; 402 atomic_store_rel_32(&vlapic->lvt_last[idx], val); 403 } 404 405 static void 406 vlapic_mask_lvts(struct vlapic *vlapic) 407 { 408 struct LAPIC *lapic = vlapic->apic_page; 409 410 lapic->lvt_cmci |= APIC_LVT_M; 411 vlapic_lvt_write_handler(vlapic, APIC_OFFSET_CMCI_LVT); 412 413 lapic->lvt_timer |= APIC_LVT_M; 414 vlapic_lvt_write_handler(vlapic, APIC_OFFSET_TIMER_LVT); 415 416 lapic->lvt_thermal |= APIC_LVT_M; 417 vlapic_lvt_write_handler(vlapic, APIC_OFFSET_THERM_LVT); 418 419 lapic->lvt_pcint |= APIC_LVT_M; 420 vlapic_lvt_write_handler(vlapic, APIC_OFFSET_PERF_LVT); 421 422 lapic->lvt_lint0 |= APIC_LVT_M; 423 vlapic_lvt_write_handler(vlapic, APIC_OFFSET_LINT0_LVT); 424 425 lapic->lvt_lint1 |= APIC_LVT_M; 426 vlapic_lvt_write_handler(vlapic, APIC_OFFSET_LINT1_LVT); 427 428 lapic->lvt_error |= APIC_LVT_M; 429 vlapic_lvt_write_handler(vlapic, APIC_OFFSET_ERROR_LVT); 430 } 431 432 static int 433 vlapic_fire_lvt(struct vlapic *vlapic, uint32_t lvt) 434 { 435 uint32_t vec, mode; 436 437 if (lvt & APIC_LVT_M) 438 return (0); 439 440 vec = lvt & APIC_LVT_VECTOR; 441 mode = lvt & APIC_LVT_DM; 442 443 switch (mode) { 444 case APIC_LVT_DM_FIXED: 445 if (vec < 16) { 446 vlapic_set_error(vlapic, APIC_ESR_SEND_ILLEGAL_VECTOR); 447 return (0); 448 } 449 if (vlapic_set_intr_ready(vlapic, vec, false)) 450 vcpu_notify_event(vlapic->vm, vlapic->vcpuid, true); 451 break; 452 case APIC_LVT_DM_NMI: 453 vm_inject_nmi(vlapic->vm, vlapic->vcpuid); 454 break; 455 case APIC_LVT_DM_EXTINT: 456 vm_inject_extint(vlapic->vm, vlapic->vcpuid); 457 break; 458 default: 459 // Other modes ignored 460 return (0); 461 } 462 return (1); 463 } 464 465 #if 1 466 static void 467 dump_isrvec_stk(struct vlapic *vlapic) 468 { 469 int i; 470 uint32_t *isrptr; 471 472 isrptr = &vlapic->apic_page->isr0; 473 for (i = 0; i < 8; i++) 474 printf("ISR%d 0x%08x\n", i, isrptr[i * 4]); 475 476 for (i = 0; i <= vlapic->isrvec_stk_top; i++) 477 printf("isrvec_stk[%d] = %d\n", i, vlapic->isrvec_stk[i]); 478 } 479 #endif 480 481 /* 482 * Algorithm adopted from section "Interrupt, Task and Processor Priority" 483 * in Intel Architecture Manual Vol 3a. 484 */ 485 static void 486 vlapic_update_ppr(struct vlapic *vlapic) 487 { 488 int isrvec, tpr, ppr; 489 490 /* 491 * Note that the value on the stack at index 0 is always 0. 492 * 493 * This is a placeholder for the value of ISRV when none of the 494 * bits is set in the ISRx registers. 495 */ 496 isrvec = vlapic->isrvec_stk[vlapic->isrvec_stk_top]; 497 tpr = vlapic->apic_page->tpr; 498 499 #if 1 500 { 501 int i, lastprio, curprio, vector, idx; 502 uint32_t *isrptr; 503 504 if (vlapic->isrvec_stk_top == 0 && isrvec != 0) 505 panic("isrvec_stk is corrupted: %d", isrvec); 506 507 /* 508 * Make sure that the priority of the nested interrupts is 509 * always increasing. 510 */ 511 lastprio = -1; 512 for (i = 1; i <= vlapic->isrvec_stk_top; i++) { 513 curprio = PRIO(vlapic->isrvec_stk[i]); 514 if (curprio <= lastprio) { 515 dump_isrvec_stk(vlapic); 516 panic("isrvec_stk does not satisfy invariant"); 517 } 518 lastprio = curprio; 519 } 520 521 /* 522 * Make sure that each bit set in the ISRx registers has a 523 * corresponding entry on the isrvec stack. 524 */ 525 i = 1; 526 isrptr = &vlapic->apic_page->isr0; 527 for (vector = 0; vector < 256; vector++) { 528 idx = (vector / 32) * 4; 529 if (isrptr[idx] & (1 << (vector % 32))) { 530 if (i > vlapic->isrvec_stk_top || 531 vlapic->isrvec_stk[i] != vector) { 532 dump_isrvec_stk(vlapic); 533 panic("ISR and isrvec_stk out of sync"); 534 } 535 i++; 536 } 537 } 538 } 539 #endif 540 541 if (PRIO(tpr) >= PRIO(isrvec)) 542 ppr = tpr; 543 else 544 ppr = isrvec & 0xf0; 545 546 vlapic->apic_page->ppr = ppr; 547 VLAPIC_CTR1(vlapic, "vlapic_update_ppr 0x%02x", ppr); 548 } 549 550 static void 551 vlapic_process_eoi(struct vlapic *vlapic) 552 { 553 struct LAPIC *lapic = vlapic->apic_page; 554 uint32_t *isrptr, *tmrptr; 555 int i, idx, bitpos, vector; 556 557 isrptr = &lapic->isr0; 558 tmrptr = &lapic->tmr0; 559 560 /* 561 * The x86 architecture reserves the the first 32 vectors for use 562 * by the processor. 563 */ 564 for (i = 7; i > 0; i--) { 565 idx = i * 4; 566 bitpos = fls(isrptr[idx]); 567 if (bitpos-- != 0) { 568 if (vlapic->isrvec_stk_top <= 0) { 569 panic("invalid vlapic isrvec_stk_top %d", 570 vlapic->isrvec_stk_top); 571 } 572 isrptr[idx] &= ~(1 << bitpos); 573 VLAPIC_CTR_ISR(vlapic, "vlapic_process_eoi"); 574 vlapic->isrvec_stk_top--; 575 vlapic_update_ppr(vlapic); 576 if ((tmrptr[idx] & (1 << bitpos)) != 0) { 577 vector = i * 32 + bitpos; 578 vioapic_process_eoi(vlapic->vm, vlapic->vcpuid, 579 vector); 580 } 581 return; 582 } 583 } 584 } 585 586 static __inline int 587 vlapic_get_lvt_field(uint32_t lvt, uint32_t mask) 588 { 589 590 return (lvt & mask); 591 } 592 593 static __inline int 594 vlapic_periodic_timer(struct vlapic *vlapic) 595 { 596 uint32_t lvt; 597 598 lvt = vlapic_get_lvt(vlapic, APIC_OFFSET_TIMER_LVT); 599 600 return (vlapic_get_lvt_field(lvt, APIC_LVTT_TM_PERIODIC)); 601 } 602 603 static VMM_STAT(VLAPIC_INTR_ERROR, "error interrupts generated by vlapic"); 604 605 void 606 vlapic_set_error(struct vlapic *vlapic, uint32_t mask) 607 { 608 uint32_t lvt; 609 610 vlapic->esr_pending |= mask; 611 if (vlapic->esr_firing) 612 return; 613 vlapic->esr_firing = 1; 614 615 // The error LVT always uses the fixed delivery mode. 616 lvt = vlapic_get_lvt(vlapic, APIC_OFFSET_ERROR_LVT); 617 if (vlapic_fire_lvt(vlapic, lvt | APIC_LVT_DM_FIXED)) { 618 vmm_stat_incr(vlapic->vm, vlapic->vcpuid, VLAPIC_INTR_ERROR, 1); 619 } 620 vlapic->esr_firing = 0; 621 } 622 623 static VMM_STAT(VLAPIC_INTR_TIMER, "timer interrupts generated by vlapic"); 624 625 static void 626 vlapic_fire_timer(struct vlapic *vlapic) 627 { 628 uint32_t lvt; 629 630 KASSERT(VLAPIC_TIMER_LOCKED(vlapic), ("vlapic_fire_timer not locked")); 631 632 // The timer LVT always uses the fixed delivery mode. 633 lvt = vlapic_get_lvt(vlapic, APIC_OFFSET_TIMER_LVT); 634 if (vlapic_fire_lvt(vlapic, lvt | APIC_LVT_DM_FIXED)) { 635 VLAPIC_CTR0(vlapic, "vlapic timer fired"); 636 vmm_stat_incr(vlapic->vm, vlapic->vcpuid, VLAPIC_INTR_TIMER, 1); 637 } 638 } 639 640 static VMM_STAT(VLAPIC_INTR_CMC, 641 "corrected machine check interrupts generated by vlapic"); 642 643 void 644 vlapic_fire_cmci(struct vlapic *vlapic) 645 { 646 uint32_t lvt; 647 648 lvt = vlapic_get_lvt(vlapic, APIC_OFFSET_CMCI_LVT); 649 if (vlapic_fire_lvt(vlapic, lvt)) { 650 vmm_stat_incr(vlapic->vm, vlapic->vcpuid, VLAPIC_INTR_CMC, 1); 651 } 652 } 653 654 static VMM_STAT_ARRAY(LVTS_TRIGGERRED, VLAPIC_MAXLVT_INDEX + 1, 655 "lvts triggered"); 656 657 int 658 vlapic_trigger_lvt(struct vlapic *vlapic, int vector) 659 { 660 uint32_t lvt; 661 662 if (vlapic_enabled(vlapic) == false) { 663 /* 664 * When the local APIC is global/hardware disabled, 665 * LINT[1:0] pins are configured as INTR and NMI pins, 666 * respectively. 667 */ 668 switch (vector) { 669 case APIC_LVT_LINT0: 670 vm_inject_extint(vlapic->vm, vlapic->vcpuid); 671 break; 672 case APIC_LVT_LINT1: 673 vm_inject_nmi(vlapic->vm, vlapic->vcpuid); 674 break; 675 default: 676 break; 677 } 678 return (0); 679 } 680 681 switch (vector) { 682 case APIC_LVT_LINT0: 683 lvt = vlapic_get_lvt(vlapic, APIC_OFFSET_LINT0_LVT); 684 break; 685 case APIC_LVT_LINT1: 686 lvt = vlapic_get_lvt(vlapic, APIC_OFFSET_LINT1_LVT); 687 break; 688 case APIC_LVT_TIMER: 689 lvt = vlapic_get_lvt(vlapic, APIC_OFFSET_TIMER_LVT); 690 lvt |= APIC_LVT_DM_FIXED; 691 break; 692 case APIC_LVT_ERROR: 693 lvt = vlapic_get_lvt(vlapic, APIC_OFFSET_ERROR_LVT); 694 lvt |= APIC_LVT_DM_FIXED; 695 break; 696 case APIC_LVT_PMC: 697 lvt = vlapic_get_lvt(vlapic, APIC_OFFSET_PERF_LVT); 698 break; 699 case APIC_LVT_THERMAL: 700 lvt = vlapic_get_lvt(vlapic, APIC_OFFSET_THERM_LVT); 701 break; 702 case APIC_LVT_CMCI: 703 lvt = vlapic_get_lvt(vlapic, APIC_OFFSET_CMCI_LVT); 704 break; 705 default: 706 return (EINVAL); 707 } 708 if (vlapic_fire_lvt(vlapic, lvt)) { 709 vmm_stat_array_incr(vlapic->vm, vlapic->vcpuid, 710 LVTS_TRIGGERRED, vector, 1); 711 } 712 return (0); 713 } 714 715 static void 716 vlapic_callout_handler(void *arg) 717 { 718 struct vlapic *vlapic; 719 struct bintime bt, btnow; 720 sbintime_t rem_sbt; 721 722 vlapic = arg; 723 724 VLAPIC_TIMER_LOCK(vlapic); 725 if (callout_pending(&vlapic->callout)) /* callout was reset */ 726 goto done; 727 728 if (!callout_active(&vlapic->callout)) /* callout was stopped */ 729 goto done; 730 731 callout_deactivate(&vlapic->callout); 732 733 vlapic_fire_timer(vlapic); 734 735 if (vlapic_periodic_timer(vlapic)) { 736 binuptime(&btnow); 737 KASSERT(bintime_cmp(&btnow, &vlapic->timer_fire_bt, >=), 738 ("vlapic callout at %#lx.%#lx, expected at %#lx.#%lx", 739 btnow.sec, btnow.frac, vlapic->timer_fire_bt.sec, 740 vlapic->timer_fire_bt.frac)); 741 742 /* 743 * Compute the delta between when the timer was supposed to 744 * fire and the present time. 745 */ 746 bt = btnow; 747 bintime_sub(&bt, &vlapic->timer_fire_bt); 748 749 rem_sbt = bttosbt(vlapic->timer_period_bt); 750 if (bintime_cmp(&bt, &vlapic->timer_period_bt, <)) { 751 /* 752 * Adjust the time until the next countdown downward 753 * to account for the lost time. 754 */ 755 rem_sbt -= bttosbt(bt); 756 } else { 757 /* 758 * If the delta is greater than the timer period then 759 * just reset our time base instead of trying to catch 760 * up. 761 */ 762 vlapic->timer_fire_bt = btnow; 763 VLAPIC_CTR2(vlapic, "vlapic timer lagging by %lu " 764 "usecs, period is %lu usecs - resetting time base", 765 bttosbt(bt) / SBT_1US, 766 bttosbt(vlapic->timer_period_bt) / SBT_1US); 767 } 768 769 bintime_add(&vlapic->timer_fire_bt, &vlapic->timer_period_bt); 770 callout_reset_sbt(&vlapic->callout, rem_sbt, 0, 771 vlapic_callout_handler, vlapic, 0); 772 } 773 done: 774 VLAPIC_TIMER_UNLOCK(vlapic); 775 } 776 777 void 778 vlapic_icrtmr_write_handler(struct vlapic *vlapic) 779 { 780 struct LAPIC *lapic; 781 sbintime_t sbt; 782 uint32_t icr_timer; 783 784 VLAPIC_TIMER_LOCK(vlapic); 785 786 lapic = vlapic->apic_page; 787 icr_timer = lapic->icr_timer; 788 789 vlapic->timer_period_bt = vlapic->timer_freq_bt; 790 bintime_mul(&vlapic->timer_period_bt, icr_timer); 791 792 if (icr_timer != 0) { 793 binuptime(&vlapic->timer_fire_bt); 794 bintime_add(&vlapic->timer_fire_bt, &vlapic->timer_period_bt); 795 796 sbt = bttosbt(vlapic->timer_period_bt); 797 callout_reset_sbt(&vlapic->callout, sbt, 0, 798 vlapic_callout_handler, vlapic, 0); 799 } else 800 callout_stop(&vlapic->callout); 801 802 VLAPIC_TIMER_UNLOCK(vlapic); 803 } 804 805 /* 806 * This function populates 'dmask' with the set of vcpus that match the 807 * addressing specified by the (dest, phys, lowprio) tuple. 808 * 809 * 'x2apic_dest' specifies whether 'dest' is interpreted as x2APIC (32-bit) 810 * or xAPIC (8-bit) destination field. 811 */ 812 static void 813 vlapic_calcdest(struct vm *vm, cpuset_t *dmask, uint32_t dest, bool phys, 814 bool lowprio, bool x2apic_dest) 815 { 816 struct vlapic *vlapic; 817 uint32_t dfr, ldr, ldest, cluster; 818 uint32_t mda_flat_ldest, mda_cluster_ldest, mda_ldest, mda_cluster_id; 819 cpuset_t amask; 820 int vcpuid; 821 822 if ((x2apic_dest && dest == 0xffffffff) || 823 (!x2apic_dest && dest == 0xff)) { 824 /* 825 * Broadcast in both logical and physical modes. 826 */ 827 *dmask = vm_active_cpus(vm); 828 return; 829 } 830 831 if (phys) { 832 /* 833 * Physical mode: destination is APIC ID. 834 */ 835 CPU_ZERO(dmask); 836 vcpuid = vm_apicid2vcpuid(vm, dest); 837 if (vcpuid < VM_MAXCPU) 838 CPU_SET(vcpuid, dmask); 839 } else { 840 /* 841 * In the "Flat Model" the MDA is interpreted as an 8-bit wide 842 * bitmask. This model is only avilable in the xAPIC mode. 843 */ 844 mda_flat_ldest = dest & 0xff; 845 846 /* 847 * In the "Cluster Model" the MDA is used to identify a 848 * specific cluster and a set of APICs in that cluster. 849 */ 850 if (x2apic_dest) { 851 mda_cluster_id = dest >> 16; 852 mda_cluster_ldest = dest & 0xffff; 853 } else { 854 mda_cluster_id = (dest >> 4) & 0xf; 855 mda_cluster_ldest = dest & 0xf; 856 } 857 858 /* 859 * Logical mode: match each APIC that has a bit set 860 * in it's LDR that matches a bit in the ldest. 861 */ 862 CPU_ZERO(dmask); 863 amask = vm_active_cpus(vm); 864 while ((vcpuid = CPU_FFS(&amask)) != 0) { 865 vcpuid--; 866 CPU_CLR(vcpuid, &amask); 867 868 vlapic = vm_lapic(vm, vcpuid); 869 dfr = vlapic->apic_page->dfr; 870 ldr = vlapic->apic_page->ldr; 871 872 if ((dfr & APIC_DFR_MODEL_MASK) == 873 APIC_DFR_MODEL_FLAT) { 874 ldest = ldr >> 24; 875 mda_ldest = mda_flat_ldest; 876 } else if ((dfr & APIC_DFR_MODEL_MASK) == 877 APIC_DFR_MODEL_CLUSTER) { 878 if (x2apic(vlapic)) { 879 cluster = ldr >> 16; 880 ldest = ldr & 0xffff; 881 } else { 882 cluster = ldr >> 28; 883 ldest = (ldr >> 24) & 0xf; 884 } 885 if (cluster != mda_cluster_id) 886 continue; 887 mda_ldest = mda_cluster_ldest; 888 } else { 889 /* 890 * Guest has configured a bad logical 891 * model for this vcpu - skip it. 892 */ 893 VLAPIC_CTR1(vlapic, "vlapic has bad logical " 894 "model %x - cannot deliver interrupt", dfr); 895 continue; 896 } 897 898 if ((mda_ldest & ldest) != 0) { 899 CPU_SET(vcpuid, dmask); 900 if (lowprio) 901 break; 902 } 903 } 904 } 905 } 906 907 static VMM_STAT_ARRAY(IPIS_SENT, VM_MAXCPU, "ipis sent to vcpu"); 908 909 static void 910 vlapic_set_tpr(struct vlapic *vlapic, uint8_t val) 911 { 912 struct LAPIC *lapic = vlapic->apic_page; 913 914 if (lapic->tpr != val) { 915 VCPU_CTR2(vlapic->vm, vlapic->vcpuid, "vlapic TPR changed " 916 "from %#x to %#x", lapic->tpr, val); 917 lapic->tpr = val; 918 vlapic_update_ppr(vlapic); 919 } 920 } 921 922 static uint8_t 923 vlapic_get_tpr(struct vlapic *vlapic) 924 { 925 struct LAPIC *lapic = vlapic->apic_page; 926 927 return (lapic->tpr); 928 } 929 930 void 931 vlapic_set_cr8(struct vlapic *vlapic, uint64_t val) 932 { 933 uint8_t tpr; 934 935 if (val & ~0xf) { 936 vm_inject_gp(vlapic->vm, vlapic->vcpuid); 937 return; 938 } 939 940 tpr = val << 4; 941 vlapic_set_tpr(vlapic, tpr); 942 } 943 944 uint64_t 945 vlapic_get_cr8(struct vlapic *vlapic) 946 { 947 uint8_t tpr; 948 949 tpr = vlapic_get_tpr(vlapic); 950 return (tpr >> 4); 951 } 952 953 int 954 vlapic_icrlo_write_handler(struct vlapic *vlapic, bool *retu) 955 { 956 int i; 957 bool phys; 958 cpuset_t dmask; 959 uint64_t icrval; 960 uint32_t dest, vec, mode; 961 struct vlapic *vlapic2; 962 struct vm_exit *vmexit; 963 struct LAPIC *lapic; 964 965 lapic = vlapic->apic_page; 966 lapic->icr_lo &= ~APIC_DELSTAT_PEND; 967 icrval = ((uint64_t)lapic->icr_hi << 32) | lapic->icr_lo; 968 969 if (x2apic(vlapic)) 970 dest = icrval >> 32; 971 else 972 dest = icrval >> (32 + 24); 973 vec = icrval & APIC_VECTOR_MASK; 974 mode = icrval & APIC_DELMODE_MASK; 975 976 if (mode == APIC_DELMODE_FIXED && vec < 16) { 977 vlapic_set_error(vlapic, APIC_ESR_SEND_ILLEGAL_VECTOR); 978 VLAPIC_CTR1(vlapic, "Ignoring invalid IPI %d", vec); 979 return (0); 980 } 981 982 VLAPIC_CTR2(vlapic, "icrlo 0x%016lx triggered ipi %d", icrval, vec); 983 984 if (mode == APIC_DELMODE_FIXED || mode == APIC_DELMODE_NMI) { 985 switch (icrval & APIC_DEST_MASK) { 986 case APIC_DEST_DESTFLD: 987 phys = ((icrval & APIC_DESTMODE_LOG) == 0); 988 vlapic_calcdest(vlapic->vm, &dmask, dest, phys, false, 989 x2apic(vlapic)); 990 break; 991 case APIC_DEST_SELF: 992 CPU_SETOF(vlapic->vcpuid, &dmask); 993 break; 994 case APIC_DEST_ALLISELF: 995 dmask = vm_active_cpus(vlapic->vm); 996 break; 997 case APIC_DEST_ALLESELF: 998 dmask = vm_active_cpus(vlapic->vm); 999 CPU_CLR(vlapic->vcpuid, &dmask); 1000 break; 1001 default: 1002 CPU_ZERO(&dmask); /* satisfy gcc */ 1003 break; 1004 } 1005 1006 while ((i = CPU_FFS(&dmask)) != 0) { 1007 i--; 1008 CPU_CLR(i, &dmask); 1009 if (mode == APIC_DELMODE_FIXED) { 1010 lapic_intr_edge(vlapic->vm, i, vec); 1011 vmm_stat_array_incr(vlapic->vm, vlapic->vcpuid, 1012 IPIS_SENT, i, 1); 1013 VLAPIC_CTR2(vlapic, "vlapic sending ipi %d " 1014 "to vcpuid %d", vec, i); 1015 } else { 1016 vm_inject_nmi(vlapic->vm, i); 1017 VLAPIC_CTR1(vlapic, "vlapic sending ipi nmi " 1018 "to vcpuid %d", i); 1019 } 1020 } 1021 1022 return (0); /* handled completely in the kernel */ 1023 } 1024 1025 if (mode == APIC_DELMODE_INIT) { 1026 if ((icrval & APIC_LEVEL_MASK) == APIC_LEVEL_DEASSERT) 1027 return (0); 1028 1029 if (vlapic->vcpuid == 0 && dest != 0 && dest < VM_MAXCPU) { 1030 vlapic2 = vm_lapic(vlapic->vm, dest); 1031 1032 /* move from INIT to waiting-for-SIPI state */ 1033 if (vlapic2->boot_state == BS_INIT) { 1034 vlapic2->boot_state = BS_SIPI; 1035 } 1036 1037 return (0); 1038 } 1039 } 1040 1041 if (mode == APIC_DELMODE_STARTUP) { 1042 if (vlapic->vcpuid == 0 && dest != 0 && dest < VM_MAXCPU) { 1043 vlapic2 = vm_lapic(vlapic->vm, dest); 1044 1045 /* 1046 * Ignore SIPIs in any state other than wait-for-SIPI 1047 */ 1048 if (vlapic2->boot_state != BS_SIPI) 1049 return (0); 1050 1051 vlapic2->boot_state = BS_RUNNING; 1052 1053 *retu = true; 1054 vmexit = vm_exitinfo(vlapic->vm, vlapic->vcpuid); 1055 vmexit->exitcode = VM_EXITCODE_SPINUP_AP; 1056 vmexit->u.spinup_ap.vcpu = dest; 1057 vmexit->u.spinup_ap.rip = vec << PAGE_SHIFT; 1058 1059 return (0); 1060 } 1061 } 1062 1063 /* 1064 * This will cause a return to userland. 1065 */ 1066 return (1); 1067 } 1068 1069 void 1070 vlapic_self_ipi_handler(struct vlapic *vlapic, uint64_t val) 1071 { 1072 int vec; 1073 1074 KASSERT(x2apic(vlapic), ("SELF_IPI does not exist in xAPIC mode")); 1075 1076 vec = val & 0xff; 1077 lapic_intr_edge(vlapic->vm, vlapic->vcpuid, vec); 1078 vmm_stat_array_incr(vlapic->vm, vlapic->vcpuid, IPIS_SENT, 1079 vlapic->vcpuid, 1); 1080 VLAPIC_CTR1(vlapic, "vlapic self-ipi %d", vec); 1081 } 1082 1083 int 1084 vlapic_pending_intr(struct vlapic *vlapic, int *vecptr) 1085 { 1086 struct LAPIC *lapic = vlapic->apic_page; 1087 int idx, i, bitpos, vector; 1088 uint32_t *irrptr, val; 1089 1090 if (vlapic->ops.pending_intr) 1091 return ((*vlapic->ops.pending_intr)(vlapic, vecptr)); 1092 1093 irrptr = &lapic->irr0; 1094 1095 /* 1096 * The x86 architecture reserves the the first 32 vectors for use 1097 * by the processor. 1098 */ 1099 for (i = 7; i > 0; i--) { 1100 idx = i * 4; 1101 val = atomic_load_acq_int(&irrptr[idx]); 1102 bitpos = fls(val); 1103 if (bitpos != 0) { 1104 vector = i * 32 + (bitpos - 1); 1105 if (PRIO(vector) > PRIO(lapic->ppr)) { 1106 VLAPIC_CTR1(vlapic, "pending intr %d", vector); 1107 if (vecptr != NULL) 1108 *vecptr = vector; 1109 return (1); 1110 } else 1111 break; 1112 } 1113 } 1114 return (0); 1115 } 1116 1117 void 1118 vlapic_intr_accepted(struct vlapic *vlapic, int vector) 1119 { 1120 struct LAPIC *lapic = vlapic->apic_page; 1121 uint32_t *irrptr, *isrptr; 1122 int idx, stk_top; 1123 1124 if (vlapic->ops.intr_accepted) 1125 return ((*vlapic->ops.intr_accepted)(vlapic, vector)); 1126 1127 /* 1128 * clear the ready bit for vector being accepted in irr 1129 * and set the vector as in service in isr. 1130 */ 1131 idx = (vector / 32) * 4; 1132 1133 irrptr = &lapic->irr0; 1134 atomic_clear_int(&irrptr[idx], 1 << (vector % 32)); 1135 VLAPIC_CTR_IRR(vlapic, "vlapic_intr_accepted"); 1136 1137 isrptr = &lapic->isr0; 1138 isrptr[idx] |= 1 << (vector % 32); 1139 VLAPIC_CTR_ISR(vlapic, "vlapic_intr_accepted"); 1140 1141 /* 1142 * Update the PPR 1143 */ 1144 vlapic->isrvec_stk_top++; 1145 1146 stk_top = vlapic->isrvec_stk_top; 1147 if (stk_top >= ISRVEC_STK_SIZE) 1148 panic("isrvec_stk_top overflow %d", stk_top); 1149 1150 vlapic->isrvec_stk[stk_top] = vector; 1151 vlapic_update_ppr(vlapic); 1152 } 1153 1154 void 1155 vlapic_svr_write_handler(struct vlapic *vlapic) 1156 { 1157 struct LAPIC *lapic; 1158 uint32_t old, new, changed; 1159 1160 lapic = vlapic->apic_page; 1161 1162 new = lapic->svr; 1163 old = vlapic->svr_last; 1164 vlapic->svr_last = new; 1165 1166 changed = old ^ new; 1167 if ((changed & APIC_SVR_ENABLE) != 0) { 1168 if ((new & APIC_SVR_ENABLE) == 0) { 1169 /* 1170 * The apic is now disabled so stop the apic timer 1171 * and mask all the LVT entries. 1172 */ 1173 VLAPIC_CTR0(vlapic, "vlapic is software-disabled"); 1174 VLAPIC_TIMER_LOCK(vlapic); 1175 callout_stop(&vlapic->callout); 1176 VLAPIC_TIMER_UNLOCK(vlapic); 1177 vlapic_mask_lvts(vlapic); 1178 } else { 1179 /* 1180 * The apic is now enabled so restart the apic timer 1181 * if it is configured in periodic mode. 1182 */ 1183 VLAPIC_CTR0(vlapic, "vlapic is software-enabled"); 1184 if (vlapic_periodic_timer(vlapic)) 1185 vlapic_icrtmr_write_handler(vlapic); 1186 } 1187 } 1188 } 1189 1190 int 1191 vlapic_read(struct vlapic *vlapic, int mmio_access, uint64_t offset, 1192 uint64_t *data, bool *retu) 1193 { 1194 struct LAPIC *lapic = vlapic->apic_page; 1195 uint32_t *reg; 1196 int i; 1197 1198 /* Ignore MMIO accesses in x2APIC mode */ 1199 if (x2apic(vlapic) && mmio_access) { 1200 VLAPIC_CTR1(vlapic, "MMIO read from offset %#lx in x2APIC mode", 1201 offset); 1202 *data = 0; 1203 goto done; 1204 } 1205 1206 if (!x2apic(vlapic) && !mmio_access) { 1207 /* 1208 * XXX Generate GP fault for MSR accesses in xAPIC mode 1209 */ 1210 VLAPIC_CTR1(vlapic, "x2APIC MSR read from offset %#lx in " 1211 "xAPIC mode", offset); 1212 *data = 0; 1213 goto done; 1214 } 1215 1216 if (offset > sizeof(*lapic)) { 1217 *data = 0; 1218 goto done; 1219 } 1220 1221 offset &= ~3; 1222 switch(offset) 1223 { 1224 case APIC_OFFSET_ID: 1225 *data = lapic->id; 1226 break; 1227 case APIC_OFFSET_VER: 1228 *data = lapic->version; 1229 break; 1230 case APIC_OFFSET_TPR: 1231 *data = vlapic_get_tpr(vlapic); 1232 break; 1233 case APIC_OFFSET_APR: 1234 *data = lapic->apr; 1235 break; 1236 case APIC_OFFSET_PPR: 1237 *data = lapic->ppr; 1238 break; 1239 case APIC_OFFSET_EOI: 1240 *data = lapic->eoi; 1241 break; 1242 case APIC_OFFSET_LDR: 1243 *data = lapic->ldr; 1244 break; 1245 case APIC_OFFSET_DFR: 1246 *data = lapic->dfr; 1247 break; 1248 case APIC_OFFSET_SVR: 1249 *data = lapic->svr; 1250 break; 1251 case APIC_OFFSET_ISR0 ... APIC_OFFSET_ISR7: 1252 i = (offset - APIC_OFFSET_ISR0) >> 2; 1253 reg = &lapic->isr0; 1254 *data = *(reg + i); 1255 break; 1256 case APIC_OFFSET_TMR0 ... APIC_OFFSET_TMR7: 1257 i = (offset - APIC_OFFSET_TMR0) >> 2; 1258 reg = &lapic->tmr0; 1259 *data = *(reg + i); 1260 break; 1261 case APIC_OFFSET_IRR0 ... APIC_OFFSET_IRR7: 1262 i = (offset - APIC_OFFSET_IRR0) >> 2; 1263 reg = &lapic->irr0; 1264 *data = atomic_load_acq_int(reg + i); 1265 break; 1266 case APIC_OFFSET_ESR: 1267 *data = lapic->esr; 1268 break; 1269 case APIC_OFFSET_ICR_LOW: 1270 *data = lapic->icr_lo; 1271 if (x2apic(vlapic)) 1272 *data |= (uint64_t)lapic->icr_hi << 32; 1273 break; 1274 case APIC_OFFSET_ICR_HI: 1275 *data = lapic->icr_hi; 1276 break; 1277 case APIC_OFFSET_CMCI_LVT: 1278 case APIC_OFFSET_TIMER_LVT ... APIC_OFFSET_ERROR_LVT: 1279 *data = vlapic_get_lvt(vlapic, offset); 1280 #ifdef INVARIANTS 1281 reg = vlapic_get_lvtptr(vlapic, offset); 1282 KASSERT(*data == *reg, ("inconsistent lvt value at " 1283 "offset %#lx: %#lx/%#x", offset, *data, *reg)); 1284 #endif 1285 break; 1286 case APIC_OFFSET_TIMER_ICR: 1287 *data = lapic->icr_timer; 1288 break; 1289 case APIC_OFFSET_TIMER_CCR: 1290 *data = vlapic_get_ccr(vlapic); 1291 break; 1292 case APIC_OFFSET_TIMER_DCR: 1293 *data = lapic->dcr_timer; 1294 break; 1295 case APIC_OFFSET_SELF_IPI: 1296 /* 1297 * XXX generate a GP fault if vlapic is in x2apic mode 1298 */ 1299 *data = 0; 1300 break; 1301 case APIC_OFFSET_RRR: 1302 default: 1303 *data = 0; 1304 break; 1305 } 1306 done: 1307 VLAPIC_CTR2(vlapic, "vlapic read offset %#x, data %#lx", offset, *data); 1308 return 0; 1309 } 1310 1311 int 1312 vlapic_write(struct vlapic *vlapic, int mmio_access, uint64_t offset, 1313 uint64_t data, bool *retu) 1314 { 1315 struct LAPIC *lapic = vlapic->apic_page; 1316 uint32_t *regptr; 1317 int retval; 1318 1319 KASSERT((offset & 0xf) == 0 && offset < PAGE_SIZE, 1320 ("vlapic_write: invalid offset %#lx", offset)); 1321 1322 VLAPIC_CTR2(vlapic, "vlapic write offset %#lx, data %#lx", 1323 offset, data); 1324 1325 if (offset > sizeof(*lapic)) 1326 return (0); 1327 1328 /* Ignore MMIO accesses in x2APIC mode */ 1329 if (x2apic(vlapic) && mmio_access) { 1330 VLAPIC_CTR2(vlapic, "MMIO write of %#lx to offset %#lx " 1331 "in x2APIC mode", data, offset); 1332 return (0); 1333 } 1334 1335 /* 1336 * XXX Generate GP fault for MSR accesses in xAPIC mode 1337 */ 1338 if (!x2apic(vlapic) && !mmio_access) { 1339 VLAPIC_CTR2(vlapic, "x2APIC MSR write of %#lx to offset %#lx " 1340 "in xAPIC mode", data, offset); 1341 return (0); 1342 } 1343 1344 retval = 0; 1345 switch(offset) 1346 { 1347 case APIC_OFFSET_ID: 1348 lapic->id = data; 1349 vlapic_id_write_handler(vlapic); 1350 break; 1351 case APIC_OFFSET_TPR: 1352 vlapic_set_tpr(vlapic, data & 0xff); 1353 break; 1354 case APIC_OFFSET_EOI: 1355 vlapic_process_eoi(vlapic); 1356 break; 1357 case APIC_OFFSET_LDR: 1358 lapic->ldr = data; 1359 vlapic_ldr_write_handler(vlapic); 1360 break; 1361 case APIC_OFFSET_DFR: 1362 lapic->dfr = data; 1363 vlapic_dfr_write_handler(vlapic); 1364 break; 1365 case APIC_OFFSET_SVR: 1366 lapic->svr = data; 1367 vlapic_svr_write_handler(vlapic); 1368 break; 1369 case APIC_OFFSET_ICR_LOW: 1370 lapic->icr_lo = data; 1371 if (x2apic(vlapic)) 1372 lapic->icr_hi = data >> 32; 1373 retval = vlapic_icrlo_write_handler(vlapic, retu); 1374 break; 1375 case APIC_OFFSET_ICR_HI: 1376 lapic->icr_hi = data; 1377 break; 1378 case APIC_OFFSET_CMCI_LVT: 1379 case APIC_OFFSET_TIMER_LVT ... APIC_OFFSET_ERROR_LVT: 1380 regptr = vlapic_get_lvtptr(vlapic, offset); 1381 *regptr = data; 1382 vlapic_lvt_write_handler(vlapic, offset); 1383 break; 1384 case APIC_OFFSET_TIMER_ICR: 1385 lapic->icr_timer = data; 1386 vlapic_icrtmr_write_handler(vlapic); 1387 break; 1388 1389 case APIC_OFFSET_TIMER_DCR: 1390 lapic->dcr_timer = data; 1391 vlapic_dcr_write_handler(vlapic); 1392 break; 1393 1394 case APIC_OFFSET_ESR: 1395 vlapic_esr_write_handler(vlapic); 1396 break; 1397 1398 case APIC_OFFSET_SELF_IPI: 1399 if (x2apic(vlapic)) 1400 vlapic_self_ipi_handler(vlapic, data); 1401 break; 1402 1403 case APIC_OFFSET_VER: 1404 case APIC_OFFSET_APR: 1405 case APIC_OFFSET_PPR: 1406 case APIC_OFFSET_RRR: 1407 case APIC_OFFSET_ISR0 ... APIC_OFFSET_ISR7: 1408 case APIC_OFFSET_TMR0 ... APIC_OFFSET_TMR7: 1409 case APIC_OFFSET_IRR0 ... APIC_OFFSET_IRR7: 1410 case APIC_OFFSET_TIMER_CCR: 1411 default: 1412 // Read only. 1413 break; 1414 } 1415 1416 return (retval); 1417 } 1418 1419 static void 1420 vlapic_reset(struct vlapic *vlapic) 1421 { 1422 struct LAPIC *lapic; 1423 1424 lapic = vlapic->apic_page; 1425 bzero(lapic, sizeof(struct LAPIC)); 1426 1427 lapic->id = vlapic_get_id(vlapic); 1428 lapic->version = VLAPIC_VERSION; 1429 lapic->version |= (VLAPIC_MAXLVT_INDEX << MAXLVTSHIFT); 1430 lapic->dfr = 0xffffffff; 1431 lapic->svr = APIC_SVR_VECTOR; 1432 vlapic_mask_lvts(vlapic); 1433 vlapic_reset_tmr(vlapic); 1434 1435 lapic->dcr_timer = 0; 1436 vlapic_dcr_write_handler(vlapic); 1437 1438 if (vlapic->vcpuid == 0) 1439 vlapic->boot_state = BS_RUNNING; /* BSP */ 1440 else 1441 vlapic->boot_state = BS_INIT; /* AP */ 1442 1443 vlapic->svr_last = lapic->svr; 1444 } 1445 1446 void 1447 vlapic_init(struct vlapic *vlapic) 1448 { 1449 KASSERT(vlapic->vm != NULL, ("vlapic_init: vm is not initialized")); 1450 KASSERT(vlapic->vcpuid >= 0 && vlapic->vcpuid < VM_MAXCPU, 1451 ("vlapic_init: vcpuid is not initialized")); 1452 KASSERT(vlapic->apic_page != NULL, ("vlapic_init: apic_page is not " 1453 "initialized")); 1454 1455 /* 1456 * If the vlapic is configured in x2apic mode then it will be 1457 * accessed in the critical section via the MSR emulation code. 1458 * 1459 * Therefore the timer mutex must be a spinlock because blockable 1460 * mutexes cannot be acquired in a critical section. 1461 */ 1462 mtx_init(&vlapic->timer_mtx, "vlapic timer mtx", NULL, MTX_SPIN); 1463 callout_init(&vlapic->callout, 1); 1464 1465 vlapic->msr_apicbase = DEFAULT_APIC_BASE | APICBASE_ENABLED; 1466 1467 if (vlapic->vcpuid == 0) 1468 vlapic->msr_apicbase |= APICBASE_BSP; 1469 1470 vlapic_reset(vlapic); 1471 } 1472 1473 void 1474 vlapic_cleanup(struct vlapic *vlapic) 1475 { 1476 1477 callout_drain(&vlapic->callout); 1478 } 1479 1480 uint64_t 1481 vlapic_get_apicbase(struct vlapic *vlapic) 1482 { 1483 1484 return (vlapic->msr_apicbase); 1485 } 1486 1487 int 1488 vlapic_set_apicbase(struct vlapic *vlapic, uint64_t new) 1489 { 1490 1491 if (vlapic->msr_apicbase != new) { 1492 VLAPIC_CTR2(vlapic, "Changing APIC_BASE MSR from %#lx to %#lx " 1493 "not supported", vlapic->msr_apicbase, new); 1494 return (-1); 1495 } 1496 1497 return (0); 1498 } 1499 1500 void 1501 vlapic_set_x2apic_state(struct vm *vm, int vcpuid, enum x2apic_state state) 1502 { 1503 struct vlapic *vlapic; 1504 struct LAPIC *lapic; 1505 1506 vlapic = vm_lapic(vm, vcpuid); 1507 1508 if (state == X2APIC_DISABLED) 1509 vlapic->msr_apicbase &= ~APICBASE_X2APIC; 1510 else 1511 vlapic->msr_apicbase |= APICBASE_X2APIC; 1512 1513 /* 1514 * Reset the local APIC registers whose values are mode-dependent. 1515 * 1516 * XXX this works because the APIC mode can be changed only at vcpu 1517 * initialization time. 1518 */ 1519 lapic = vlapic->apic_page; 1520 lapic->id = vlapic_get_id(vlapic); 1521 if (x2apic(vlapic)) { 1522 lapic->ldr = x2apic_ldr(vlapic); 1523 lapic->dfr = 0; 1524 } else { 1525 lapic->ldr = 0; 1526 lapic->dfr = 0xffffffff; 1527 } 1528 1529 if (state == X2APIC_ENABLED) { 1530 if (vlapic->ops.enable_x2apic_mode) 1531 (*vlapic->ops.enable_x2apic_mode)(vlapic); 1532 } 1533 } 1534 1535 void 1536 vlapic_deliver_intr(struct vm *vm, bool level, uint32_t dest, bool phys, 1537 int delmode, int vec) 1538 { 1539 bool lowprio; 1540 int vcpuid; 1541 cpuset_t dmask; 1542 1543 if (delmode != IOART_DELFIXED && 1544 delmode != IOART_DELLOPRI && 1545 delmode != IOART_DELEXINT) { 1546 VM_CTR1(vm, "vlapic intr invalid delmode %#x", delmode); 1547 return; 1548 } 1549 lowprio = (delmode == IOART_DELLOPRI); 1550 1551 /* 1552 * We don't provide any virtual interrupt redirection hardware so 1553 * all interrupts originating from the ioapic or MSI specify the 1554 * 'dest' in the legacy xAPIC format. 1555 */ 1556 vlapic_calcdest(vm, &dmask, dest, phys, lowprio, false); 1557 1558 while ((vcpuid = CPU_FFS(&dmask)) != 0) { 1559 vcpuid--; 1560 CPU_CLR(vcpuid, &dmask); 1561 if (delmode == IOART_DELEXINT) { 1562 vm_inject_extint(vm, vcpuid); 1563 } else { 1564 lapic_set_intr(vm, vcpuid, vec, level); 1565 } 1566 } 1567 } 1568 1569 void 1570 vlapic_post_intr(struct vlapic *vlapic, int hostcpu, int ipinum) 1571 { 1572 /* 1573 * Post an interrupt to the vcpu currently running on 'hostcpu'. 1574 * 1575 * This is done by leveraging features like Posted Interrupts (Intel) 1576 * Doorbell MSR (AMD AVIC) that avoid a VM exit. 1577 * 1578 * If neither of these features are available then fallback to 1579 * sending an IPI to 'hostcpu'. 1580 */ 1581 if (vlapic->ops.post_intr) 1582 (*vlapic->ops.post_intr)(vlapic, hostcpu); 1583 else 1584 ipi_cpu(hostcpu, ipinum); 1585 } 1586 1587 bool 1588 vlapic_enabled(struct vlapic *vlapic) 1589 { 1590 struct LAPIC *lapic = vlapic->apic_page; 1591 1592 if ((vlapic->msr_apicbase & APICBASE_ENABLED) != 0 && 1593 (lapic->svr & APIC_SVR_ENABLE) != 0) 1594 return (true); 1595 else 1596 return (false); 1597 } 1598 1599 static void 1600 vlapic_set_tmr(struct vlapic *vlapic, int vector, bool level) 1601 { 1602 struct LAPIC *lapic; 1603 uint32_t *tmrptr, mask; 1604 int idx; 1605 1606 lapic = vlapic->apic_page; 1607 tmrptr = &lapic->tmr0; 1608 idx = (vector / 32) * 4; 1609 mask = 1 << (vector % 32); 1610 if (level) 1611 tmrptr[idx] |= mask; 1612 else 1613 tmrptr[idx] &= ~mask; 1614 1615 if (vlapic->ops.set_tmr != NULL) 1616 (*vlapic->ops.set_tmr)(vlapic, vector, level); 1617 } 1618 1619 void 1620 vlapic_reset_tmr(struct vlapic *vlapic) 1621 { 1622 int vector; 1623 1624 VLAPIC_CTR0(vlapic, "vlapic resetting all vectors to edge-triggered"); 1625 1626 for (vector = 0; vector <= 255; vector++) 1627 vlapic_set_tmr(vlapic, vector, false); 1628 } 1629 1630 void 1631 vlapic_set_tmr_level(struct vlapic *vlapic, uint32_t dest, bool phys, 1632 int delmode, int vector) 1633 { 1634 cpuset_t dmask; 1635 bool lowprio; 1636 1637 KASSERT(vector >= 0 && vector <= 255, ("invalid vector %d", vector)); 1638 1639 /* 1640 * A level trigger is valid only for fixed and lowprio delivery modes. 1641 */ 1642 if (delmode != APIC_DELMODE_FIXED && delmode != APIC_DELMODE_LOWPRIO) { 1643 VLAPIC_CTR1(vlapic, "Ignoring level trigger-mode for " 1644 "delivery-mode %d", delmode); 1645 return; 1646 } 1647 1648 lowprio = (delmode == APIC_DELMODE_LOWPRIO); 1649 vlapic_calcdest(vlapic->vm, &dmask, dest, phys, lowprio, false); 1650 1651 if (!CPU_ISSET(vlapic->vcpuid, &dmask)) 1652 return; 1653 1654 VLAPIC_CTR1(vlapic, "vector %d set to level-triggered", vector); 1655 vlapic_set_tmr(vlapic, vector, true); 1656 } 1657