1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2020 Oleksandr Tymoshenko <gonzo@FreeBSD.org> 5 * Copyright (c) 2018 Jared McNeill <jmcneill@invisible.ca> 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 #include <sys/param.h> 31 #include <sys/systm.h> 32 #include <sys/bus.h> 33 #include <sys/kernel.h> 34 #include <sys/lock.h> 35 #include <sys/module.h> 36 #include <sys/mutex.h> 37 #include <sys/rman.h> 38 #include <sys/resource.h> 39 #include <machine/bus.h> 40 41 #include <dev/ofw/ofw_bus.h> 42 #include <dev/ofw/ofw_bus_subr.h> 43 44 #include <dev/extres/clk/clk.h> 45 #include <dev/extres/hwreset/hwreset.h> 46 47 #include "syscon_if.h" 48 49 #include "opt_snd.h" 50 #include <dev/sound/pcm/sound.h> 51 #include <dev/sound/fdt/audio_dai.h> 52 #include "audio_dai_if.h" 53 54 #define FIFO_LEVEL 0x40 55 56 #define DA_CTL 0x00 57 #define DA_CTL_BCLK_OUT (1 << 18) /* sun8i */ 58 #define DA_CLK_LRCK_OUT (1 << 17) /* sun8i */ 59 #define DA_CTL_SDO_EN (1 << 8) 60 #define DA_CTL_MS (1 << 5) /* sun4i */ 61 #define DA_CTL_PCM (1 << 4) /* sun4i */ 62 #define DA_CTL_MODE_SEL_MASK (3 << 4) /* sun8i */ 63 #define DA_CTL_MODE_SEL_PCM (0 << 4) /* sun8i */ 64 #define DA_CTL_MODE_SEL_LJ (1 << 4) /* sun8i */ 65 #define DA_CTL_MODE_SEL_RJ (2 << 4) /* sun8i */ 66 #define DA_CTL_TXEN (1 << 2) 67 #define DA_CTL_RXEN (1 << 1) 68 #define DA_CTL_GEN (1 << 0) 69 #define DA_FAT0 0x04 70 #define DA_FAT0_LRCK_PERIOD_MASK (0x3ff << 8) /* sun8i */ 71 #define DA_FAT0_LRCK_PERIOD(n) (((n) & 0x3fff) << 8) /* sun8i */ 72 #define DA_FAT0_LRCP_MASK (1 << 7) 73 #define DA_LRCP_NORMAL (0 << 7) 74 #define DA_LRCP_INVERTED (1 << 7) 75 #define DA_FAT0_BCP_MASK (1 << 6) 76 #define DA_BCP_NORMAL (0 << 6) 77 #define DA_BCP_INVERTED (1 << 6) 78 #define DA_FAT0_SR __BITS(5,4) 79 #define DA_FAT0_WSS __BITS(3,2) 80 #define DA_FAT0_FMT_MASK (3 << 0) 81 #define DA_FMT_I2S 0 82 #define DA_FMT_LJ 1 83 #define DA_FMT_RJ 2 84 #define DA_FAT1 0x08 85 #define DA_ISTA 0x0c 86 #define DA_ISTA_TXUI_INT (1 << 6) 87 #define DA_ISTA_TXEI_INT (1 << 4) 88 #define DA_ISTA_RXAI_INT (1 << 0) 89 #define DA_RXFIFO 0x10 90 #define DA_FCTL 0x14 91 #define DA_FCTL_HUB_EN (1 << 31) 92 #define DA_FCTL_FTX (1 << 25) 93 #define DA_FCTL_FRX (1 << 24) 94 #define DA_FCTL_TXTL_MASK (0x7f << 12) 95 #define DA_FCTL_TXTL(v) (((v) & 0x7f) << 12) 96 #define DA_FCTL_TXIM (1 << 2) 97 #define DA_FSTA 0x18 98 #define DA_FSTA_TXE_CNT(v) (((v) >> 16) & 0xff) 99 #define DA_FSTA_RXA_CNT(v) ((v) & 0x3f) 100 #define DA_INT 0x1c 101 #define DA_INT_TX_DRQ (1 << 7) 102 #define DA_INT_TXUI_EN (1 << 6) 103 #define DA_INT_TXEI_EN (1 << 4) 104 #define DA_INT_RX_DRQ (1 << 3) 105 #define DA_INT_RXAI_EN (1 << 0) 106 #define DA_TXFIFO 0x20 107 #define DA_CLKD 0x24 108 #define DA_CLKD_MCLKO_EN_SUN8I (1 << 8) 109 #define DA_CLKD_MCLKO_EN_SUN4I (1 << 7) 110 #define DA_CLKD_BCLKDIV_SUN8I(n) (((n) & 0xf) << 4) 111 #define DA_CLKD_BCLKDIV_SUN8I_MASK (0xf << 4) 112 #define DA_CLKD_BCLKDIV_SUN4I(n) (((n) & 7) << 4) 113 #define DA_CLKD_BCLKDIV_SUN4I_MASK (7 << 4) 114 #define DA_CLKD_BCLKDIV_8 3 115 #define DA_CLKD_BCLKDIV_16 5 116 #define DA_CLKD_MCLKDIV(n) (((n) & 0xff) << 0) 117 #define DA_CLKD_MCLKDIV_MASK (0xf << 0) 118 #define DA_CLKD_MCLKDIV_1 0 119 #define DA_TXCNT 0x28 120 #define DA_RXCNT 0x2c 121 #define DA_CHCFG 0x30 /* sun8i */ 122 #define DA_CHCFG_TX_SLOT_HIZ (1 << 9) 123 #define DA_CHCFG_TXN_STATE (1 << 8) 124 #define DA_CHCFG_RX_SLOT_NUM_MASK (7 << 4) 125 #define DA_CHCFG_RX_SLOT_NUM(n) (((n) & 7) << 4) 126 #define DA_CHCFG_TX_SLOT_NUM_MASK (7 << 0) 127 #define DA_CHCFG_TX_SLOT_NUM(n) (((n) & 7) << 0) 128 129 #define DA_CHSEL_OFFSET(n) (((n) & 3) << 12) /* sun8i */ 130 #define DA_CHSEL_OFFSET_MASK (3 << 12) /* sun8i */ 131 #define DA_CHSEL_EN(n) (((n) & 0xff) << 4) 132 #define DA_CHSEL_EN_MASK (0xff << 4) 133 #define DA_CHSEL_SEL(n) (((n) & 7) << 0) 134 #define DA_CHSEL_SEL_MASK (7 << 0) 135 136 #define AUDIO_BUFFER_SIZE 48000 * 4 137 138 #define AW_I2S_SAMPLE_RATE 48000 139 #define AW_I2S_CLK_RATE 24576000 140 141 enum sunxi_i2s_type { 142 SUNXI_I2S_SUN4I, 143 SUNXI_I2S_SUN8I, 144 }; 145 146 struct sunxi_i2s_config { 147 const char *name; 148 enum sunxi_i2s_type type; 149 bus_size_t txchsel; 150 bus_size_t txchmap; 151 bus_size_t rxchsel; 152 bus_size_t rxchmap; 153 }; 154 155 static const struct sunxi_i2s_config sun50i_a64_codec_config = { 156 .name = "Audio Codec (digital part)", 157 .type = SUNXI_I2S_SUN4I, 158 .txchsel = 0x30, 159 .txchmap = 0x34, 160 .rxchsel = 0x38, 161 .rxchmap = 0x3c, 162 }; 163 164 static const struct sunxi_i2s_config sun8i_h3_config = { 165 .name = "I2S/PCM controller", 166 .type = SUNXI_I2S_SUN8I, 167 .txchsel = 0x34, 168 .txchmap = 0x44, 169 .rxchsel = 0x54, 170 .rxchmap = 0x58, 171 }; 172 173 static const u_int sun4i_i2s_bclk_divmap[] = { 174 [0] = 2, 175 [1] = 4, 176 [2] = 6, 177 [3] = 8, 178 [4] = 12, 179 [5] = 16, 180 }; 181 182 static const u_int sun4i_i2s_mclk_divmap[] = { 183 [0] = 1, 184 [1] = 2, 185 [2] = 4, 186 [3] = 6, 187 [4] = 8, 188 [5] = 12, 189 [6] = 16, 190 [7] = 24, 191 }; 192 193 static const u_int sun8i_i2s_divmap[] = { 194 [1] = 1, 195 [2] = 2, 196 [3] = 4, 197 [4] = 6, 198 [5] = 8, 199 [6] = 12, 200 [7] = 16, 201 [8] = 24, 202 [9] = 32, 203 [10] = 48, 204 [11] = 64, 205 [12] = 96, 206 [13] = 128, 207 [14] = 176, 208 [15] = 192, 209 }; 210 211 212 static struct ofw_compat_data compat_data[] = { 213 { "allwinner,sun50i-a64-codec-i2s", (uintptr_t)&sun50i_a64_codec_config }, 214 { "allwinner,sun8i-h3-i2s", (uintptr_t)&sun8i_h3_config }, 215 { NULL, 0 } 216 }; 217 218 static struct resource_spec aw_i2s_spec[] = { 219 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 220 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 221 { -1, 0 } 222 }; 223 224 struct aw_i2s_softc { 225 device_t dev; 226 struct resource *res[2]; 227 struct mtx mtx; 228 clk_t clk; 229 struct sunxi_i2s_config *cfg; 230 void * intrhand; 231 /* pointers to playback/capture buffers */ 232 uint32_t play_ptr; 233 uint32_t rec_ptr; 234 }; 235 236 #define I2S_LOCK(sc) mtx_lock(&(sc)->mtx) 237 #define I2S_UNLOCK(sc) mtx_unlock(&(sc)->mtx) 238 #define I2S_READ(sc, reg) bus_read_4((sc)->res[0], (reg)) 239 #define I2S_WRITE(sc, reg, val) bus_write_4((sc)->res[0], (reg), (val)) 240 #define I2S_TYPE(sc) ((sc)->cfg->type) 241 242 static int aw_i2s_probe(device_t dev); 243 static int aw_i2s_attach(device_t dev); 244 static int aw_i2s_detach(device_t dev); 245 246 static u_int 247 sunxi_i2s_div_to_regval(const u_int *divmap, u_int divmaplen, u_int div) 248 { 249 u_int n; 250 251 for (n = 0; n < divmaplen; n++) 252 if (divmap[n] == div) 253 return n; 254 255 return -1; 256 } 257 258 static uint32_t sc_fmt[] = { 259 SND_FORMAT(AFMT_S16_LE, 2, 0), 260 0 261 }; 262 static struct pcmchan_caps aw_i2s_caps = {AW_I2S_SAMPLE_RATE, AW_I2S_SAMPLE_RATE, sc_fmt, 0}; 263 264 265 static int 266 aw_i2s_init(struct aw_i2s_softc *sc) 267 { 268 uint32_t val; 269 int error; 270 271 error = clk_enable(sc->clk); 272 if (error != 0) { 273 device_printf(sc->dev, "cannot enable mod clock\n"); 274 return (ENXIO); 275 } 276 277 /* Reset */ 278 val = I2S_READ(sc, DA_CTL); 279 val &= ~(DA_CTL_TXEN|DA_CTL_RXEN|DA_CTL_GEN); 280 I2S_WRITE(sc, DA_CTL, val); 281 282 val = I2S_READ(sc, DA_FCTL); 283 val &= ~(DA_FCTL_FTX|DA_FCTL_FRX); 284 val &= ~(DA_FCTL_TXTL_MASK); 285 val |= DA_FCTL_TXTL(FIFO_LEVEL); 286 I2S_WRITE(sc, DA_FCTL, val); 287 288 I2S_WRITE(sc, DA_TXCNT, 0); 289 I2S_WRITE(sc, DA_RXCNT, 0); 290 291 /* Enable */ 292 val = I2S_READ(sc, DA_CTL); 293 val |= DA_CTL_GEN; 294 I2S_WRITE(sc, DA_CTL, val); 295 val |= DA_CTL_SDO_EN; 296 I2S_WRITE(sc, DA_CTL, val); 297 298 /* Setup channels */ 299 I2S_WRITE(sc, sc->cfg->txchmap, 0x76543210); 300 val = I2S_READ(sc, sc->cfg->txchsel); 301 val &= ~DA_CHSEL_EN_MASK; 302 val |= DA_CHSEL_EN(3); 303 val &= ~DA_CHSEL_SEL_MASK; 304 val |= DA_CHSEL_SEL(1); 305 I2S_WRITE(sc, sc->cfg->txchsel, val); 306 I2S_WRITE(sc, sc->cfg->rxchmap, 0x76543210); 307 val = I2S_READ(sc, sc->cfg->rxchsel); 308 val &= ~DA_CHSEL_EN_MASK; 309 val |= DA_CHSEL_EN(3); 310 val &= ~DA_CHSEL_SEL_MASK; 311 val |= DA_CHSEL_SEL(1); 312 I2S_WRITE(sc, sc->cfg->rxchsel, val); 313 314 if (I2S_TYPE(sc) == SUNXI_I2S_SUN8I) { 315 val = I2S_READ(sc, DA_CHCFG); 316 val &= ~DA_CHCFG_TX_SLOT_NUM_MASK; 317 val |= DA_CHCFG_TX_SLOT_NUM(1); 318 val &= ~DA_CHCFG_RX_SLOT_NUM_MASK; 319 val |= DA_CHCFG_RX_SLOT_NUM(1); 320 I2S_WRITE(sc, DA_CHCFG, val); 321 } 322 323 return (0); 324 } 325 326 static int 327 aw_i2s_probe(device_t dev) 328 { 329 if (!ofw_bus_status_okay(dev)) 330 return (ENXIO); 331 332 if (!ofw_bus_search_compatible(dev, compat_data)->ocd_data) 333 return (ENXIO); 334 335 device_set_desc(dev, "Allwinner I2S"); 336 return (BUS_PROBE_DEFAULT); 337 } 338 339 static int 340 aw_i2s_attach(device_t dev) 341 { 342 struct aw_i2s_softc *sc; 343 int error; 344 phandle_t node; 345 hwreset_t rst; 346 clk_t clk; 347 348 sc = device_get_softc(dev); 349 sc->dev = dev; 350 351 sc->cfg = (void*)ofw_bus_search_compatible(dev, compat_data)->ocd_data; 352 353 mtx_init(&sc->mtx, device_get_nameunit(dev), NULL, MTX_DEF); 354 355 if (bus_alloc_resources(dev, aw_i2s_spec, sc->res) != 0) { 356 device_printf(dev, "cannot allocate resources for device\n"); 357 error = ENXIO; 358 goto fail; 359 } 360 361 error = clk_get_by_ofw_name(dev, 0, "mod", &sc->clk); 362 if (error != 0) { 363 device_printf(dev, "cannot get i2s_clk clock\n"); 364 goto fail; 365 } 366 367 error = clk_get_by_ofw_name(dev, 0, "apb", &clk); 368 if (error != 0) { 369 device_printf(dev, "cannot get APB clock\n"); 370 goto fail; 371 } 372 373 error = clk_enable(clk); 374 if (error != 0) { 375 device_printf(dev, "cannot enable APB clock\n"); 376 goto fail; 377 } 378 379 if (hwreset_get_by_ofw_idx(dev, 0, 0, &rst) == 0) { 380 error = hwreset_deassert(rst); 381 if (error != 0) { 382 device_printf(dev, "cannot de-assert reset\n"); 383 goto fail; 384 } 385 } 386 387 aw_i2s_init(sc); 388 389 node = ofw_bus_get_node(dev); 390 OF_device_register_xref(OF_xref_from_node(node), dev); 391 392 return (0); 393 394 fail: 395 aw_i2s_detach(dev); 396 return (error); 397 } 398 399 static int 400 aw_i2s_detach(device_t dev) 401 { 402 struct aw_i2s_softc *i2s; 403 404 i2s = device_get_softc(dev); 405 406 if (i2s->clk) 407 clk_release(i2s->clk); 408 409 if (i2s->intrhand != NULL) 410 bus_teardown_intr(i2s->dev, i2s->res[1], i2s->intrhand); 411 412 bus_release_resources(dev, aw_i2s_spec, i2s->res); 413 mtx_destroy(&i2s->mtx); 414 415 return (0); 416 } 417 418 static int 419 aw_i2s_dai_init(device_t dev, uint32_t format) 420 { 421 struct aw_i2s_softc *sc; 422 int fmt, pol; 423 uint32_t ctl, fat0, chsel; 424 u_int offset; 425 426 sc = device_get_softc(dev); 427 428 fmt = AUDIO_DAI_FORMAT_FORMAT(format); 429 pol = AUDIO_DAI_FORMAT_POLARITY(format); 430 431 ctl = I2S_READ(sc, DA_CTL); 432 fat0 = I2S_READ(sc, DA_FAT0); 433 434 if (I2S_TYPE(sc) == SUNXI_I2S_SUN4I) { 435 fat0 &= ~DA_FAT0_FMT_MASK; 436 switch (fmt) { 437 case AUDIO_DAI_FORMAT_I2S: 438 fat0 |= DA_FMT_I2S; 439 break; 440 case AUDIO_DAI_FORMAT_RJ: 441 fat0 |= DA_FMT_RJ; 442 break; 443 case AUDIO_DAI_FORMAT_LJ: 444 fat0 |= DA_FMT_LJ; 445 break; 446 default: 447 return EINVAL; 448 } 449 ctl &= ~DA_CTL_PCM; 450 } else { 451 ctl &= ~DA_CTL_MODE_SEL_MASK; 452 switch (fmt) { 453 case AUDIO_DAI_FORMAT_I2S: 454 ctl |= DA_CTL_MODE_SEL_LJ; 455 offset = 1; 456 break; 457 case AUDIO_DAI_FORMAT_LJ: 458 ctl |= DA_CTL_MODE_SEL_LJ; 459 offset = 0; 460 break; 461 case AUDIO_DAI_FORMAT_RJ: 462 ctl |= DA_CTL_MODE_SEL_RJ; 463 offset = 0; 464 break; 465 case AUDIO_DAI_FORMAT_DSPA: 466 ctl |= DA_CTL_MODE_SEL_PCM; 467 offset = 1; 468 break; 469 case AUDIO_DAI_FORMAT_DSPB: 470 ctl |= DA_CTL_MODE_SEL_PCM; 471 offset = 0; 472 break; 473 default: 474 return EINVAL; 475 } 476 477 chsel = I2S_READ(sc, sc->cfg->txchsel); 478 chsel &= ~DA_CHSEL_OFFSET_MASK; 479 chsel |= DA_CHSEL_OFFSET(offset); 480 I2S_WRITE(sc, sc->cfg->txchsel, chsel); 481 482 chsel = I2S_READ(sc, sc->cfg->rxchsel); 483 chsel &= ~DA_CHSEL_OFFSET_MASK; 484 chsel |= DA_CHSEL_OFFSET(offset); 485 I2S_WRITE(sc, sc->cfg->rxchsel, chsel); 486 } 487 488 fat0 &= ~(DA_FAT0_LRCP_MASK|DA_FAT0_BCP_MASK); 489 if (I2S_TYPE(sc) == SUNXI_I2S_SUN4I) { 490 if (AUDIO_DAI_POLARITY_INVERTED_BCLK(pol)) 491 fat0 |= DA_BCP_INVERTED; 492 if (AUDIO_DAI_POLARITY_INVERTED_FRAME(pol)) 493 fat0 |= DA_LRCP_INVERTED; 494 } else { 495 if (AUDIO_DAI_POLARITY_INVERTED_BCLK(pol)) 496 fat0 |= DA_BCP_INVERTED; 497 if (!AUDIO_DAI_POLARITY_INVERTED_FRAME(pol)) 498 fat0 |= DA_LRCP_INVERTED; 499 500 fat0 &= ~DA_FAT0_LRCK_PERIOD_MASK; 501 fat0 |= DA_FAT0_LRCK_PERIOD(32 - 1); 502 } 503 504 I2S_WRITE(sc, DA_CTL, ctl); 505 I2S_WRITE(sc, DA_FAT0, fat0); 506 507 return (0); 508 } 509 510 511 static int 512 aw_i2s_dai_intr(device_t dev, struct snd_dbuf *play_buf, struct snd_dbuf *rec_buf) 513 { 514 struct aw_i2s_softc *sc; 515 int ret = 0; 516 uint32_t val, status; 517 518 sc = device_get_softc(dev); 519 520 I2S_LOCK(sc); 521 522 status = I2S_READ(sc, DA_ISTA); 523 /* Clear interrupts */ 524 // device_printf(sc->dev, "status: %08x\n", status); 525 I2S_WRITE(sc, DA_ISTA, status); 526 527 if (status & DA_ISTA_TXEI_INT) { 528 uint8_t *samples; 529 uint32_t count, size, readyptr, written, empty; 530 531 val = I2S_READ(sc, DA_FSTA); 532 empty = DA_FSTA_TXE_CNT(val); 533 count = sndbuf_getready(play_buf); 534 size = sndbuf_getsize(play_buf); 535 readyptr = sndbuf_getreadyptr(play_buf); 536 537 samples = (uint8_t*)sndbuf_getbuf(play_buf); 538 written = 0; 539 if (empty > count / 2) 540 empty = count / 2; 541 for (; empty > 0; empty--) { 542 val = (samples[readyptr++ % size] << 16); 543 val |= (samples[readyptr++ % size] << 24); 544 written += 2; 545 I2S_WRITE(sc, DA_TXFIFO, val); 546 } 547 sc->play_ptr += written; 548 sc->play_ptr %= size; 549 ret |= AUDIO_DAI_PLAY_INTR; 550 } 551 552 if (status & DA_ISTA_RXAI_INT) { 553 uint8_t *samples; 554 uint32_t count, size, freeptr, recorded, available; 555 556 val = I2S_READ(sc, DA_FSTA); 557 available = DA_FSTA_RXA_CNT(val); 558 559 count = sndbuf_getfree(rec_buf); 560 size = sndbuf_getsize(rec_buf); 561 freeptr = sndbuf_getfreeptr(rec_buf); 562 samples = (uint8_t*)sndbuf_getbuf(rec_buf); 563 recorded = 0; 564 if (available > count / 2) 565 available = count / 2; 566 567 for (; available > 0; available--) { 568 val = I2S_READ(sc, DA_RXFIFO); 569 samples[freeptr++ % size] = (val >> 16) & 0xff; 570 samples[freeptr++ % size] = (val >> 24) & 0xff; 571 recorded += 2; 572 } 573 sc->rec_ptr += recorded; 574 sc->rec_ptr %= size; 575 ret |= AUDIO_DAI_REC_INTR; 576 } 577 578 I2S_UNLOCK(sc); 579 580 return (ret); 581 } 582 583 static struct pcmchan_caps * 584 aw_i2s_dai_get_caps(device_t dev) 585 { 586 return (&aw_i2s_caps); 587 } 588 589 static int 590 aw_i2s_dai_trigger(device_t dev, int go, int pcm_dir) 591 { 592 struct aw_i2s_softc *sc = device_get_softc(dev); 593 uint32_t val; 594 595 if ((pcm_dir != PCMDIR_PLAY) && (pcm_dir != PCMDIR_REC)) 596 return (EINVAL); 597 598 switch (go) { 599 case PCMTRIG_START: 600 if (pcm_dir == PCMDIR_PLAY) { 601 /* Flush FIFO */ 602 val = I2S_READ(sc, DA_FCTL); 603 I2S_WRITE(sc, DA_FCTL, val | DA_FCTL_FTX); 604 I2S_WRITE(sc, DA_FCTL, val & ~DA_FCTL_FTX); 605 606 /* Reset TX sample counter */ 607 I2S_WRITE(sc, DA_TXCNT, 0); 608 609 /* Enable TX block */ 610 val = I2S_READ(sc, DA_CTL); 611 I2S_WRITE(sc, DA_CTL, val | DA_CTL_TXEN); 612 613 /* Enable TX underrun interrupt */ 614 val = I2S_READ(sc, DA_INT); 615 I2S_WRITE(sc, DA_INT, val | DA_INT_TXEI_EN); 616 } 617 618 if (pcm_dir == PCMDIR_REC) { 619 /* Flush FIFO */ 620 val = I2S_READ(sc, DA_FCTL); 621 I2S_WRITE(sc, DA_FCTL, val | DA_FCTL_FRX); 622 I2S_WRITE(sc, DA_FCTL, val & ~DA_FCTL_FRX); 623 624 /* Reset RX sample counter */ 625 I2S_WRITE(sc, DA_RXCNT, 0); 626 627 /* Enable RX block */ 628 val = I2S_READ(sc, DA_CTL); 629 I2S_WRITE(sc, DA_CTL, val | DA_CTL_RXEN); 630 631 /* Enable RX data available interrupt */ 632 val = I2S_READ(sc, DA_INT); 633 I2S_WRITE(sc, DA_INT, val | DA_INT_RXAI_EN); 634 } 635 636 break; 637 638 case PCMTRIG_STOP: 639 case PCMTRIG_ABORT: 640 I2S_LOCK(sc); 641 642 if (pcm_dir == PCMDIR_PLAY) { 643 /* Disable TX block */ 644 val = I2S_READ(sc, DA_CTL); 645 I2S_WRITE(sc, DA_CTL, val & ~DA_CTL_TXEN); 646 647 /* Enable TX underrun interrupt */ 648 val = I2S_READ(sc, DA_INT); 649 I2S_WRITE(sc, DA_INT, val & ~DA_INT_TXEI_EN); 650 651 sc->play_ptr = 0; 652 } else { 653 /* Disable RX block */ 654 val = I2S_READ(sc, DA_CTL); 655 I2S_WRITE(sc, DA_CTL, val & ~DA_CTL_RXEN); 656 657 /* Disable RX data available interrupt */ 658 val = I2S_READ(sc, DA_INT); 659 I2S_WRITE(sc, DA_INT, val & ~DA_INT_RXAI_EN); 660 661 sc->rec_ptr = 0; 662 } 663 664 I2S_UNLOCK(sc); 665 break; 666 } 667 668 return (0); 669 } 670 671 static uint32_t 672 aw_i2s_dai_get_ptr(device_t dev, int pcm_dir) 673 { 674 struct aw_i2s_softc *sc; 675 uint32_t ptr; 676 677 sc = device_get_softc(dev); 678 679 I2S_LOCK(sc); 680 if (pcm_dir == PCMDIR_PLAY) 681 ptr = sc->play_ptr; 682 else 683 ptr = sc->rec_ptr; 684 I2S_UNLOCK(sc); 685 686 return ptr; 687 } 688 689 static int 690 aw_i2s_dai_setup_intr(device_t dev, driver_intr_t intr_handler, void *intr_arg) 691 { 692 struct aw_i2s_softc *sc = device_get_softc(dev); 693 694 if (bus_setup_intr(dev, sc->res[1], 695 INTR_TYPE_MISC | INTR_MPSAFE, NULL, intr_handler, intr_arg, 696 &sc->intrhand)) { 697 device_printf(dev, "cannot setup interrupt handler\n"); 698 return (ENXIO); 699 } 700 701 return (0); 702 } 703 704 static uint32_t 705 aw_i2s_dai_set_chanformat(device_t dev, uint32_t format) 706 { 707 708 return (0); 709 } 710 711 static int 712 aw_i2s_dai_set_sysclk(device_t dev, unsigned int rate, int dai_dir) 713 { 714 struct aw_i2s_softc *sc; 715 int bclk_val, mclk_val; 716 uint32_t val; 717 int error; 718 719 sc = device_get_softc(dev); 720 721 error = clk_set_freq(sc->clk, AW_I2S_CLK_RATE, CLK_SET_ROUND_DOWN); 722 if (error != 0) { 723 device_printf(sc->dev, 724 "couldn't set mod clock rate to %u Hz: %d\n", AW_I2S_CLK_RATE, error); 725 return error; 726 } 727 error = clk_enable(sc->clk); 728 if (error != 0) { 729 device_printf(sc->dev, 730 "couldn't enable mod clock: %d\n", error); 731 return error; 732 } 733 734 const u_int bclk_prate = I2S_TYPE(sc) == SUNXI_I2S_SUN4I ? rate : AW_I2S_CLK_RATE; 735 736 const u_int bclk_div = bclk_prate / (2 * 32 * AW_I2S_SAMPLE_RATE); 737 const u_int mclk_div = AW_I2S_CLK_RATE / rate; 738 739 if (I2S_TYPE(sc) == SUNXI_I2S_SUN4I) { 740 bclk_val = sunxi_i2s_div_to_regval(sun4i_i2s_bclk_divmap, 741 nitems(sun4i_i2s_bclk_divmap), bclk_div); 742 mclk_val = sunxi_i2s_div_to_regval(sun4i_i2s_mclk_divmap, 743 nitems(sun4i_i2s_mclk_divmap), mclk_div); 744 } else { 745 bclk_val = sunxi_i2s_div_to_regval(sun8i_i2s_divmap, 746 nitems(sun8i_i2s_divmap), bclk_div); 747 mclk_val = sunxi_i2s_div_to_regval(sun8i_i2s_divmap, 748 nitems(sun8i_i2s_divmap), mclk_div); 749 } 750 if (bclk_val == -1 || mclk_val == -1) { 751 device_printf(sc->dev, "couldn't configure bclk/mclk dividers\n"); 752 return EIO; 753 } 754 755 val = I2S_READ(sc, DA_CLKD); 756 if (I2S_TYPE(sc) == SUNXI_I2S_SUN4I) { 757 val |= DA_CLKD_MCLKO_EN_SUN4I; 758 val &= ~DA_CLKD_BCLKDIV_SUN4I_MASK; 759 val |= DA_CLKD_BCLKDIV_SUN4I(bclk_val); 760 } else { 761 val |= DA_CLKD_MCLKO_EN_SUN8I; 762 val &= ~DA_CLKD_BCLKDIV_SUN8I_MASK; 763 val |= DA_CLKD_BCLKDIV_SUN8I(bclk_val); 764 } 765 val &= ~DA_CLKD_MCLKDIV_MASK; 766 val |= DA_CLKD_MCLKDIV(mclk_val); 767 I2S_WRITE(sc, DA_CLKD, val); 768 769 770 return (0); 771 } 772 773 static uint32_t 774 aw_i2s_dai_set_chanspeed(device_t dev, uint32_t speed) 775 { 776 777 return (speed); 778 } 779 780 static device_method_t aw_i2s_methods[] = { 781 /* Device interface */ 782 DEVMETHOD(device_probe, aw_i2s_probe), 783 DEVMETHOD(device_attach, aw_i2s_attach), 784 DEVMETHOD(device_detach, aw_i2s_detach), 785 786 DEVMETHOD(audio_dai_init, aw_i2s_dai_init), 787 DEVMETHOD(audio_dai_setup_intr, aw_i2s_dai_setup_intr), 788 DEVMETHOD(audio_dai_set_sysclk, aw_i2s_dai_set_sysclk), 789 DEVMETHOD(audio_dai_set_chanspeed, aw_i2s_dai_set_chanspeed), 790 DEVMETHOD(audio_dai_set_chanformat, aw_i2s_dai_set_chanformat), 791 DEVMETHOD(audio_dai_intr, aw_i2s_dai_intr), 792 DEVMETHOD(audio_dai_get_caps, aw_i2s_dai_get_caps), 793 DEVMETHOD(audio_dai_trigger, aw_i2s_dai_trigger), 794 DEVMETHOD(audio_dai_get_ptr, aw_i2s_dai_get_ptr), 795 796 DEVMETHOD_END 797 }; 798 799 static driver_t aw_i2s_driver = { 800 "i2s", 801 aw_i2s_methods, 802 sizeof(struct aw_i2s_softc), 803 }; 804 805 DRIVER_MODULE(aw_i2s, simplebus, aw_i2s_driver, 0, 0); 806 SIMPLEBUS_PNP_INFO(compat_data); 807