1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2018 Emmanuel Vadot <manu@FreeBSD.org> 5 * Copyright (c) 2013 Alexander Fedorov 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/bus.h> 36 #include <sys/kernel.h> 37 #include <sys/lock.h> 38 #include <sys/malloc.h> 39 #include <sys/module.h> 40 #include <sys/mutex.h> 41 #include <sys/resource.h> 42 #include <sys/rman.h> 43 #include <sys/sysctl.h> 44 45 #include <machine/bus.h> 46 47 #include <dev/ofw/ofw_bus.h> 48 #include <dev/ofw/ofw_bus_subr.h> 49 50 #include <dev/mmc/bridge.h> 51 #include <dev/mmc/mmcbrvar.h> 52 53 #include <arm/allwinner/aw_mmc.h> 54 #include <dev/extres/clk/clk.h> 55 #include <dev/extres/hwreset/hwreset.h> 56 #include <dev/extres/regulator/regulator.h> 57 58 #include "opt_mmccam.h" 59 60 #ifdef MMCCAM 61 #include <cam/cam.h> 62 #include <cam/cam_ccb.h> 63 #include <cam/cam_debug.h> 64 #include <cam/cam_sim.h> 65 #include <cam/cam_xpt_sim.h> 66 #endif 67 68 #define AW_MMC_MEMRES 0 69 #define AW_MMC_IRQRES 1 70 #define AW_MMC_RESSZ 2 71 #define AW_MMC_DMA_SEGS (PAGE_SIZE / sizeof(struct aw_mmc_dma_desc)) 72 #define AW_MMC_DMA_DESC_SIZE (sizeof(struct aw_mmc_dma_desc) * AW_MMC_DMA_SEGS) 73 #define AW_MMC_DMA_FTRGLEVEL 0x20070008 74 75 #define AW_MMC_RESET_RETRY 1000 76 77 #define CARD_ID_FREQUENCY 400000 78 79 struct aw_mmc_conf { 80 uint32_t dma_xferlen; 81 bool mask_data0; 82 bool can_calibrate; 83 bool new_timing; 84 }; 85 86 static const struct aw_mmc_conf a10_mmc_conf = { 87 .dma_xferlen = 0x2000, 88 }; 89 90 static const struct aw_mmc_conf a13_mmc_conf = { 91 .dma_xferlen = 0x10000, 92 }; 93 94 static const struct aw_mmc_conf a64_mmc_conf = { 95 .dma_xferlen = 0x10000, 96 .mask_data0 = true, 97 .can_calibrate = true, 98 .new_timing = true, 99 }; 100 101 static const struct aw_mmc_conf a64_emmc_conf = { 102 .dma_xferlen = 0x2000, 103 .can_calibrate = true, 104 }; 105 106 static struct ofw_compat_data compat_data[] = { 107 {"allwinner,sun4i-a10-mmc", (uintptr_t)&a10_mmc_conf}, 108 {"allwinner,sun5i-a13-mmc", (uintptr_t)&a13_mmc_conf}, 109 {"allwinner,sun7i-a20-mmc", (uintptr_t)&a13_mmc_conf}, 110 {"allwinner,sun50i-a64-mmc", (uintptr_t)&a64_mmc_conf}, 111 {"allwinner,sun50i-a64-emmc", (uintptr_t)&a64_emmc_conf}, 112 {NULL, 0} 113 }; 114 115 struct aw_mmc_softc { 116 device_t aw_dev; 117 clk_t aw_clk_ahb; 118 clk_t aw_clk_mmc; 119 hwreset_t aw_rst_ahb; 120 int aw_bus_busy; 121 int aw_resid; 122 int aw_timeout; 123 struct callout aw_timeoutc; 124 struct mmc_host aw_host; 125 #ifdef MMCCAM 126 union ccb * ccb; 127 struct cam_devq * devq; 128 struct cam_sim * sim; 129 struct mtx sim_mtx; 130 #else 131 struct mmc_request * aw_req; 132 #endif 133 struct mtx aw_mtx; 134 struct resource * aw_res[AW_MMC_RESSZ]; 135 struct aw_mmc_conf * aw_mmc_conf; 136 uint32_t aw_intr; 137 uint32_t aw_intr_wait; 138 void * aw_intrhand; 139 regulator_t aw_reg_vmmc; 140 regulator_t aw_reg_vqmmc; 141 unsigned int aw_clock; 142 143 /* Fields required for DMA access. */ 144 bus_addr_t aw_dma_desc_phys; 145 bus_dmamap_t aw_dma_map; 146 bus_dma_tag_t aw_dma_tag; 147 void * aw_dma_desc; 148 bus_dmamap_t aw_dma_buf_map; 149 bus_dma_tag_t aw_dma_buf_tag; 150 int aw_dma_map_err; 151 }; 152 153 static struct resource_spec aw_mmc_res_spec[] = { 154 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 155 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 156 { -1, 0, 0 } 157 }; 158 159 static int aw_mmc_probe(device_t); 160 static int aw_mmc_attach(device_t); 161 static int aw_mmc_detach(device_t); 162 static int aw_mmc_setup_dma(struct aw_mmc_softc *); 163 static int aw_mmc_reset(struct aw_mmc_softc *); 164 static int aw_mmc_init(struct aw_mmc_softc *); 165 static void aw_mmc_intr(void *); 166 static int aw_mmc_update_clock(struct aw_mmc_softc *, uint32_t); 167 168 static void aw_mmc_print_error(uint32_t); 169 static int aw_mmc_update_ios(device_t, device_t); 170 static int aw_mmc_request(device_t, device_t, struct mmc_request *); 171 static int aw_mmc_get_ro(device_t, device_t); 172 static int aw_mmc_acquire_host(device_t, device_t); 173 static int aw_mmc_release_host(device_t, device_t); 174 #ifdef MMCCAM 175 static void aw_mmc_cam_action(struct cam_sim *, union ccb *); 176 static void aw_mmc_cam_poll(struct cam_sim *); 177 static int aw_mmc_cam_settran_settings(struct aw_mmc_softc *, union ccb *); 178 static int aw_mmc_cam_request(struct aw_mmc_softc *, union ccb *); 179 static void aw_mmc_cam_handle_mmcio(struct cam_sim *, union ccb *); 180 #endif 181 182 #define AW_MMC_LOCK(_sc) mtx_lock(&(_sc)->aw_mtx) 183 #define AW_MMC_UNLOCK(_sc) mtx_unlock(&(_sc)->aw_mtx) 184 #define AW_MMC_READ_4(_sc, _reg) \ 185 bus_read_4((_sc)->aw_res[AW_MMC_MEMRES], _reg) 186 #define AW_MMC_WRITE_4(_sc, _reg, _value) \ 187 bus_write_4((_sc)->aw_res[AW_MMC_MEMRES], _reg, _value) 188 189 #ifdef MMCCAM 190 static void 191 aw_mmc_cam_handle_mmcio(struct cam_sim *sim, union ccb *ccb) 192 { 193 struct aw_mmc_softc *sc; 194 195 sc = cam_sim_softc(sim); 196 197 aw_mmc_cam_request(sc, ccb); 198 } 199 200 static void 201 aw_mmc_cam_action(struct cam_sim *sim, union ccb *ccb) 202 { 203 struct aw_mmc_softc *sc; 204 205 sc = cam_sim_softc(sim); 206 if (sc == NULL) { 207 ccb->ccb_h.status = CAM_SEL_TIMEOUT; 208 xpt_done(ccb); 209 return; 210 } 211 212 mtx_assert(&sc->sim_mtx, MA_OWNED); 213 214 switch (ccb->ccb_h.func_code) { 215 case XPT_PATH_INQ: 216 { 217 struct ccb_pathinq *cpi; 218 219 cpi = &ccb->cpi; 220 cpi->version_num = 1; 221 cpi->hba_inquiry = 0; 222 cpi->target_sprt = 0; 223 cpi->hba_misc = PIM_NOBUSRESET | PIM_SEQSCAN; 224 cpi->hba_eng_cnt = 0; 225 cpi->max_target = 0; 226 cpi->max_lun = 0; 227 cpi->initiator_id = 1; 228 cpi->maxio = (sc->aw_mmc_conf->dma_xferlen * 229 AW_MMC_DMA_SEGS) / MMC_SECTOR_SIZE; 230 strncpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN); 231 strncpy(cpi->hba_vid, "Deglitch Networks", HBA_IDLEN); 232 strncpy(cpi->dev_name, cam_sim_name(sim), DEV_IDLEN); 233 cpi->unit_number = cam_sim_unit(sim); 234 cpi->bus_id = cam_sim_bus(sim); 235 cpi->protocol = PROTO_MMCSD; 236 cpi->protocol_version = SCSI_REV_0; 237 cpi->transport = XPORT_MMCSD; 238 cpi->transport_version = 1; 239 240 cpi->ccb_h.status = CAM_REQ_CMP; 241 break; 242 } 243 case XPT_GET_TRAN_SETTINGS: 244 { 245 struct ccb_trans_settings *cts = &ccb->cts; 246 247 if (bootverbose) 248 device_printf(sc->aw_dev, "Got XPT_GET_TRAN_SETTINGS\n"); 249 250 cts->protocol = PROTO_MMCSD; 251 cts->protocol_version = 1; 252 cts->transport = XPORT_MMCSD; 253 cts->transport_version = 1; 254 cts->xport_specific.valid = 0; 255 cts->proto_specific.mmc.host_ocr = sc->aw_host.host_ocr; 256 cts->proto_specific.mmc.host_f_min = sc->aw_host.f_min; 257 cts->proto_specific.mmc.host_f_max = sc->aw_host.f_max; 258 cts->proto_specific.mmc.host_caps = sc->aw_host.caps; 259 memcpy(&cts->proto_specific.mmc.ios, &sc->aw_host.ios, sizeof(struct mmc_ios)); 260 ccb->ccb_h.status = CAM_REQ_CMP; 261 break; 262 } 263 case XPT_SET_TRAN_SETTINGS: 264 { 265 if (bootverbose) 266 device_printf(sc->aw_dev, "Got XPT_SET_TRAN_SETTINGS\n"); 267 aw_mmc_cam_settran_settings(sc, ccb); 268 ccb->ccb_h.status = CAM_REQ_CMP; 269 break; 270 } 271 case XPT_RESET_BUS: 272 if (bootverbose) 273 device_printf(sc->aw_dev, "Got XPT_RESET_BUS, ACK it...\n"); 274 ccb->ccb_h.status = CAM_REQ_CMP; 275 break; 276 case XPT_MMC_IO: 277 /* 278 * Here is the HW-dependent part of 279 * sending the command to the underlying h/w 280 * At some point in the future an interrupt comes. 281 * Then the request will be marked as completed. 282 */ 283 ccb->ccb_h.status = CAM_REQ_INPROG; 284 285 aw_mmc_cam_handle_mmcio(sim, ccb); 286 return; 287 /* NOTREACHED */ 288 break; 289 default: 290 ccb->ccb_h.status = CAM_REQ_INVALID; 291 break; 292 } 293 xpt_done(ccb); 294 return; 295 } 296 297 static void 298 aw_mmc_cam_poll(struct cam_sim *sim) 299 { 300 return; 301 } 302 303 static int 304 aw_mmc_cam_settran_settings(struct aw_mmc_softc *sc, union ccb *ccb) 305 { 306 struct mmc_ios *ios; 307 struct mmc_ios *new_ios; 308 struct ccb_trans_settings_mmc *cts; 309 310 ios = &sc->aw_host.ios; 311 312 cts = &ccb->cts.proto_specific.mmc; 313 new_ios = &cts->ios; 314 315 /* Update only requested fields */ 316 if (cts->ios_valid & MMC_CLK) { 317 ios->clock = new_ios->clock; 318 device_printf(sc->aw_dev, "Clock => %d\n", ios->clock); 319 } 320 if (cts->ios_valid & MMC_VDD) { 321 ios->vdd = new_ios->vdd; 322 device_printf(sc->aw_dev, "VDD => %d\n", ios->vdd); 323 } 324 if (cts->ios_valid & MMC_CS) { 325 ios->chip_select = new_ios->chip_select; 326 device_printf(sc->aw_dev, "CS => %d\n", ios->chip_select); 327 } 328 if (cts->ios_valid & MMC_BW) { 329 ios->bus_width = new_ios->bus_width; 330 device_printf(sc->aw_dev, "Bus width => %d\n", ios->bus_width); 331 } 332 if (cts->ios_valid & MMC_PM) { 333 ios->power_mode = new_ios->power_mode; 334 device_printf(sc->aw_dev, "Power mode => %d\n", ios->power_mode); 335 } 336 if (cts->ios_valid & MMC_BT) { 337 ios->timing = new_ios->timing; 338 device_printf(sc->aw_dev, "Timing => %d\n", ios->timing); 339 } 340 if (cts->ios_valid & MMC_BM) { 341 ios->bus_mode = new_ios->bus_mode; 342 device_printf(sc->aw_dev, "Bus mode => %d\n", ios->bus_mode); 343 } 344 345 return (aw_mmc_update_ios(sc->aw_dev, NULL)); 346 } 347 348 static int 349 aw_mmc_cam_request(struct aw_mmc_softc *sc, union ccb *ccb) 350 { 351 struct ccb_mmcio *mmcio; 352 353 mmcio = &ccb->mmcio; 354 355 AW_MMC_LOCK(sc); 356 357 #ifdef DEBUG 358 if (__predict_false(bootverbose)) { 359 device_printf(sc->aw_dev, "CMD%u arg %#x flags %#x dlen %u dflags %#x\n", 360 mmcio->cmd.opcode, mmcio->cmd.arg, mmcio->cmd.flags, 361 mmcio->cmd.data != NULL ? (unsigned int) mmcio->cmd.data->len : 0, 362 mmcio->cmd.data != NULL ? mmcio->cmd.data->flags: 0); 363 } 364 #endif 365 if (mmcio->cmd.data != NULL) { 366 if (mmcio->cmd.data->len == 0 || mmcio->cmd.data->flags == 0) 367 panic("data->len = %d, data->flags = %d -- something is b0rked", 368 (int)mmcio->cmd.data->len, mmcio->cmd.data->flags); 369 } 370 if (sc->ccb != NULL) { 371 device_printf(sc->aw_dev, "Controller still has an active command\n"); 372 return (EBUSY); 373 } 374 sc->ccb = ccb; 375 /* aw_mmc_request locks again */ 376 AW_MMC_UNLOCK(sc); 377 aw_mmc_request(sc->aw_dev, NULL, NULL); 378 379 return (0); 380 } 381 #endif /* MMCCAM */ 382 383 static int 384 aw_mmc_probe(device_t dev) 385 { 386 387 if (!ofw_bus_status_okay(dev)) 388 return (ENXIO); 389 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) 390 return (ENXIO); 391 392 device_set_desc(dev, "Allwinner Integrated MMC/SD controller"); 393 394 return (BUS_PROBE_DEFAULT); 395 } 396 397 static int 398 aw_mmc_attach(device_t dev) 399 { 400 device_t child; 401 struct aw_mmc_softc *sc; 402 struct sysctl_ctx_list *ctx; 403 struct sysctl_oid_list *tree; 404 uint32_t bus_width, max_freq; 405 phandle_t node; 406 int error; 407 408 node = ofw_bus_get_node(dev); 409 sc = device_get_softc(dev); 410 sc->aw_dev = dev; 411 412 sc->aw_mmc_conf = (struct aw_mmc_conf *)ofw_bus_search_compatible(dev, compat_data)->ocd_data; 413 414 #ifndef MMCCAM 415 sc->aw_req = NULL; 416 #endif 417 if (bus_alloc_resources(dev, aw_mmc_res_spec, sc->aw_res) != 0) { 418 device_printf(dev, "cannot allocate device resources\n"); 419 return (ENXIO); 420 } 421 if (bus_setup_intr(dev, sc->aw_res[AW_MMC_IRQRES], 422 INTR_TYPE_MISC | INTR_MPSAFE, NULL, aw_mmc_intr, sc, 423 &sc->aw_intrhand)) { 424 bus_release_resources(dev, aw_mmc_res_spec, sc->aw_res); 425 device_printf(dev, "cannot setup interrupt handler\n"); 426 return (ENXIO); 427 } 428 mtx_init(&sc->aw_mtx, device_get_nameunit(sc->aw_dev), "aw_mmc", 429 MTX_DEF); 430 callout_init_mtx(&sc->aw_timeoutc, &sc->aw_mtx, 0); 431 432 /* De-assert reset */ 433 if (hwreset_get_by_ofw_name(dev, 0, "ahb", &sc->aw_rst_ahb) == 0) { 434 error = hwreset_deassert(sc->aw_rst_ahb); 435 if (error != 0) { 436 device_printf(dev, "cannot de-assert reset\n"); 437 goto fail; 438 } 439 } 440 441 /* Activate the module clock. */ 442 error = clk_get_by_ofw_name(dev, 0, "ahb", &sc->aw_clk_ahb); 443 if (error != 0) { 444 device_printf(dev, "cannot get ahb clock\n"); 445 goto fail; 446 } 447 error = clk_enable(sc->aw_clk_ahb); 448 if (error != 0) { 449 device_printf(dev, "cannot enable ahb clock\n"); 450 goto fail; 451 } 452 error = clk_get_by_ofw_name(dev, 0, "mmc", &sc->aw_clk_mmc); 453 if (error != 0) { 454 device_printf(dev, "cannot get mmc clock\n"); 455 goto fail; 456 } 457 error = clk_set_freq(sc->aw_clk_mmc, CARD_ID_FREQUENCY, 458 CLK_SET_ROUND_DOWN); 459 if (error != 0) { 460 device_printf(dev, "cannot init mmc clock\n"); 461 goto fail; 462 } 463 error = clk_enable(sc->aw_clk_mmc); 464 if (error != 0) { 465 device_printf(dev, "cannot enable mmc clock\n"); 466 goto fail; 467 } 468 469 sc->aw_timeout = 10; 470 ctx = device_get_sysctl_ctx(dev); 471 tree = SYSCTL_CHILDREN(device_get_sysctl_tree(dev)); 472 SYSCTL_ADD_INT(ctx, tree, OID_AUTO, "req_timeout", CTLFLAG_RW, 473 &sc->aw_timeout, 0, "Request timeout in seconds"); 474 475 /* Soft Reset controller. */ 476 if (aw_mmc_reset(sc) != 0) { 477 device_printf(dev, "cannot reset the controller\n"); 478 goto fail; 479 } 480 481 if (aw_mmc_setup_dma(sc) != 0) { 482 device_printf(sc->aw_dev, "Couldn't setup DMA!\n"); 483 goto fail; 484 } 485 486 if (OF_getencprop(node, "bus-width", &bus_width, sizeof(uint32_t)) <= 0) 487 bus_width = 4; 488 489 if (regulator_get_by_ofw_property(dev, 0, "vmmc-supply", 490 &sc->aw_reg_vmmc) == 0) { 491 if (bootverbose) 492 device_printf(dev, "vmmc-supply regulator found\n"); 493 } 494 if (regulator_get_by_ofw_property(dev, 0, "vqmmc-supply", 495 &sc->aw_reg_vqmmc) == 0 && bootverbose) { 496 if (bootverbose) 497 device_printf(dev, "vqmmc-supply regulator found\n"); 498 } 499 500 sc->aw_host.f_min = 400000; 501 502 if (OF_getencprop(node, "max-frequency", &max_freq, 503 sizeof(uint32_t)) <= 0) 504 max_freq = 52000000; 505 sc->aw_host.f_max = max_freq; 506 507 sc->aw_host.host_ocr = MMC_OCR_320_330 | MMC_OCR_330_340; 508 sc->aw_host.caps = MMC_CAP_HSPEED | MMC_CAP_UHS_SDR12 | 509 MMC_CAP_UHS_SDR25 | MMC_CAP_UHS_SDR50 | 510 MMC_CAP_UHS_DDR50 | MMC_CAP_MMC_DDR52; 511 512 sc->aw_host.caps |= MMC_CAP_SIGNALING_330 | MMC_CAP_SIGNALING_180; 513 514 if (bus_width >= 4) 515 sc->aw_host.caps |= MMC_CAP_4_BIT_DATA; 516 if (bus_width >= 8) 517 sc->aw_host.caps |= MMC_CAP_8_BIT_DATA; 518 519 #ifdef MMCCAM 520 child = NULL; /* Not used by MMCCAM, need to silence compiler warnings */ 521 sc->ccb = NULL; 522 if ((sc->devq = cam_simq_alloc(1)) == NULL) { 523 goto fail; 524 } 525 526 mtx_init(&sc->sim_mtx, "awmmcsim", NULL, MTX_DEF); 527 sc->sim = cam_sim_alloc(aw_mmc_cam_action, aw_mmc_cam_poll, 528 "aw_mmc_sim", sc, device_get_unit(dev), 529 &sc->sim_mtx, 1, 1, sc->devq); 530 531 if (sc->sim == NULL) { 532 cam_simq_free(sc->devq); 533 device_printf(dev, "cannot allocate CAM SIM\n"); 534 goto fail; 535 } 536 537 mtx_lock(&sc->sim_mtx); 538 if (xpt_bus_register(sc->sim, sc->aw_dev, 0) != 0) { 539 device_printf(dev, "cannot register SCSI pass-through bus\n"); 540 cam_sim_free(sc->sim, FALSE); 541 cam_simq_free(sc->devq); 542 mtx_unlock(&sc->sim_mtx); 543 goto fail; 544 } 545 546 mtx_unlock(&sc->sim_mtx); 547 #else /* !MMCCAM */ 548 child = device_add_child(dev, "mmc", -1); 549 if (child == NULL) { 550 device_printf(dev, "attaching MMC bus failed!\n"); 551 goto fail; 552 } 553 if (device_probe_and_attach(child) != 0) { 554 device_printf(dev, "attaching MMC child failed!\n"); 555 device_delete_child(dev, child); 556 goto fail; 557 } 558 #endif /* MMCCAM */ 559 return (0); 560 561 fail: 562 callout_drain(&sc->aw_timeoutc); 563 mtx_destroy(&sc->aw_mtx); 564 bus_teardown_intr(dev, sc->aw_res[AW_MMC_IRQRES], sc->aw_intrhand); 565 bus_release_resources(dev, aw_mmc_res_spec, sc->aw_res); 566 567 #ifdef MMCCAM 568 if (sc->sim != NULL) { 569 mtx_lock(&sc->sim_mtx); 570 xpt_bus_deregister(cam_sim_path(sc->sim)); 571 cam_sim_free(sc->sim, FALSE); 572 mtx_unlock(&sc->sim_mtx); 573 } 574 575 if (sc->devq != NULL) 576 cam_simq_free(sc->devq); 577 #endif 578 return (ENXIO); 579 } 580 581 static int 582 aw_mmc_detach(device_t dev) 583 { 584 585 return (EBUSY); 586 } 587 588 static void 589 aw_dma_desc_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int err) 590 { 591 struct aw_mmc_softc *sc; 592 593 sc = (struct aw_mmc_softc *)arg; 594 if (err) { 595 sc->aw_dma_map_err = err; 596 return; 597 } 598 sc->aw_dma_desc_phys = segs[0].ds_addr; 599 } 600 601 static int 602 aw_mmc_setup_dma(struct aw_mmc_softc *sc) 603 { 604 int error; 605 606 /* Allocate the DMA descriptor memory. */ 607 error = bus_dma_tag_create( 608 bus_get_dma_tag(sc->aw_dev), /* parent */ 609 AW_MMC_DMA_ALIGN, 0, /* align, boundary */ 610 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 611 BUS_SPACE_MAXADDR, /* highaddr */ 612 NULL, NULL, /* filter, filterarg*/ 613 AW_MMC_DMA_DESC_SIZE, 1, /* maxsize, nsegment */ 614 AW_MMC_DMA_DESC_SIZE, /* maxsegsize */ 615 0, /* flags */ 616 NULL, NULL, /* lock, lockarg*/ 617 &sc->aw_dma_tag); 618 if (error) 619 return (error); 620 621 error = bus_dmamem_alloc(sc->aw_dma_tag, &sc->aw_dma_desc, 622 BUS_DMA_COHERENT | BUS_DMA_WAITOK | BUS_DMA_ZERO, 623 &sc->aw_dma_map); 624 if (error) 625 return (error); 626 627 error = bus_dmamap_load(sc->aw_dma_tag, 628 sc->aw_dma_map, 629 sc->aw_dma_desc, AW_MMC_DMA_DESC_SIZE, 630 aw_dma_desc_cb, sc, 0); 631 if (error) 632 return (error); 633 if (sc->aw_dma_map_err) 634 return (sc->aw_dma_map_err); 635 636 /* Create the DMA map for data transfers. */ 637 error = bus_dma_tag_create( 638 bus_get_dma_tag(sc->aw_dev), /* parent */ 639 AW_MMC_DMA_ALIGN, 0, /* align, boundary */ 640 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 641 BUS_SPACE_MAXADDR, /* highaddr */ 642 NULL, NULL, /* filter, filterarg*/ 643 sc->aw_mmc_conf->dma_xferlen * 644 AW_MMC_DMA_SEGS, AW_MMC_DMA_SEGS, /* maxsize, nsegments */ 645 sc->aw_mmc_conf->dma_xferlen, /* maxsegsize */ 646 BUS_DMA_ALLOCNOW, /* flags */ 647 NULL, NULL, /* lock, lockarg*/ 648 &sc->aw_dma_buf_tag); 649 if (error) 650 return (error); 651 error = bus_dmamap_create(sc->aw_dma_buf_tag, 0, 652 &sc->aw_dma_buf_map); 653 if (error) 654 return (error); 655 656 return (0); 657 } 658 659 static void 660 aw_dma_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int err) 661 { 662 int i; 663 struct aw_mmc_dma_desc *dma_desc; 664 struct aw_mmc_softc *sc; 665 666 sc = (struct aw_mmc_softc *)arg; 667 sc->aw_dma_map_err = err; 668 669 if (err) 670 return; 671 672 dma_desc = sc->aw_dma_desc; 673 for (i = 0; i < nsegs; i++) { 674 if (segs[i].ds_len == sc->aw_mmc_conf->dma_xferlen) 675 dma_desc[i].buf_size = 0; /* Size of 0 indicate max len */ 676 else 677 dma_desc[i].buf_size = segs[i].ds_len; 678 dma_desc[i].buf_addr = segs[i].ds_addr; 679 dma_desc[i].config = AW_MMC_DMA_CONFIG_CH | 680 AW_MMC_DMA_CONFIG_OWN | AW_MMC_DMA_CONFIG_DIC; 681 682 dma_desc[i].next = sc->aw_dma_desc_phys + 683 ((i + 1) * sizeof(struct aw_mmc_dma_desc)); 684 } 685 686 dma_desc[0].config |= AW_MMC_DMA_CONFIG_FD; 687 dma_desc[nsegs - 1].config |= AW_MMC_DMA_CONFIG_LD | 688 AW_MMC_DMA_CONFIG_ER; 689 dma_desc[nsegs - 1].config &= ~AW_MMC_DMA_CONFIG_DIC; 690 dma_desc[nsegs - 1].next = 0; 691 } 692 693 static int 694 aw_mmc_prepare_dma(struct aw_mmc_softc *sc) 695 { 696 bus_dmasync_op_t sync_op; 697 int error; 698 struct mmc_command *cmd; 699 uint32_t val; 700 701 #ifdef MMCCAM 702 cmd = &sc->ccb->mmcio.cmd; 703 #else 704 cmd = sc->aw_req->cmd; 705 #endif 706 if (cmd->data->len > (sc->aw_mmc_conf->dma_xferlen * AW_MMC_DMA_SEGS)) 707 return (EFBIG); 708 error = bus_dmamap_load(sc->aw_dma_buf_tag, sc->aw_dma_buf_map, 709 cmd->data->data, cmd->data->len, aw_dma_cb, sc, 0); 710 if (error) 711 return (error); 712 if (sc->aw_dma_map_err) 713 return (sc->aw_dma_map_err); 714 715 if (cmd->data->flags & MMC_DATA_WRITE) 716 sync_op = BUS_DMASYNC_PREWRITE; 717 else 718 sync_op = BUS_DMASYNC_PREREAD; 719 bus_dmamap_sync(sc->aw_dma_buf_tag, sc->aw_dma_buf_map, sync_op); 720 bus_dmamap_sync(sc->aw_dma_tag, sc->aw_dma_map, BUS_DMASYNC_PREWRITE); 721 722 /* Enable DMA */ 723 val = AW_MMC_READ_4(sc, AW_MMC_GCTL); 724 val &= ~AW_MMC_GCTL_FIFO_AC_MOD; 725 val |= AW_MMC_GCTL_DMA_ENB; 726 AW_MMC_WRITE_4(sc, AW_MMC_GCTL, val); 727 728 /* Reset DMA */ 729 val |= AW_MMC_GCTL_DMA_RST; 730 AW_MMC_WRITE_4(sc, AW_MMC_GCTL, val); 731 732 AW_MMC_WRITE_4(sc, AW_MMC_DMAC, AW_MMC_DMAC_IDMAC_SOFT_RST); 733 AW_MMC_WRITE_4(sc, AW_MMC_DMAC, 734 AW_MMC_DMAC_IDMAC_IDMA_ON | AW_MMC_DMAC_IDMAC_FIX_BURST); 735 736 /* Enable RX or TX DMA interrupt */ 737 val = AW_MMC_READ_4(sc, AW_MMC_IDIE); 738 if (cmd->data->flags & MMC_DATA_WRITE) 739 val |= AW_MMC_IDST_TX_INT; 740 else 741 val |= AW_MMC_IDST_RX_INT; 742 AW_MMC_WRITE_4(sc, AW_MMC_IDIE, val); 743 744 /* Set DMA descritptor list address */ 745 AW_MMC_WRITE_4(sc, AW_MMC_DLBA, sc->aw_dma_desc_phys); 746 747 /* FIFO trigger level */ 748 AW_MMC_WRITE_4(sc, AW_MMC_FWLR, AW_MMC_DMA_FTRGLEVEL); 749 750 return (0); 751 } 752 753 static int 754 aw_mmc_reset(struct aw_mmc_softc *sc) 755 { 756 uint32_t reg; 757 int timeout; 758 759 reg = AW_MMC_READ_4(sc, AW_MMC_GCTL); 760 reg |= AW_MMC_GCTL_RESET; 761 AW_MMC_WRITE_4(sc, AW_MMC_GCTL, reg); 762 timeout = AW_MMC_RESET_RETRY; 763 while (--timeout > 0) { 764 if ((AW_MMC_READ_4(sc, AW_MMC_GCTL) & AW_MMC_GCTL_RESET) == 0) 765 break; 766 DELAY(100); 767 } 768 if (timeout == 0) 769 return (ETIMEDOUT); 770 771 return (0); 772 } 773 774 static int 775 aw_mmc_init(struct aw_mmc_softc *sc) 776 { 777 uint32_t reg; 778 int ret; 779 780 ret = aw_mmc_reset(sc); 781 if (ret != 0) 782 return (ret); 783 784 /* Set the timeout. */ 785 AW_MMC_WRITE_4(sc, AW_MMC_TMOR, 786 AW_MMC_TMOR_DTO_LMT_SHIFT(AW_MMC_TMOR_DTO_LMT_MASK) | 787 AW_MMC_TMOR_RTO_LMT_SHIFT(AW_MMC_TMOR_RTO_LMT_MASK)); 788 789 /* Unmask interrupts. */ 790 AW_MMC_WRITE_4(sc, AW_MMC_IMKR, 0); 791 792 /* Clear pending interrupts. */ 793 AW_MMC_WRITE_4(sc, AW_MMC_RISR, 0xffffffff); 794 795 /* Debug register, undocumented */ 796 AW_MMC_WRITE_4(sc, AW_MMC_DBGC, 0xdeb); 797 798 /* Function select register */ 799 AW_MMC_WRITE_4(sc, AW_MMC_FUNS, 0xceaa0000); 800 801 AW_MMC_WRITE_4(sc, AW_MMC_IDST, 0xffffffff); 802 803 /* Enable interrupts and disable AHB access. */ 804 reg = AW_MMC_READ_4(sc, AW_MMC_GCTL); 805 reg |= AW_MMC_GCTL_INT_ENB; 806 reg &= ~AW_MMC_GCTL_FIFO_AC_MOD; 807 reg &= ~AW_MMC_GCTL_WAIT_MEM_ACCESS; 808 AW_MMC_WRITE_4(sc, AW_MMC_GCTL, reg); 809 810 return (0); 811 } 812 813 static void 814 aw_mmc_req_done(struct aw_mmc_softc *sc) 815 { 816 struct mmc_command *cmd; 817 #ifdef MMCCAM 818 union ccb *ccb; 819 #else 820 struct mmc_request *req; 821 #endif 822 uint32_t val, mask; 823 int retry; 824 825 #ifdef MMCCAM 826 ccb = sc->ccb; 827 cmd = &ccb->mmcio.cmd; 828 #else 829 cmd = sc->aw_req->cmd; 830 #endif 831 #ifdef DEBUG 832 if (bootverbose) { 833 device_printf(sc->aw_dev, "%s: cmd %d err %d\n", __func__, cmd->opcode, cmd->error); 834 } 835 #endif 836 if (cmd->error != MMC_ERR_NONE) { 837 /* Reset the FIFO and DMA engines. */ 838 mask = AW_MMC_GCTL_FIFO_RST | AW_MMC_GCTL_DMA_RST; 839 val = AW_MMC_READ_4(sc, AW_MMC_GCTL); 840 AW_MMC_WRITE_4(sc, AW_MMC_GCTL, val | mask); 841 842 retry = AW_MMC_RESET_RETRY; 843 while (--retry > 0) { 844 if ((AW_MMC_READ_4(sc, AW_MMC_GCTL) & 845 AW_MMC_GCTL_RESET) == 0) 846 break; 847 DELAY(100); 848 } 849 if (retry == 0) 850 device_printf(sc->aw_dev, 851 "timeout resetting DMA/FIFO\n"); 852 aw_mmc_update_clock(sc, 1); 853 } 854 855 callout_stop(&sc->aw_timeoutc); 856 sc->aw_intr = 0; 857 sc->aw_resid = 0; 858 sc->aw_dma_map_err = 0; 859 sc->aw_intr_wait = 0; 860 #ifdef MMCCAM 861 sc->ccb = NULL; 862 ccb->ccb_h.status = 863 (ccb->mmcio.cmd.error == 0 ? CAM_REQ_CMP : CAM_REQ_CMP_ERR); 864 xpt_done(ccb); 865 #else 866 req = sc->aw_req; 867 sc->aw_req = NULL; 868 req->done(req); 869 #endif 870 } 871 872 static void 873 aw_mmc_req_ok(struct aw_mmc_softc *sc) 874 { 875 int timeout; 876 struct mmc_command *cmd; 877 uint32_t status; 878 879 timeout = 1000; 880 while (--timeout > 0) { 881 status = AW_MMC_READ_4(sc, AW_MMC_STAR); 882 if ((status & AW_MMC_STAR_CARD_BUSY) == 0) 883 break; 884 DELAY(1000); 885 } 886 #ifdef MMCCAM 887 cmd = &sc->ccb->mmcio.cmd; 888 #else 889 cmd = sc->aw_req->cmd; 890 #endif 891 if (timeout == 0) { 892 cmd->error = MMC_ERR_FAILED; 893 aw_mmc_req_done(sc); 894 return; 895 } 896 if (cmd->flags & MMC_RSP_PRESENT) { 897 if (cmd->flags & MMC_RSP_136) { 898 cmd->resp[0] = AW_MMC_READ_4(sc, AW_MMC_RESP3); 899 cmd->resp[1] = AW_MMC_READ_4(sc, AW_MMC_RESP2); 900 cmd->resp[2] = AW_MMC_READ_4(sc, AW_MMC_RESP1); 901 cmd->resp[3] = AW_MMC_READ_4(sc, AW_MMC_RESP0); 902 } else 903 cmd->resp[0] = AW_MMC_READ_4(sc, AW_MMC_RESP0); 904 } 905 /* All data has been transferred ? */ 906 if (cmd->data != NULL && (sc->aw_resid << 2) < cmd->data->len) 907 cmd->error = MMC_ERR_FAILED; 908 aw_mmc_req_done(sc); 909 } 910 911 912 static inline void 913 set_mmc_error(struct aw_mmc_softc *sc, int error_code) 914 { 915 #ifdef MMCCAM 916 sc->ccb->mmcio.cmd.error = error_code; 917 #else 918 sc->aw_req->cmd->error = error_code; 919 #endif 920 } 921 922 static void 923 aw_mmc_timeout(void *arg) 924 { 925 struct aw_mmc_softc *sc; 926 927 sc = (struct aw_mmc_softc *)arg; 928 #ifdef MMCCAM 929 if (sc->ccb != NULL) { 930 #else 931 if (sc->aw_req != NULL) { 932 #endif 933 device_printf(sc->aw_dev, "controller timeout\n"); 934 set_mmc_error(sc, MMC_ERR_TIMEOUT); 935 aw_mmc_req_done(sc); 936 } else 937 device_printf(sc->aw_dev, 938 "Spurious timeout - no active request\n"); 939 } 940 941 static void 942 aw_mmc_print_error(uint32_t err) 943 { 944 if(err & AW_MMC_INT_RESP_ERR) 945 printf("AW_MMC_INT_RESP_ERR "); 946 if (err & AW_MMC_INT_RESP_CRC_ERR) 947 printf("AW_MMC_INT_RESP_CRC_ERR "); 948 if (err & AW_MMC_INT_DATA_CRC_ERR) 949 printf("AW_MMC_INT_DATA_CRC_ERR "); 950 if (err & AW_MMC_INT_RESP_TIMEOUT) 951 printf("AW_MMC_INT_RESP_TIMEOUT "); 952 if (err & AW_MMC_INT_FIFO_RUN_ERR) 953 printf("AW_MMC_INT_FIFO_RUN_ERR "); 954 if (err & AW_MMC_INT_CMD_BUSY) 955 printf("AW_MMC_INT_CMD_BUSY "); 956 if (err & AW_MMC_INT_DATA_START_ERR) 957 printf("AW_MMC_INT_DATA_START_ERR "); 958 if (err & AW_MMC_INT_DATA_END_BIT_ERR) 959 printf("AW_MMC_INT_DATA_END_BIT_ERR"); 960 printf("\n"); 961 } 962 963 static void 964 aw_mmc_intr(void *arg) 965 { 966 bus_dmasync_op_t sync_op; 967 struct aw_mmc_softc *sc; 968 struct mmc_data *data; 969 uint32_t idst, imask, rint; 970 971 sc = (struct aw_mmc_softc *)arg; 972 AW_MMC_LOCK(sc); 973 rint = AW_MMC_READ_4(sc, AW_MMC_RISR); 974 idst = AW_MMC_READ_4(sc, AW_MMC_IDST); 975 imask = AW_MMC_READ_4(sc, AW_MMC_IMKR); 976 if (idst == 0 && imask == 0 && rint == 0) { 977 AW_MMC_UNLOCK(sc); 978 return; 979 } 980 #ifdef DEBUG 981 device_printf(sc->aw_dev, "idst: %#x, imask: %#x, rint: %#x\n", 982 idst, imask, rint); 983 #endif 984 #ifdef MMCCAM 985 if (sc->ccb == NULL) { 986 #else 987 if (sc->aw_req == NULL) { 988 #endif 989 device_printf(sc->aw_dev, 990 "Spurious interrupt - no active request, rint: 0x%08X\n", 991 rint); 992 aw_mmc_print_error(rint); 993 goto end; 994 } 995 if (rint & AW_MMC_INT_ERR_BIT) { 996 if (bootverbose) 997 device_printf(sc->aw_dev, "error rint: 0x%08X\n", rint); 998 aw_mmc_print_error(rint); 999 if (rint & AW_MMC_INT_RESP_TIMEOUT) 1000 set_mmc_error(sc, MMC_ERR_TIMEOUT); 1001 else 1002 set_mmc_error(sc, MMC_ERR_FAILED); 1003 aw_mmc_req_done(sc); 1004 goto end; 1005 } 1006 if (idst & AW_MMC_IDST_ERROR) { 1007 device_printf(sc->aw_dev, "error idst: 0x%08x\n", idst); 1008 set_mmc_error(sc, MMC_ERR_FAILED); 1009 aw_mmc_req_done(sc); 1010 goto end; 1011 } 1012 1013 sc->aw_intr |= rint; 1014 #ifdef MMCCAM 1015 data = sc->ccb->mmcio.cmd.data; 1016 #else 1017 data = sc->aw_req->cmd->data; 1018 #endif 1019 if (data != NULL && (idst & AW_MMC_IDST_COMPLETE) != 0) { 1020 if (data->flags & MMC_DATA_WRITE) 1021 sync_op = BUS_DMASYNC_POSTWRITE; 1022 else 1023 sync_op = BUS_DMASYNC_POSTREAD; 1024 bus_dmamap_sync(sc->aw_dma_buf_tag, sc->aw_dma_buf_map, 1025 sync_op); 1026 bus_dmamap_sync(sc->aw_dma_tag, sc->aw_dma_map, 1027 BUS_DMASYNC_POSTWRITE); 1028 bus_dmamap_unload(sc->aw_dma_buf_tag, sc->aw_dma_buf_map); 1029 sc->aw_resid = data->len >> 2; 1030 } 1031 if ((sc->aw_intr & sc->aw_intr_wait) == sc->aw_intr_wait) 1032 aw_mmc_req_ok(sc); 1033 1034 end: 1035 AW_MMC_WRITE_4(sc, AW_MMC_IDST, idst); 1036 AW_MMC_WRITE_4(sc, AW_MMC_RISR, rint); 1037 AW_MMC_UNLOCK(sc); 1038 } 1039 1040 static int 1041 aw_mmc_request(device_t bus, device_t child, struct mmc_request *req) 1042 { 1043 int blksz; 1044 struct aw_mmc_softc *sc; 1045 struct mmc_command *cmd; 1046 uint32_t cmdreg, imask; 1047 int err; 1048 1049 sc = device_get_softc(bus); 1050 1051 AW_MMC_LOCK(sc); 1052 #ifdef MMCCAM 1053 KASSERT(req == NULL, ("req should be NULL in MMCCAM case!")); 1054 /* 1055 * For MMCCAM, sc->ccb has been NULL-checked and populated 1056 * by aw_mmc_cam_request() already. 1057 */ 1058 cmd = &sc->ccb->mmcio.cmd; 1059 #else 1060 if (sc->aw_req) { 1061 AW_MMC_UNLOCK(sc); 1062 return (EBUSY); 1063 } 1064 sc->aw_req = req; 1065 cmd = req->cmd; 1066 1067 #ifdef DEBUG 1068 if (bootverbose) 1069 device_printf(sc->aw_dev, "CMD%u arg %#x flags %#x dlen %u dflags %#x\n", 1070 cmd->opcode, cmd->arg, cmd->flags, 1071 cmd->data != NULL ? (unsigned int)cmd->data->len : 0, 1072 cmd->data != NULL ? cmd->data->flags: 0); 1073 #endif 1074 #endif 1075 cmdreg = AW_MMC_CMDR_LOAD; 1076 imask = AW_MMC_INT_ERR_BIT; 1077 sc->aw_intr_wait = 0; 1078 sc->aw_intr = 0; 1079 sc->aw_resid = 0; 1080 cmd->error = MMC_ERR_NONE; 1081 1082 if (cmd->opcode == MMC_GO_IDLE_STATE) 1083 cmdreg |= AW_MMC_CMDR_SEND_INIT_SEQ; 1084 1085 if (cmd->flags & MMC_RSP_PRESENT) 1086 cmdreg |= AW_MMC_CMDR_RESP_RCV; 1087 if (cmd->flags & MMC_RSP_136) 1088 cmdreg |= AW_MMC_CMDR_LONG_RESP; 1089 if (cmd->flags & MMC_RSP_CRC) 1090 cmdreg |= AW_MMC_CMDR_CHK_RESP_CRC; 1091 1092 if (cmd->data) { 1093 cmdreg |= AW_MMC_CMDR_DATA_TRANS | AW_MMC_CMDR_WAIT_PRE_OVER; 1094 1095 if (cmd->data->flags & MMC_DATA_MULTI) { 1096 cmdreg |= AW_MMC_CMDR_STOP_CMD_FLAG; 1097 imask |= AW_MMC_INT_AUTO_STOP_DONE; 1098 sc->aw_intr_wait |= AW_MMC_INT_AUTO_STOP_DONE; 1099 } else { 1100 sc->aw_intr_wait |= AW_MMC_INT_DATA_OVER; 1101 imask |= AW_MMC_INT_DATA_OVER; 1102 } 1103 if (cmd->data->flags & MMC_DATA_WRITE) 1104 cmdreg |= AW_MMC_CMDR_DIR_WRITE; 1105 1106 blksz = min(cmd->data->len, MMC_SECTOR_SIZE); 1107 AW_MMC_WRITE_4(sc, AW_MMC_BKSR, blksz); 1108 AW_MMC_WRITE_4(sc, AW_MMC_BYCR, cmd->data->len); 1109 } else { 1110 imask |= AW_MMC_INT_CMD_DONE; 1111 } 1112 1113 /* Enable the interrupts we are interested in */ 1114 AW_MMC_WRITE_4(sc, AW_MMC_IMKR, imask); 1115 AW_MMC_WRITE_4(sc, AW_MMC_RISR, 0xffffffff); 1116 1117 /* Enable auto stop if needed */ 1118 AW_MMC_WRITE_4(sc, AW_MMC_A12A, 1119 cmdreg & AW_MMC_CMDR_STOP_CMD_FLAG ? 0 : 0xffff); 1120 1121 /* Write the command argument */ 1122 AW_MMC_WRITE_4(sc, AW_MMC_CAGR, cmd->arg); 1123 1124 /* 1125 * If we don't have data start the request 1126 * if we do prepare the dma request and start the request 1127 */ 1128 if (cmd->data == NULL) { 1129 AW_MMC_WRITE_4(sc, AW_MMC_CMDR, cmdreg | cmd->opcode); 1130 } else { 1131 err = aw_mmc_prepare_dma(sc); 1132 if (err != 0) 1133 device_printf(sc->aw_dev, "prepare_dma failed: %d\n", err); 1134 1135 AW_MMC_WRITE_4(sc, AW_MMC_CMDR, cmdreg | cmd->opcode); 1136 } 1137 1138 callout_reset(&sc->aw_timeoutc, sc->aw_timeout * hz, 1139 aw_mmc_timeout, sc); 1140 AW_MMC_UNLOCK(sc); 1141 1142 return (0); 1143 } 1144 1145 static int 1146 aw_mmc_read_ivar(device_t bus, device_t child, int which, 1147 uintptr_t *result) 1148 { 1149 struct aw_mmc_softc *sc; 1150 1151 sc = device_get_softc(bus); 1152 switch (which) { 1153 default: 1154 return (EINVAL); 1155 case MMCBR_IVAR_BUS_MODE: 1156 *(int *)result = sc->aw_host.ios.bus_mode; 1157 break; 1158 case MMCBR_IVAR_BUS_WIDTH: 1159 *(int *)result = sc->aw_host.ios.bus_width; 1160 break; 1161 case MMCBR_IVAR_CHIP_SELECT: 1162 *(int *)result = sc->aw_host.ios.chip_select; 1163 break; 1164 case MMCBR_IVAR_CLOCK: 1165 *(int *)result = sc->aw_host.ios.clock; 1166 break; 1167 case MMCBR_IVAR_F_MIN: 1168 *(int *)result = sc->aw_host.f_min; 1169 break; 1170 case MMCBR_IVAR_F_MAX: 1171 *(int *)result = sc->aw_host.f_max; 1172 break; 1173 case MMCBR_IVAR_HOST_OCR: 1174 *(int *)result = sc->aw_host.host_ocr; 1175 break; 1176 case MMCBR_IVAR_MODE: 1177 *(int *)result = sc->aw_host.mode; 1178 break; 1179 case MMCBR_IVAR_OCR: 1180 *(int *)result = sc->aw_host.ocr; 1181 break; 1182 case MMCBR_IVAR_POWER_MODE: 1183 *(int *)result = sc->aw_host.ios.power_mode; 1184 break; 1185 case MMCBR_IVAR_VDD: 1186 *(int *)result = sc->aw_host.ios.vdd; 1187 break; 1188 case MMCBR_IVAR_VCCQ: 1189 *(int *)result = sc->aw_host.ios.vccq; 1190 break; 1191 case MMCBR_IVAR_CAPS: 1192 *(int *)result = sc->aw_host.caps; 1193 break; 1194 case MMCBR_IVAR_TIMING: 1195 *(int *)result = sc->aw_host.ios.timing; 1196 break; 1197 case MMCBR_IVAR_MAX_DATA: 1198 *(int *)result = (sc->aw_mmc_conf->dma_xferlen * 1199 AW_MMC_DMA_SEGS) / MMC_SECTOR_SIZE; 1200 break; 1201 case MMCBR_IVAR_RETUNE_REQ: 1202 *(int *)result = retune_req_none; 1203 break; 1204 } 1205 1206 return (0); 1207 } 1208 1209 static int 1210 aw_mmc_write_ivar(device_t bus, device_t child, int which, 1211 uintptr_t value) 1212 { 1213 struct aw_mmc_softc *sc; 1214 1215 sc = device_get_softc(bus); 1216 switch (which) { 1217 default: 1218 return (EINVAL); 1219 case MMCBR_IVAR_BUS_MODE: 1220 sc->aw_host.ios.bus_mode = value; 1221 break; 1222 case MMCBR_IVAR_BUS_WIDTH: 1223 sc->aw_host.ios.bus_width = value; 1224 break; 1225 case MMCBR_IVAR_CHIP_SELECT: 1226 sc->aw_host.ios.chip_select = value; 1227 break; 1228 case MMCBR_IVAR_CLOCK: 1229 sc->aw_host.ios.clock = value; 1230 break; 1231 case MMCBR_IVAR_MODE: 1232 sc->aw_host.mode = value; 1233 break; 1234 case MMCBR_IVAR_OCR: 1235 sc->aw_host.ocr = value; 1236 break; 1237 case MMCBR_IVAR_POWER_MODE: 1238 sc->aw_host.ios.power_mode = value; 1239 break; 1240 case MMCBR_IVAR_VDD: 1241 sc->aw_host.ios.vdd = value; 1242 break; 1243 case MMCBR_IVAR_VCCQ: 1244 sc->aw_host.ios.vccq = value; 1245 break; 1246 case MMCBR_IVAR_TIMING: 1247 sc->aw_host.ios.timing = value; 1248 break; 1249 /* These are read-only */ 1250 case MMCBR_IVAR_CAPS: 1251 case MMCBR_IVAR_HOST_OCR: 1252 case MMCBR_IVAR_F_MIN: 1253 case MMCBR_IVAR_F_MAX: 1254 case MMCBR_IVAR_MAX_DATA: 1255 return (EINVAL); 1256 } 1257 1258 return (0); 1259 } 1260 1261 static int 1262 aw_mmc_update_clock(struct aw_mmc_softc *sc, uint32_t clkon) 1263 { 1264 uint32_t reg; 1265 int retry; 1266 1267 reg = AW_MMC_READ_4(sc, AW_MMC_CKCR); 1268 reg &= ~(AW_MMC_CKCR_ENB | AW_MMC_CKCR_LOW_POWER | 1269 AW_MMC_CKCR_MASK_DATA0); 1270 1271 if (clkon) 1272 reg |= AW_MMC_CKCR_ENB; 1273 if (sc->aw_mmc_conf->mask_data0) 1274 reg |= AW_MMC_CKCR_MASK_DATA0; 1275 1276 AW_MMC_WRITE_4(sc, AW_MMC_CKCR, reg); 1277 1278 reg = AW_MMC_CMDR_LOAD | AW_MMC_CMDR_PRG_CLK | 1279 AW_MMC_CMDR_WAIT_PRE_OVER; 1280 AW_MMC_WRITE_4(sc, AW_MMC_CMDR, reg); 1281 retry = 0xfffff; 1282 1283 while (reg & AW_MMC_CMDR_LOAD && --retry > 0) { 1284 reg = AW_MMC_READ_4(sc, AW_MMC_CMDR); 1285 DELAY(10); 1286 } 1287 AW_MMC_WRITE_4(sc, AW_MMC_RISR, 0xffffffff); 1288 1289 if (reg & AW_MMC_CMDR_LOAD) { 1290 device_printf(sc->aw_dev, "timeout updating clock\n"); 1291 return (ETIMEDOUT); 1292 } 1293 1294 if (sc->aw_mmc_conf->mask_data0) { 1295 reg = AW_MMC_READ_4(sc, AW_MMC_CKCR); 1296 reg &= ~AW_MMC_CKCR_MASK_DATA0; 1297 AW_MMC_WRITE_4(sc, AW_MMC_CKCR, reg); 1298 } 1299 1300 return (0); 1301 } 1302 1303 static int 1304 aw_mmc_switch_vccq(device_t bus, device_t child) 1305 { 1306 struct aw_mmc_softc *sc; 1307 int uvolt, err; 1308 1309 sc = device_get_softc(bus); 1310 1311 if (sc->aw_reg_vqmmc == NULL) 1312 return EOPNOTSUPP; 1313 1314 switch (sc->aw_host.ios.vccq) { 1315 case vccq_180: 1316 uvolt = 1800000; 1317 break; 1318 case vccq_330: 1319 uvolt = 3300000; 1320 break; 1321 default: 1322 return EINVAL; 1323 } 1324 1325 err = regulator_set_voltage(sc->aw_reg_vqmmc, uvolt, uvolt); 1326 if (err != 0) { 1327 device_printf(sc->aw_dev, 1328 "Cannot set vqmmc to %d<->%d\n", 1329 uvolt, 1330 uvolt); 1331 return (err); 1332 } 1333 1334 return (0); 1335 } 1336 1337 static int 1338 aw_mmc_update_ios(device_t bus, device_t child) 1339 { 1340 int error; 1341 struct aw_mmc_softc *sc; 1342 struct mmc_ios *ios; 1343 unsigned int clock; 1344 uint32_t reg, div = 1; 1345 1346 sc = device_get_softc(bus); 1347 1348 ios = &sc->aw_host.ios; 1349 1350 /* Set the bus width. */ 1351 switch (ios->bus_width) { 1352 case bus_width_1: 1353 AW_MMC_WRITE_4(sc, AW_MMC_BWDR, AW_MMC_BWDR1); 1354 break; 1355 case bus_width_4: 1356 AW_MMC_WRITE_4(sc, AW_MMC_BWDR, AW_MMC_BWDR4); 1357 break; 1358 case bus_width_8: 1359 AW_MMC_WRITE_4(sc, AW_MMC_BWDR, AW_MMC_BWDR8); 1360 break; 1361 } 1362 1363 switch (ios->power_mode) { 1364 case power_on: 1365 break; 1366 case power_off: 1367 if (bootverbose) 1368 device_printf(sc->aw_dev, "Powering down sd/mmc\n"); 1369 1370 if (sc->aw_reg_vmmc) 1371 regulator_disable(sc->aw_reg_vmmc); 1372 if (sc->aw_reg_vqmmc) 1373 regulator_disable(sc->aw_reg_vqmmc); 1374 1375 aw_mmc_reset(sc); 1376 break; 1377 case power_up: 1378 if (bootverbose) 1379 device_printf(sc->aw_dev, "Powering up sd/mmc\n"); 1380 1381 if (sc->aw_reg_vmmc) 1382 regulator_enable(sc->aw_reg_vmmc); 1383 if (sc->aw_reg_vqmmc) 1384 regulator_enable(sc->aw_reg_vqmmc); 1385 aw_mmc_init(sc); 1386 break; 1387 }; 1388 1389 /* Enable ddr mode if needed */ 1390 reg = AW_MMC_READ_4(sc, AW_MMC_GCTL); 1391 if (ios->timing == bus_timing_uhs_ddr50 || 1392 ios->timing == bus_timing_mmc_ddr52) 1393 reg |= AW_MMC_GCTL_DDR_MOD_SEL; 1394 else 1395 reg &= ~AW_MMC_GCTL_DDR_MOD_SEL; 1396 AW_MMC_WRITE_4(sc, AW_MMC_GCTL, reg); 1397 1398 if (ios->clock && ios->clock != sc->aw_clock) { 1399 sc->aw_clock = clock = ios->clock; 1400 1401 /* Disable clock */ 1402 error = aw_mmc_update_clock(sc, 0); 1403 if (error != 0) 1404 return (error); 1405 1406 if (ios->timing == bus_timing_mmc_ddr52 && 1407 (sc->aw_mmc_conf->new_timing || 1408 ios->bus_width == bus_width_8)) { 1409 div = 2; 1410 clock <<= 1; 1411 } 1412 1413 /* Reset the divider. */ 1414 reg = AW_MMC_READ_4(sc, AW_MMC_CKCR); 1415 reg &= ~AW_MMC_CKCR_DIV; 1416 reg |= div - 1; 1417 AW_MMC_WRITE_4(sc, AW_MMC_CKCR, reg); 1418 1419 /* New timing mode if needed */ 1420 if (sc->aw_mmc_conf->new_timing) { 1421 reg = AW_MMC_READ_4(sc, AW_MMC_NTSR); 1422 reg |= AW_MMC_NTSR_MODE_SELECT; 1423 AW_MMC_WRITE_4(sc, AW_MMC_NTSR, reg); 1424 } 1425 1426 /* Set the MMC clock. */ 1427 error = clk_set_freq(sc->aw_clk_mmc, clock, 1428 CLK_SET_ROUND_DOWN); 1429 if (error != 0) { 1430 device_printf(sc->aw_dev, 1431 "failed to set frequency to %u Hz: %d\n", 1432 clock, error); 1433 return (error); 1434 } 1435 1436 if (sc->aw_mmc_conf->can_calibrate) 1437 AW_MMC_WRITE_4(sc, AW_MMC_SAMP_DL, AW_MMC_SAMP_DL_SW_EN); 1438 1439 /* Enable clock. */ 1440 error = aw_mmc_update_clock(sc, 1); 1441 if (error != 0) 1442 return (error); 1443 } 1444 1445 1446 return (0); 1447 } 1448 1449 static int 1450 aw_mmc_get_ro(device_t bus, device_t child) 1451 { 1452 1453 return (0); 1454 } 1455 1456 static int 1457 aw_mmc_acquire_host(device_t bus, device_t child) 1458 { 1459 struct aw_mmc_softc *sc; 1460 int error; 1461 1462 sc = device_get_softc(bus); 1463 AW_MMC_LOCK(sc); 1464 while (sc->aw_bus_busy) { 1465 error = msleep(sc, &sc->aw_mtx, PCATCH, "mmchw", 0); 1466 if (error != 0) { 1467 AW_MMC_UNLOCK(sc); 1468 return (error); 1469 } 1470 } 1471 sc->aw_bus_busy++; 1472 AW_MMC_UNLOCK(sc); 1473 1474 return (0); 1475 } 1476 1477 static int 1478 aw_mmc_release_host(device_t bus, device_t child) 1479 { 1480 struct aw_mmc_softc *sc; 1481 1482 sc = device_get_softc(bus); 1483 AW_MMC_LOCK(sc); 1484 sc->aw_bus_busy--; 1485 wakeup(sc); 1486 AW_MMC_UNLOCK(sc); 1487 1488 return (0); 1489 } 1490 1491 static device_method_t aw_mmc_methods[] = { 1492 /* Device interface */ 1493 DEVMETHOD(device_probe, aw_mmc_probe), 1494 DEVMETHOD(device_attach, aw_mmc_attach), 1495 DEVMETHOD(device_detach, aw_mmc_detach), 1496 1497 /* Bus interface */ 1498 DEVMETHOD(bus_read_ivar, aw_mmc_read_ivar), 1499 DEVMETHOD(bus_write_ivar, aw_mmc_write_ivar), 1500 1501 /* MMC bridge interface */ 1502 DEVMETHOD(mmcbr_update_ios, aw_mmc_update_ios), 1503 DEVMETHOD(mmcbr_request, aw_mmc_request), 1504 DEVMETHOD(mmcbr_get_ro, aw_mmc_get_ro), 1505 DEVMETHOD(mmcbr_switch_vccq, aw_mmc_switch_vccq), 1506 DEVMETHOD(mmcbr_acquire_host, aw_mmc_acquire_host), 1507 DEVMETHOD(mmcbr_release_host, aw_mmc_release_host), 1508 1509 DEVMETHOD_END 1510 }; 1511 1512 static devclass_t aw_mmc_devclass; 1513 1514 static driver_t aw_mmc_driver = { 1515 "aw_mmc", 1516 aw_mmc_methods, 1517 sizeof(struct aw_mmc_softc), 1518 }; 1519 1520 DRIVER_MODULE(aw_mmc, simplebus, aw_mmc_driver, aw_mmc_devclass, NULL, 1521 NULL); 1522 #ifndef MMCCAM 1523 MMC_DECLARE_BRIDGE(aw_mmc); 1524 #endif 1525