1 /*- 2 * Copyright (c) 2016 Jared McNeill <jmcneill@invisible.ca> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 16 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 17 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 19 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 20 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 21 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 22 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 */ 28 29 /* 30 * Allwinner Gigabit Ethernet MAC (EMAC) controller 31 */ 32 33 #include "opt_device_polling.h" 34 35 #include <sys/cdefs.h> 36 __FBSDID("$FreeBSD$"); 37 38 #include <sys/param.h> 39 #include <sys/systm.h> 40 #include <sys/bus.h> 41 #include <sys/rman.h> 42 #include <sys/kernel.h> 43 #include <sys/endian.h> 44 #include <sys/mbuf.h> 45 #include <sys/socket.h> 46 #include <sys/sockio.h> 47 #include <sys/module.h> 48 #include <sys/taskqueue.h> 49 #include <sys/gpio.h> 50 51 #include <net/bpf.h> 52 #include <net/if.h> 53 #include <net/ethernet.h> 54 #include <net/if_dl.h> 55 #include <net/if_media.h> 56 #include <net/if_types.h> 57 #include <net/if_var.h> 58 59 #include <machine/bus.h> 60 61 #include <dev/ofw/ofw_bus.h> 62 #include <dev/ofw/ofw_bus_subr.h> 63 64 #include <arm/allwinner/if_awgreg.h> 65 #include <arm/allwinner/aw_sid.h> 66 #include <dev/mii/mii.h> 67 #include <dev/mii/miivar.h> 68 69 #include <dev/extres/clk/clk.h> 70 #include <dev/extres/hwreset/hwreset.h> 71 #include <dev/extres/regulator/regulator.h> 72 #include <dev/extres/syscon/syscon.h> 73 74 #include "syscon_if.h" 75 #include "miibus_if.h" 76 #include "gpio_if.h" 77 78 #define RD4(sc, reg) bus_read_4((sc)->res[_RES_EMAC], (reg)) 79 #define WR4(sc, reg, val) bus_write_4((sc)->res[_RES_EMAC], (reg), (val)) 80 81 #define AWG_LOCK(sc) mtx_lock(&(sc)->mtx) 82 #define AWG_UNLOCK(sc) mtx_unlock(&(sc)->mtx); 83 #define AWG_ASSERT_LOCKED(sc) mtx_assert(&(sc)->mtx, MA_OWNED) 84 #define AWG_ASSERT_UNLOCKED(sc) mtx_assert(&(sc)->mtx, MA_NOTOWNED) 85 86 #define DESC_ALIGN 4 87 #define TX_DESC_COUNT 1024 88 #define TX_DESC_SIZE (sizeof(struct emac_desc) * TX_DESC_COUNT) 89 #define RX_DESC_COUNT 256 90 #define RX_DESC_SIZE (sizeof(struct emac_desc) * RX_DESC_COUNT) 91 92 #define DESC_OFF(n) ((n) * sizeof(struct emac_desc)) 93 #define TX_NEXT(n) (((n) + 1) & (TX_DESC_COUNT - 1)) 94 #define TX_SKIP(n, o) (((n) + (o)) & (TX_DESC_COUNT - 1)) 95 #define RX_NEXT(n) (((n) + 1) & (RX_DESC_COUNT - 1)) 96 97 #define TX_MAX_SEGS 20 98 99 #define SOFT_RST_RETRY 1000 100 #define MII_BUSY_RETRY 1000 101 #define MDIO_FREQ 2500000 102 103 #define BURST_LEN_DEFAULT 8 104 #define RX_TX_PRI_DEFAULT 0 105 #define PAUSE_TIME_DEFAULT 0x400 106 #define TX_INTERVAL_DEFAULT 64 107 #define RX_BATCH_DEFAULT 64 108 109 /* syscon EMAC clock register */ 110 #define EMAC_CLK_REG 0x30 111 #define EMAC_CLK_EPHY_ADDR (0x1f << 20) /* H3 */ 112 #define EMAC_CLK_EPHY_ADDR_SHIFT 20 113 #define EMAC_CLK_EPHY_LED_POL (1 << 17) /* H3 */ 114 #define EMAC_CLK_EPHY_SHUTDOWN (1 << 16) /* H3 */ 115 #define EMAC_CLK_EPHY_SELECT (1 << 15) /* H3 */ 116 #define EMAC_CLK_RMII_EN (1 << 13) 117 #define EMAC_CLK_ETXDC (0x7 << 10) 118 #define EMAC_CLK_ETXDC_SHIFT 10 119 #define EMAC_CLK_ERXDC (0x1f << 5) 120 #define EMAC_CLK_ERXDC_SHIFT 5 121 #define EMAC_CLK_PIT (0x1 << 2) 122 #define EMAC_CLK_PIT_MII (0 << 2) 123 #define EMAC_CLK_PIT_RGMII (1 << 2) 124 #define EMAC_CLK_SRC (0x3 << 0) 125 #define EMAC_CLK_SRC_MII (0 << 0) 126 #define EMAC_CLK_SRC_EXT_RGMII (1 << 0) 127 #define EMAC_CLK_SRC_RGMII (2 << 0) 128 129 /* Burst length of RX and TX DMA transfers */ 130 static int awg_burst_len = BURST_LEN_DEFAULT; 131 TUNABLE_INT("hw.awg.burst_len", &awg_burst_len); 132 133 /* RX / TX DMA priority. If 1, RX DMA has priority over TX DMA. */ 134 static int awg_rx_tx_pri = RX_TX_PRI_DEFAULT; 135 TUNABLE_INT("hw.awg.rx_tx_pri", &awg_rx_tx_pri); 136 137 /* Pause time field in the transmitted control frame */ 138 static int awg_pause_time = PAUSE_TIME_DEFAULT; 139 TUNABLE_INT("hw.awg.pause_time", &awg_pause_time); 140 141 /* Request a TX interrupt every <n> descriptors */ 142 static int awg_tx_interval = TX_INTERVAL_DEFAULT; 143 TUNABLE_INT("hw.awg.tx_interval", &awg_tx_interval); 144 145 /* Maximum number of mbufs to send to if_input */ 146 static int awg_rx_batch = RX_BATCH_DEFAULT; 147 TUNABLE_INT("hw.awg.rx_batch", &awg_rx_batch); 148 149 enum awg_type { 150 EMAC_A83T = 1, 151 EMAC_H3, 152 EMAC_A64, 153 }; 154 155 static struct ofw_compat_data compat_data[] = { 156 { "allwinner,sun8i-a83t-emac", EMAC_A83T }, 157 { "allwinner,sun8i-h3-emac", EMAC_H3 }, 158 { "allwinner,sun50i-a64-emac", EMAC_A64 }, 159 { NULL, 0 } 160 }; 161 162 struct awg_bufmap { 163 bus_dmamap_t map; 164 struct mbuf *mbuf; 165 }; 166 167 struct awg_txring { 168 bus_dma_tag_t desc_tag; 169 bus_dmamap_t desc_map; 170 struct emac_desc *desc_ring; 171 bus_addr_t desc_ring_paddr; 172 bus_dma_tag_t buf_tag; 173 struct awg_bufmap buf_map[TX_DESC_COUNT]; 174 u_int cur, next, queued; 175 u_int segs; 176 }; 177 178 struct awg_rxring { 179 bus_dma_tag_t desc_tag; 180 bus_dmamap_t desc_map; 181 struct emac_desc *desc_ring; 182 bus_addr_t desc_ring_paddr; 183 bus_dma_tag_t buf_tag; 184 struct awg_bufmap buf_map[RX_DESC_COUNT]; 185 bus_dmamap_t buf_spare_map; 186 u_int cur; 187 }; 188 189 enum { 190 _RES_EMAC, 191 _RES_IRQ, 192 _RES_SYSCON, 193 _RES_NITEMS 194 }; 195 196 struct awg_softc { 197 struct resource *res[_RES_NITEMS]; 198 struct mtx mtx; 199 if_t ifp; 200 device_t dev; 201 device_t miibus; 202 struct callout stat_ch; 203 struct task link_task; 204 void *ih; 205 u_int mdc_div_ratio_m; 206 int link; 207 int if_flags; 208 enum awg_type type; 209 struct syscon *syscon; 210 211 struct awg_txring tx; 212 struct awg_rxring rx; 213 }; 214 215 static struct resource_spec awg_spec[] = { 216 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 217 { SYS_RES_IRQ, 0, RF_ACTIVE }, 218 { SYS_RES_MEMORY, 1, RF_ACTIVE | RF_OPTIONAL }, 219 { -1, 0 } 220 }; 221 222 static void awg_txeof(struct awg_softc *sc); 223 224 static int awg_parse_delay(device_t dev, uint32_t *tx_delay, 225 uint32_t *rx_delay); 226 static uint32_t syscon_read_emac_clk_reg(device_t dev); 227 static void syscon_write_emac_clk_reg(device_t dev, uint32_t val); 228 static phandle_t awg_get_phy_node(device_t dev); 229 static bool awg_has_internal_phy(device_t dev); 230 231 static int 232 awg_miibus_readreg(device_t dev, int phy, int reg) 233 { 234 struct awg_softc *sc; 235 int retry, val; 236 237 sc = device_get_softc(dev); 238 val = 0; 239 240 WR4(sc, EMAC_MII_CMD, 241 (sc->mdc_div_ratio_m << MDC_DIV_RATIO_M_SHIFT) | 242 (phy << PHY_ADDR_SHIFT) | 243 (reg << PHY_REG_ADDR_SHIFT) | 244 MII_BUSY); 245 for (retry = MII_BUSY_RETRY; retry > 0; retry--) { 246 if ((RD4(sc, EMAC_MII_CMD) & MII_BUSY) == 0) { 247 val = RD4(sc, EMAC_MII_DATA); 248 break; 249 } 250 DELAY(10); 251 } 252 253 if (retry == 0) 254 device_printf(dev, "phy read timeout, phy=%d reg=%d\n", 255 phy, reg); 256 257 return (val); 258 } 259 260 static int 261 awg_miibus_writereg(device_t dev, int phy, int reg, int val) 262 { 263 struct awg_softc *sc; 264 int retry; 265 266 sc = device_get_softc(dev); 267 268 WR4(sc, EMAC_MII_DATA, val); 269 WR4(sc, EMAC_MII_CMD, 270 (sc->mdc_div_ratio_m << MDC_DIV_RATIO_M_SHIFT) | 271 (phy << PHY_ADDR_SHIFT) | 272 (reg << PHY_REG_ADDR_SHIFT) | 273 MII_WR | MII_BUSY); 274 for (retry = MII_BUSY_RETRY; retry > 0; retry--) { 275 if ((RD4(sc, EMAC_MII_CMD) & MII_BUSY) == 0) 276 break; 277 DELAY(10); 278 } 279 280 if (retry == 0) 281 device_printf(dev, "phy write timeout, phy=%d reg=%d\n", 282 phy, reg); 283 284 return (0); 285 } 286 287 static void 288 awg_update_link_locked(struct awg_softc *sc) 289 { 290 struct mii_data *mii; 291 uint32_t val; 292 293 AWG_ASSERT_LOCKED(sc); 294 295 if ((if_getdrvflags(sc->ifp) & IFF_DRV_RUNNING) == 0) 296 return; 297 mii = device_get_softc(sc->miibus); 298 299 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 300 (IFM_ACTIVE | IFM_AVALID)) { 301 switch (IFM_SUBTYPE(mii->mii_media_active)) { 302 case IFM_1000_T: 303 case IFM_1000_SX: 304 case IFM_100_TX: 305 case IFM_10_T: 306 sc->link = 1; 307 break; 308 default: 309 sc->link = 0; 310 break; 311 } 312 } else 313 sc->link = 0; 314 315 if (sc->link == 0) 316 return; 317 318 val = RD4(sc, EMAC_BASIC_CTL_0); 319 val &= ~(BASIC_CTL_SPEED | BASIC_CTL_DUPLEX); 320 321 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T || 322 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) 323 val |= BASIC_CTL_SPEED_1000 << BASIC_CTL_SPEED_SHIFT; 324 else if (IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) 325 val |= BASIC_CTL_SPEED_100 << BASIC_CTL_SPEED_SHIFT; 326 else 327 val |= BASIC_CTL_SPEED_10 << BASIC_CTL_SPEED_SHIFT; 328 329 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) 330 val |= BASIC_CTL_DUPLEX; 331 332 WR4(sc, EMAC_BASIC_CTL_0, val); 333 334 val = RD4(sc, EMAC_RX_CTL_0); 335 val &= ~RX_FLOW_CTL_EN; 336 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 337 val |= RX_FLOW_CTL_EN; 338 WR4(sc, EMAC_RX_CTL_0, val); 339 340 val = RD4(sc, EMAC_TX_FLOW_CTL); 341 val &= ~(PAUSE_TIME|TX_FLOW_CTL_EN); 342 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 343 val |= TX_FLOW_CTL_EN; 344 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) 345 val |= awg_pause_time << PAUSE_TIME_SHIFT; 346 WR4(sc, EMAC_TX_FLOW_CTL, val); 347 } 348 349 static void 350 awg_link_task(void *arg, int pending) 351 { 352 struct awg_softc *sc; 353 354 sc = arg; 355 356 AWG_LOCK(sc); 357 awg_update_link_locked(sc); 358 AWG_UNLOCK(sc); 359 } 360 361 static void 362 awg_miibus_statchg(device_t dev) 363 { 364 struct awg_softc *sc; 365 366 sc = device_get_softc(dev); 367 368 taskqueue_enqueue(taskqueue_swi, &sc->link_task); 369 } 370 371 static void 372 awg_media_status(if_t ifp, struct ifmediareq *ifmr) 373 { 374 struct awg_softc *sc; 375 struct mii_data *mii; 376 377 sc = if_getsoftc(ifp); 378 mii = device_get_softc(sc->miibus); 379 380 AWG_LOCK(sc); 381 mii_pollstat(mii); 382 ifmr->ifm_active = mii->mii_media_active; 383 ifmr->ifm_status = mii->mii_media_status; 384 AWG_UNLOCK(sc); 385 } 386 387 static int 388 awg_media_change(if_t ifp) 389 { 390 struct awg_softc *sc; 391 struct mii_data *mii; 392 int error; 393 394 sc = if_getsoftc(ifp); 395 mii = device_get_softc(sc->miibus); 396 397 AWG_LOCK(sc); 398 error = mii_mediachg(mii); 399 AWG_UNLOCK(sc); 400 401 return (error); 402 } 403 404 static int 405 awg_encap(struct awg_softc *sc, struct mbuf **mp) 406 { 407 bus_dmamap_t map; 408 bus_dma_segment_t segs[TX_MAX_SEGS]; 409 int error, nsegs, cur, first, last, i; 410 u_int csum_flags; 411 uint32_t flags, status; 412 struct mbuf *m; 413 414 cur = first = sc->tx.cur; 415 map = sc->tx.buf_map[first].map; 416 417 m = *mp; 418 error = bus_dmamap_load_mbuf_sg(sc->tx.buf_tag, map, m, segs, 419 &nsegs, BUS_DMA_NOWAIT); 420 if (error == EFBIG) { 421 m = m_collapse(m, M_NOWAIT, TX_MAX_SEGS); 422 if (m == NULL) { 423 device_printf(sc->dev, "awg_encap: m_collapse failed\n"); 424 m_freem(*mp); 425 *mp = NULL; 426 return (ENOMEM); 427 } 428 *mp = m; 429 error = bus_dmamap_load_mbuf_sg(sc->tx.buf_tag, map, m, 430 segs, &nsegs, BUS_DMA_NOWAIT); 431 if (error != 0) { 432 m_freem(*mp); 433 *mp = NULL; 434 } 435 } 436 if (error != 0) { 437 device_printf(sc->dev, "awg_encap: bus_dmamap_load_mbuf_sg failed\n"); 438 return (error); 439 } 440 if (nsegs == 0) { 441 m_freem(*mp); 442 *mp = NULL; 443 return (EIO); 444 } 445 446 if (sc->tx.queued + nsegs > TX_DESC_COUNT) { 447 bus_dmamap_unload(sc->tx.buf_tag, map); 448 return (ENOBUFS); 449 } 450 451 bus_dmamap_sync(sc->tx.buf_tag, map, BUS_DMASYNC_PREWRITE); 452 453 flags = TX_FIR_DESC; 454 status = 0; 455 if ((m->m_pkthdr.csum_flags & CSUM_IP) != 0) { 456 if ((m->m_pkthdr.csum_flags & (CSUM_TCP|CSUM_UDP)) != 0) 457 csum_flags = TX_CHECKSUM_CTL_FULL; 458 else 459 csum_flags = TX_CHECKSUM_CTL_IP; 460 flags |= (csum_flags << TX_CHECKSUM_CTL_SHIFT); 461 } 462 463 for (i = 0; i < nsegs; i++) { 464 sc->tx.segs++; 465 if (i == nsegs - 1) { 466 flags |= TX_LAST_DESC; 467 /* 468 * Can only request TX completion 469 * interrupt on last descriptor. 470 */ 471 if (sc->tx.segs >= awg_tx_interval) { 472 sc->tx.segs = 0; 473 flags |= TX_INT_CTL; 474 } 475 } 476 477 sc->tx.desc_ring[cur].addr = htole32((uint32_t)segs[i].ds_addr); 478 sc->tx.desc_ring[cur].size = htole32(flags | segs[i].ds_len); 479 sc->tx.desc_ring[cur].status = htole32(status); 480 481 flags &= ~TX_FIR_DESC; 482 /* 483 * Setting of the valid bit in the first descriptor is 484 * deferred until the whole chain is fully set up. 485 */ 486 status = TX_DESC_CTL; 487 488 ++sc->tx.queued; 489 cur = TX_NEXT(cur); 490 } 491 492 sc->tx.cur = cur; 493 494 /* Store mapping and mbuf in the last segment */ 495 last = TX_SKIP(cur, TX_DESC_COUNT - 1); 496 sc->tx.buf_map[first].map = sc->tx.buf_map[last].map; 497 sc->tx.buf_map[last].map = map; 498 sc->tx.buf_map[last].mbuf = m; 499 500 /* 501 * The whole mbuf chain has been DMA mapped, 502 * fix the first descriptor. 503 */ 504 sc->tx.desc_ring[first].status = htole32(TX_DESC_CTL); 505 506 return (0); 507 } 508 509 static void 510 awg_clean_txbuf(struct awg_softc *sc, int index) 511 { 512 struct awg_bufmap *bmap; 513 514 --sc->tx.queued; 515 516 bmap = &sc->tx.buf_map[index]; 517 if (bmap->mbuf != NULL) { 518 bus_dmamap_sync(sc->tx.buf_tag, bmap->map, 519 BUS_DMASYNC_POSTWRITE); 520 bus_dmamap_unload(sc->tx.buf_tag, bmap->map); 521 m_freem(bmap->mbuf); 522 bmap->mbuf = NULL; 523 } 524 } 525 526 static void 527 awg_setup_rxdesc(struct awg_softc *sc, int index, bus_addr_t paddr) 528 { 529 uint32_t status, size; 530 531 status = RX_DESC_CTL; 532 size = MCLBYTES - 1; 533 534 sc->rx.desc_ring[index].addr = htole32((uint32_t)paddr); 535 sc->rx.desc_ring[index].size = htole32(size); 536 sc->rx.desc_ring[index].status = htole32(status); 537 } 538 539 static void 540 awg_reuse_rxdesc(struct awg_softc *sc, int index) 541 { 542 543 sc->rx.desc_ring[index].status = htole32(RX_DESC_CTL); 544 } 545 546 static int 547 awg_newbuf_rx(struct awg_softc *sc, int index) 548 { 549 struct mbuf *m; 550 bus_dma_segment_t seg; 551 bus_dmamap_t map; 552 int nsegs; 553 554 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 555 if (m == NULL) 556 return (ENOBUFS); 557 558 m->m_pkthdr.len = m->m_len = m->m_ext.ext_size; 559 m_adj(m, ETHER_ALIGN); 560 561 if (bus_dmamap_load_mbuf_sg(sc->rx.buf_tag, sc->rx.buf_spare_map, 562 m, &seg, &nsegs, BUS_DMA_NOWAIT) != 0) { 563 m_freem(m); 564 return (ENOBUFS); 565 } 566 567 if (sc->rx.buf_map[index].mbuf != NULL) { 568 bus_dmamap_sync(sc->rx.buf_tag, sc->rx.buf_map[index].map, 569 BUS_DMASYNC_POSTREAD); 570 bus_dmamap_unload(sc->rx.buf_tag, sc->rx.buf_map[index].map); 571 } 572 map = sc->rx.buf_map[index].map; 573 sc->rx.buf_map[index].map = sc->rx.buf_spare_map; 574 sc->rx.buf_spare_map = map; 575 bus_dmamap_sync(sc->rx.buf_tag, sc->rx.buf_map[index].map, 576 BUS_DMASYNC_PREREAD); 577 578 sc->rx.buf_map[index].mbuf = m; 579 awg_setup_rxdesc(sc, index, seg.ds_addr); 580 581 return (0); 582 } 583 584 static void 585 awg_start_locked(struct awg_softc *sc) 586 { 587 struct mbuf *m; 588 uint32_t val; 589 if_t ifp; 590 int cnt, err; 591 592 AWG_ASSERT_LOCKED(sc); 593 594 if (!sc->link) 595 return; 596 597 ifp = sc->ifp; 598 599 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING|IFF_DRV_OACTIVE)) != 600 IFF_DRV_RUNNING) 601 return; 602 603 for (cnt = 0; ; cnt++) { 604 m = if_dequeue(ifp); 605 if (m == NULL) 606 break; 607 608 err = awg_encap(sc, &m); 609 if (err != 0) { 610 if (err == ENOBUFS) 611 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0); 612 if (m != NULL) 613 if_sendq_prepend(ifp, m); 614 break; 615 } 616 if_bpfmtap(ifp, m); 617 } 618 619 if (cnt != 0) { 620 bus_dmamap_sync(sc->tx.desc_tag, sc->tx.desc_map, 621 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 622 623 /* Start and run TX DMA */ 624 val = RD4(sc, EMAC_TX_CTL_1); 625 WR4(sc, EMAC_TX_CTL_1, val | TX_DMA_START); 626 } 627 } 628 629 static void 630 awg_start(if_t ifp) 631 { 632 struct awg_softc *sc; 633 634 sc = if_getsoftc(ifp); 635 636 AWG_LOCK(sc); 637 awg_start_locked(sc); 638 AWG_UNLOCK(sc); 639 } 640 641 static void 642 awg_tick(void *softc) 643 { 644 struct awg_softc *sc; 645 struct mii_data *mii; 646 if_t ifp; 647 int link; 648 649 sc = softc; 650 ifp = sc->ifp; 651 mii = device_get_softc(sc->miibus); 652 653 AWG_ASSERT_LOCKED(sc); 654 655 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) 656 return; 657 658 link = sc->link; 659 mii_tick(mii); 660 if (sc->link && !link) 661 awg_start_locked(sc); 662 663 callout_reset(&sc->stat_ch, hz, awg_tick, sc); 664 } 665 666 /* Bit Reversal - http://aggregate.org/MAGIC/#Bit%20Reversal */ 667 static uint32_t 668 bitrev32(uint32_t x) 669 { 670 x = (((x & 0xaaaaaaaa) >> 1) | ((x & 0x55555555) << 1)); 671 x = (((x & 0xcccccccc) >> 2) | ((x & 0x33333333) << 2)); 672 x = (((x & 0xf0f0f0f0) >> 4) | ((x & 0x0f0f0f0f) << 4)); 673 x = (((x & 0xff00ff00) >> 8) | ((x & 0x00ff00ff) << 8)); 674 675 return (x >> 16) | (x << 16); 676 } 677 678 static void 679 awg_setup_rxfilter(struct awg_softc *sc) 680 { 681 uint32_t val, crc, hashreg, hashbit, hash[2], machi, maclo; 682 int mc_count, mcnt, i; 683 uint8_t *eaddr, *mta; 684 if_t ifp; 685 686 AWG_ASSERT_LOCKED(sc); 687 688 ifp = sc->ifp; 689 val = 0; 690 hash[0] = hash[1] = 0; 691 692 mc_count = if_multiaddr_count(ifp, -1); 693 694 if (if_getflags(ifp) & IFF_PROMISC) 695 val |= DIS_ADDR_FILTER; 696 else if (if_getflags(ifp) & IFF_ALLMULTI) { 697 val |= RX_ALL_MULTICAST; 698 hash[0] = hash[1] = ~0; 699 } else if (mc_count > 0) { 700 val |= HASH_MULTICAST; 701 702 mta = malloc(sizeof(unsigned char) * ETHER_ADDR_LEN * mc_count, 703 M_DEVBUF, M_NOWAIT); 704 if (mta == NULL) { 705 if_printf(ifp, 706 "failed to allocate temporary multicast list\n"); 707 return; 708 } 709 710 if_multiaddr_array(ifp, mta, &mcnt, mc_count); 711 for (i = 0; i < mcnt; i++) { 712 crc = ether_crc32_le(mta + (i * ETHER_ADDR_LEN), 713 ETHER_ADDR_LEN) & 0x7f; 714 crc = bitrev32(~crc) >> 26; 715 hashreg = (crc >> 5); 716 hashbit = (crc & 0x1f); 717 hash[hashreg] |= (1 << hashbit); 718 } 719 720 free(mta, M_DEVBUF); 721 } 722 723 /* Write our unicast address */ 724 eaddr = IF_LLADDR(ifp); 725 machi = (eaddr[5] << 8) | eaddr[4]; 726 maclo = (eaddr[3] << 24) | (eaddr[2] << 16) | (eaddr[1] << 8) | 727 (eaddr[0] << 0); 728 WR4(sc, EMAC_ADDR_HIGH(0), machi); 729 WR4(sc, EMAC_ADDR_LOW(0), maclo); 730 731 /* Multicast hash filters */ 732 WR4(sc, EMAC_RX_HASH_0, hash[1]); 733 WR4(sc, EMAC_RX_HASH_1, hash[0]); 734 735 /* RX frame filter config */ 736 WR4(sc, EMAC_RX_FRM_FLT, val); 737 } 738 739 static void 740 awg_enable_intr(struct awg_softc *sc) 741 { 742 /* Enable interrupts */ 743 WR4(sc, EMAC_INT_EN, RX_INT_EN | TX_INT_EN | TX_BUF_UA_INT_EN); 744 } 745 746 static void 747 awg_disable_intr(struct awg_softc *sc) 748 { 749 /* Disable interrupts */ 750 WR4(sc, EMAC_INT_EN, 0); 751 } 752 753 static void 754 awg_init_locked(struct awg_softc *sc) 755 { 756 struct mii_data *mii; 757 uint32_t val; 758 if_t ifp; 759 760 mii = device_get_softc(sc->miibus); 761 ifp = sc->ifp; 762 763 AWG_ASSERT_LOCKED(sc); 764 765 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) 766 return; 767 768 awg_setup_rxfilter(sc); 769 770 /* Configure DMA burst length and priorities */ 771 val = awg_burst_len << BASIC_CTL_BURST_LEN_SHIFT; 772 if (awg_rx_tx_pri) 773 val |= BASIC_CTL_RX_TX_PRI; 774 WR4(sc, EMAC_BASIC_CTL_1, val); 775 776 /* Enable interrupts */ 777 #ifdef DEVICE_POLLING 778 if ((if_getcapenable(ifp) & IFCAP_POLLING) == 0) 779 awg_enable_intr(sc); 780 else 781 awg_disable_intr(sc); 782 #else 783 awg_enable_intr(sc); 784 #endif 785 786 /* Enable transmit DMA */ 787 val = RD4(sc, EMAC_TX_CTL_1); 788 WR4(sc, EMAC_TX_CTL_1, val | TX_DMA_EN | TX_MD | TX_NEXT_FRAME); 789 790 /* Enable receive DMA */ 791 val = RD4(sc, EMAC_RX_CTL_1); 792 WR4(sc, EMAC_RX_CTL_1, val | RX_DMA_EN | RX_MD); 793 794 /* Enable transmitter */ 795 val = RD4(sc, EMAC_TX_CTL_0); 796 WR4(sc, EMAC_TX_CTL_0, val | TX_EN); 797 798 /* Enable receiver */ 799 val = RD4(sc, EMAC_RX_CTL_0); 800 WR4(sc, EMAC_RX_CTL_0, val | RX_EN | CHECK_CRC); 801 802 if_setdrvflagbits(ifp, IFF_DRV_RUNNING, IFF_DRV_OACTIVE); 803 804 mii_mediachg(mii); 805 callout_reset(&sc->stat_ch, hz, awg_tick, sc); 806 } 807 808 static void 809 awg_init(void *softc) 810 { 811 struct awg_softc *sc; 812 813 sc = softc; 814 815 AWG_LOCK(sc); 816 awg_init_locked(sc); 817 AWG_UNLOCK(sc); 818 } 819 820 static void 821 awg_stop(struct awg_softc *sc) 822 { 823 if_t ifp; 824 uint32_t val; 825 int i; 826 827 AWG_ASSERT_LOCKED(sc); 828 829 ifp = sc->ifp; 830 831 callout_stop(&sc->stat_ch); 832 833 /* Stop transmit DMA and flush data in the TX FIFO */ 834 val = RD4(sc, EMAC_TX_CTL_1); 835 val &= ~TX_DMA_EN; 836 val |= FLUSH_TX_FIFO; 837 WR4(sc, EMAC_TX_CTL_1, val); 838 839 /* Disable transmitter */ 840 val = RD4(sc, EMAC_TX_CTL_0); 841 WR4(sc, EMAC_TX_CTL_0, val & ~TX_EN); 842 843 /* Disable receiver */ 844 val = RD4(sc, EMAC_RX_CTL_0); 845 WR4(sc, EMAC_RX_CTL_0, val & ~RX_EN); 846 847 /* Disable interrupts */ 848 awg_disable_intr(sc); 849 850 /* Disable transmit DMA */ 851 val = RD4(sc, EMAC_TX_CTL_1); 852 WR4(sc, EMAC_TX_CTL_1, val & ~TX_DMA_EN); 853 854 /* Disable receive DMA */ 855 val = RD4(sc, EMAC_RX_CTL_1); 856 WR4(sc, EMAC_RX_CTL_1, val & ~RX_DMA_EN); 857 858 sc->link = 0; 859 860 /* Finish handling transmitted buffers */ 861 awg_txeof(sc); 862 863 /* Release any untransmitted buffers. */ 864 for (i = sc->tx.next; sc->tx.queued > 0; i = TX_NEXT(i)) { 865 val = le32toh(sc->tx.desc_ring[i].status); 866 if ((val & TX_DESC_CTL) != 0) 867 break; 868 awg_clean_txbuf(sc, i); 869 } 870 sc->tx.next = i; 871 for (; sc->tx.queued > 0; i = TX_NEXT(i)) { 872 sc->tx.desc_ring[i].status = 0; 873 awg_clean_txbuf(sc, i); 874 } 875 sc->tx.cur = sc->tx.next; 876 bus_dmamap_sync(sc->tx.desc_tag, sc->tx.desc_map, 877 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 878 879 /* Setup RX buffers for reuse */ 880 bus_dmamap_sync(sc->rx.desc_tag, sc->rx.desc_map, 881 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 882 883 for (i = sc->rx.cur; ; i = RX_NEXT(i)) { 884 val = le32toh(sc->rx.desc_ring[i].status); 885 if ((val & RX_DESC_CTL) != 0) 886 break; 887 awg_reuse_rxdesc(sc, i); 888 } 889 sc->rx.cur = i; 890 bus_dmamap_sync(sc->rx.desc_tag, sc->rx.desc_map, 891 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 892 893 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 894 } 895 896 static int 897 awg_rxintr(struct awg_softc *sc) 898 { 899 if_t ifp; 900 struct mbuf *m, *mh, *mt; 901 int error, index, len, cnt, npkt; 902 uint32_t status; 903 904 ifp = sc->ifp; 905 mh = mt = NULL; 906 cnt = 0; 907 npkt = 0; 908 909 bus_dmamap_sync(sc->rx.desc_tag, sc->rx.desc_map, 910 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 911 912 for (index = sc->rx.cur; ; index = RX_NEXT(index)) { 913 status = le32toh(sc->rx.desc_ring[index].status); 914 if ((status & RX_DESC_CTL) != 0) 915 break; 916 917 len = (status & RX_FRM_LEN) >> RX_FRM_LEN_SHIFT; 918 919 if (len == 0) { 920 if ((status & (RX_NO_ENOUGH_BUF_ERR | RX_OVERFLOW_ERR)) != 0) 921 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 922 awg_reuse_rxdesc(sc, index); 923 continue; 924 } 925 926 m = sc->rx.buf_map[index].mbuf; 927 928 error = awg_newbuf_rx(sc, index); 929 if (error != 0) { 930 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 931 awg_reuse_rxdesc(sc, index); 932 continue; 933 } 934 935 m->m_pkthdr.rcvif = ifp; 936 m->m_pkthdr.len = len; 937 m->m_len = len; 938 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); 939 940 if ((if_getcapenable(ifp) & IFCAP_RXCSUM) != 0 && 941 (status & RX_FRM_TYPE) != 0) { 942 m->m_pkthdr.csum_flags = CSUM_IP_CHECKED; 943 if ((status & RX_HEADER_ERR) == 0) 944 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 945 if ((status & RX_PAYLOAD_ERR) == 0) { 946 m->m_pkthdr.csum_flags |= 947 CSUM_DATA_VALID | CSUM_PSEUDO_HDR; 948 m->m_pkthdr.csum_data = 0xffff; 949 } 950 } 951 952 m->m_nextpkt = NULL; 953 if (mh == NULL) 954 mh = m; 955 else 956 mt->m_nextpkt = m; 957 mt = m; 958 ++cnt; 959 ++npkt; 960 961 if (cnt == awg_rx_batch) { 962 AWG_UNLOCK(sc); 963 if_input(ifp, mh); 964 AWG_LOCK(sc); 965 mh = mt = NULL; 966 cnt = 0; 967 } 968 } 969 970 if (index != sc->rx.cur) { 971 bus_dmamap_sync(sc->rx.desc_tag, sc->rx.desc_map, 972 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 973 } 974 975 if (mh != NULL) { 976 AWG_UNLOCK(sc); 977 if_input(ifp, mh); 978 AWG_LOCK(sc); 979 } 980 981 sc->rx.cur = index; 982 983 return (npkt); 984 } 985 986 static void 987 awg_txeof(struct awg_softc *sc) 988 { 989 struct emac_desc *desc; 990 uint32_t status, size; 991 if_t ifp; 992 int i, prog; 993 994 AWG_ASSERT_LOCKED(sc); 995 996 bus_dmamap_sync(sc->tx.desc_tag, sc->tx.desc_map, 997 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 998 999 ifp = sc->ifp; 1000 1001 prog = 0; 1002 for (i = sc->tx.next; sc->tx.queued > 0; i = TX_NEXT(i)) { 1003 desc = &sc->tx.desc_ring[i]; 1004 status = le32toh(desc->status); 1005 if ((status & TX_DESC_CTL) != 0) 1006 break; 1007 size = le32toh(desc->size); 1008 if (size & TX_LAST_DESC) { 1009 if ((status & (TX_HEADER_ERR | TX_PAYLOAD_ERR)) != 0) 1010 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 1011 else 1012 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); 1013 } 1014 prog++; 1015 awg_clean_txbuf(sc, i); 1016 } 1017 1018 if (prog > 0) { 1019 sc->tx.next = i; 1020 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 1021 } 1022 } 1023 1024 static void 1025 awg_intr(void *arg) 1026 { 1027 struct awg_softc *sc; 1028 uint32_t val; 1029 1030 sc = arg; 1031 1032 AWG_LOCK(sc); 1033 val = RD4(sc, EMAC_INT_STA); 1034 WR4(sc, EMAC_INT_STA, val); 1035 1036 if (val & RX_INT) 1037 awg_rxintr(sc); 1038 1039 if (val & TX_INT) 1040 awg_txeof(sc); 1041 1042 if (val & (TX_INT | TX_BUF_UA_INT)) { 1043 if (!if_sendq_empty(sc->ifp)) 1044 awg_start_locked(sc); 1045 } 1046 1047 AWG_UNLOCK(sc); 1048 } 1049 1050 #ifdef DEVICE_POLLING 1051 static int 1052 awg_poll(if_t ifp, enum poll_cmd cmd, int count) 1053 { 1054 struct awg_softc *sc; 1055 uint32_t val; 1056 int rx_npkts; 1057 1058 sc = if_getsoftc(ifp); 1059 rx_npkts = 0; 1060 1061 AWG_LOCK(sc); 1062 1063 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) { 1064 AWG_UNLOCK(sc); 1065 return (0); 1066 } 1067 1068 rx_npkts = awg_rxintr(sc); 1069 awg_txeof(sc); 1070 if (!if_sendq_empty(ifp)) 1071 awg_start_locked(sc); 1072 1073 if (cmd == POLL_AND_CHECK_STATUS) { 1074 val = RD4(sc, EMAC_INT_STA); 1075 if (val != 0) 1076 WR4(sc, EMAC_INT_STA, val); 1077 } 1078 1079 AWG_UNLOCK(sc); 1080 1081 return (rx_npkts); 1082 } 1083 #endif 1084 1085 static int 1086 awg_ioctl(if_t ifp, u_long cmd, caddr_t data) 1087 { 1088 struct awg_softc *sc; 1089 struct mii_data *mii; 1090 struct ifreq *ifr; 1091 int flags, mask, error; 1092 1093 sc = if_getsoftc(ifp); 1094 mii = device_get_softc(sc->miibus); 1095 ifr = (struct ifreq *)data; 1096 error = 0; 1097 1098 switch (cmd) { 1099 case SIOCSIFFLAGS: 1100 AWG_LOCK(sc); 1101 if (if_getflags(ifp) & IFF_UP) { 1102 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 1103 flags = if_getflags(ifp) ^ sc->if_flags; 1104 if ((flags & (IFF_PROMISC|IFF_ALLMULTI)) != 0) 1105 awg_setup_rxfilter(sc); 1106 } else 1107 awg_init_locked(sc); 1108 } else { 1109 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) 1110 awg_stop(sc); 1111 } 1112 sc->if_flags = if_getflags(ifp); 1113 AWG_UNLOCK(sc); 1114 break; 1115 case SIOCADDMULTI: 1116 case SIOCDELMULTI: 1117 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 1118 AWG_LOCK(sc); 1119 awg_setup_rxfilter(sc); 1120 AWG_UNLOCK(sc); 1121 } 1122 break; 1123 case SIOCSIFMEDIA: 1124 case SIOCGIFMEDIA: 1125 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 1126 break; 1127 case SIOCSIFCAP: 1128 mask = ifr->ifr_reqcap ^ if_getcapenable(ifp); 1129 #ifdef DEVICE_POLLING 1130 if (mask & IFCAP_POLLING) { 1131 if ((ifr->ifr_reqcap & IFCAP_POLLING) != 0) { 1132 error = ether_poll_register(awg_poll, ifp); 1133 if (error != 0) 1134 break; 1135 AWG_LOCK(sc); 1136 awg_disable_intr(sc); 1137 if_setcapenablebit(ifp, IFCAP_POLLING, 0); 1138 AWG_UNLOCK(sc); 1139 } else { 1140 error = ether_poll_deregister(ifp); 1141 AWG_LOCK(sc); 1142 awg_enable_intr(sc); 1143 if_setcapenablebit(ifp, 0, IFCAP_POLLING); 1144 AWG_UNLOCK(sc); 1145 } 1146 } 1147 #endif 1148 if (mask & IFCAP_VLAN_MTU) 1149 if_togglecapenable(ifp, IFCAP_VLAN_MTU); 1150 if (mask & IFCAP_RXCSUM) 1151 if_togglecapenable(ifp, IFCAP_RXCSUM); 1152 if (mask & IFCAP_TXCSUM) 1153 if_togglecapenable(ifp, IFCAP_TXCSUM); 1154 if ((if_getcapenable(ifp) & IFCAP_TXCSUM) != 0) 1155 if_sethwassistbits(ifp, CSUM_IP | CSUM_UDP | CSUM_TCP, 0); 1156 else 1157 if_sethwassistbits(ifp, 0, CSUM_IP | CSUM_UDP | CSUM_TCP); 1158 break; 1159 default: 1160 error = ether_ioctl(ifp, cmd, data); 1161 break; 1162 } 1163 1164 return (error); 1165 } 1166 1167 static uint32_t 1168 syscon_read_emac_clk_reg(device_t dev) 1169 { 1170 struct awg_softc *sc; 1171 1172 sc = device_get_softc(dev); 1173 if (sc->syscon != NULL) 1174 return (SYSCON_READ_4(sc->syscon, EMAC_CLK_REG)); 1175 else if (sc->res[_RES_SYSCON] != NULL) 1176 return (bus_read_4(sc->res[_RES_SYSCON], 0)); 1177 1178 return (0); 1179 } 1180 1181 static void 1182 syscon_write_emac_clk_reg(device_t dev, uint32_t val) 1183 { 1184 struct awg_softc *sc; 1185 1186 sc = device_get_softc(dev); 1187 if (sc->syscon != NULL) 1188 SYSCON_WRITE_4(sc->syscon, EMAC_CLK_REG, val); 1189 else if (sc->res[_RES_SYSCON] != NULL) 1190 bus_write_4(sc->res[_RES_SYSCON], 0, val); 1191 } 1192 1193 static phandle_t 1194 awg_get_phy_node(device_t dev) 1195 { 1196 phandle_t node; 1197 pcell_t phy_handle; 1198 1199 node = ofw_bus_get_node(dev); 1200 if (OF_getencprop(node, "phy-handle", (void *)&phy_handle, 1201 sizeof(phy_handle)) <= 0) 1202 return (0); 1203 1204 return (OF_node_from_xref(phy_handle)); 1205 } 1206 1207 static bool 1208 awg_has_internal_phy(device_t dev) 1209 { 1210 phandle_t node, phy_node; 1211 1212 node = ofw_bus_get_node(dev); 1213 /* Legacy binding */ 1214 if (OF_hasprop(node, "allwinner,use-internal-phy")) 1215 return (true); 1216 1217 phy_node = awg_get_phy_node(dev); 1218 return (phy_node != 0 && ofw_bus_node_is_compatible(OF_parent(phy_node), 1219 "allwinner,sun8i-h3-mdio-internal") != 0); 1220 } 1221 1222 static int 1223 awg_parse_delay(device_t dev, uint32_t *tx_delay, uint32_t *rx_delay) 1224 { 1225 phandle_t node; 1226 uint32_t delay; 1227 1228 if (tx_delay == NULL || rx_delay == NULL) 1229 return (EINVAL); 1230 *tx_delay = *rx_delay = 0; 1231 node = ofw_bus_get_node(dev); 1232 1233 if (OF_getencprop(node, "tx-delay", &delay, sizeof(delay)) >= 0) 1234 *tx_delay = delay; 1235 else if (OF_getencprop(node, "allwinner,tx-delay-ps", &delay, 1236 sizeof(delay)) >= 0) { 1237 if ((delay % 100) != 0) { 1238 device_printf(dev, "tx-delay-ps is not a multiple of 100\n"); 1239 return (EDOM); 1240 } 1241 *tx_delay = delay / 100; 1242 } 1243 if (*tx_delay > 7) { 1244 device_printf(dev, "tx-delay out of range\n"); 1245 return (ERANGE); 1246 } 1247 1248 if (OF_getencprop(node, "rx-delay", &delay, sizeof(delay)) >= 0) 1249 *rx_delay = delay; 1250 else if (OF_getencprop(node, "allwinner,rx-delay-ps", &delay, 1251 sizeof(delay)) >= 0) { 1252 if ((delay % 100) != 0) { 1253 device_printf(dev, "rx-delay-ps is not within documented domain\n"); 1254 return (EDOM); 1255 } 1256 *rx_delay = delay / 100; 1257 } 1258 if (*rx_delay > 31) { 1259 device_printf(dev, "rx-delay out of range\n"); 1260 return (ERANGE); 1261 } 1262 1263 return (0); 1264 } 1265 1266 static int 1267 awg_setup_phy(device_t dev) 1268 { 1269 struct awg_softc *sc; 1270 clk_t clk_tx, clk_tx_parent; 1271 const char *tx_parent_name; 1272 char *phy_type; 1273 phandle_t node; 1274 uint32_t reg, tx_delay, rx_delay; 1275 int error; 1276 bool use_syscon; 1277 1278 sc = device_get_softc(dev); 1279 node = ofw_bus_get_node(dev); 1280 use_syscon = false; 1281 1282 if (OF_getprop_alloc(node, "phy-mode", (void **)&phy_type) == 0) 1283 return (0); 1284 1285 if (sc->syscon != NULL || sc->res[_RES_SYSCON] != NULL) 1286 use_syscon = true; 1287 1288 if (bootverbose) 1289 device_printf(dev, "PHY type: %s, conf mode: %s\n", phy_type, 1290 use_syscon ? "reg" : "clk"); 1291 1292 if (use_syscon) { 1293 /* 1294 * Abstract away writing to syscon for devices like the pine64. 1295 * For the pine64, we get dtb from U-Boot and it still uses the 1296 * legacy setup of specifying syscon register in emac node 1297 * rather than as its own node and using an xref in emac. 1298 * These abstractions can go away once U-Boot dts is up-to-date. 1299 */ 1300 reg = syscon_read_emac_clk_reg(dev); 1301 reg &= ~(EMAC_CLK_PIT | EMAC_CLK_SRC | EMAC_CLK_RMII_EN); 1302 if (strncmp(phy_type, "rgmii", 5) == 0) 1303 reg |= EMAC_CLK_PIT_RGMII | EMAC_CLK_SRC_RGMII; 1304 else if (strcmp(phy_type, "rmii") == 0) 1305 reg |= EMAC_CLK_RMII_EN; 1306 else 1307 reg |= EMAC_CLK_PIT_MII | EMAC_CLK_SRC_MII; 1308 1309 /* 1310 * Fail attach if we fail to parse either of the delay 1311 * parameters. If we don't have the proper delay to write to 1312 * syscon, then awg likely won't function properly anyways. 1313 * Lack of delay is not an error! 1314 */ 1315 error = awg_parse_delay(dev, &tx_delay, &rx_delay); 1316 if (error != 0) 1317 goto fail; 1318 1319 /* Default to 0 and we'll increase it if we need to. */ 1320 reg &= ~(EMAC_CLK_ETXDC | EMAC_CLK_ERXDC); 1321 if (tx_delay > 0) 1322 reg |= (tx_delay << EMAC_CLK_ETXDC_SHIFT); 1323 if (rx_delay > 0) 1324 reg |= (rx_delay << EMAC_CLK_ERXDC_SHIFT); 1325 1326 if (sc->type == EMAC_H3) { 1327 if (awg_has_internal_phy(dev)) { 1328 reg |= EMAC_CLK_EPHY_SELECT; 1329 reg &= ~EMAC_CLK_EPHY_SHUTDOWN; 1330 if (OF_hasprop(node, 1331 "allwinner,leds-active-low")) 1332 reg |= EMAC_CLK_EPHY_LED_POL; 1333 else 1334 reg &= ~EMAC_CLK_EPHY_LED_POL; 1335 1336 /* Set internal PHY addr to 1 */ 1337 reg &= ~EMAC_CLK_EPHY_ADDR; 1338 reg |= (1 << EMAC_CLK_EPHY_ADDR_SHIFT); 1339 } else { 1340 reg &= ~EMAC_CLK_EPHY_SELECT; 1341 } 1342 } 1343 1344 if (bootverbose) 1345 device_printf(dev, "EMAC clock: 0x%08x\n", reg); 1346 syscon_write_emac_clk_reg(dev, reg); 1347 } else { 1348 if (strncmp(phy_type, "rgmii", 5) == 0) 1349 tx_parent_name = "emac_int_tx"; 1350 else 1351 tx_parent_name = "mii_phy_tx"; 1352 1353 /* Get the TX clock */ 1354 error = clk_get_by_ofw_name(dev, 0, "tx", &clk_tx); 1355 if (error != 0) { 1356 device_printf(dev, "cannot get tx clock\n"); 1357 goto fail; 1358 } 1359 1360 /* Find the desired parent clock based on phy-mode property */ 1361 error = clk_get_by_name(dev, tx_parent_name, &clk_tx_parent); 1362 if (error != 0) { 1363 device_printf(dev, "cannot get clock '%s'\n", 1364 tx_parent_name); 1365 goto fail; 1366 } 1367 1368 /* Set TX clock parent */ 1369 error = clk_set_parent_by_clk(clk_tx, clk_tx_parent); 1370 if (error != 0) { 1371 device_printf(dev, "cannot set tx clock parent\n"); 1372 goto fail; 1373 } 1374 1375 /* Enable TX clock */ 1376 error = clk_enable(clk_tx); 1377 if (error != 0) { 1378 device_printf(dev, "cannot enable tx clock\n"); 1379 goto fail; 1380 } 1381 } 1382 1383 error = 0; 1384 1385 fail: 1386 OF_prop_free(phy_type); 1387 return (error); 1388 } 1389 1390 static int 1391 awg_setup_extres(device_t dev) 1392 { 1393 struct awg_softc *sc; 1394 phandle_t node, phy_node; 1395 hwreset_t rst_ahb, rst_ephy; 1396 clk_t clk_ahb, clk_ephy; 1397 regulator_t reg; 1398 uint64_t freq; 1399 int error, div; 1400 1401 sc = device_get_softc(dev); 1402 rst_ahb = rst_ephy = NULL; 1403 clk_ahb = clk_ephy = NULL; 1404 reg = NULL; 1405 node = ofw_bus_get_node(dev); 1406 phy_node = awg_get_phy_node(dev); 1407 1408 if (phy_node == 0 && OF_hasprop(node, "phy-handle")) { 1409 error = ENXIO; 1410 device_printf(dev, "cannot get phy handle\n"); 1411 goto fail; 1412 } 1413 1414 /* Get AHB clock and reset resources */ 1415 error = hwreset_get_by_ofw_name(dev, 0, "stmmaceth", &rst_ahb); 1416 if (error != 0) 1417 error = hwreset_get_by_ofw_name(dev, 0, "ahb", &rst_ahb); 1418 if (error != 0) { 1419 device_printf(dev, "cannot get ahb reset\n"); 1420 goto fail; 1421 } 1422 if (hwreset_get_by_ofw_name(dev, 0, "ephy", &rst_ephy) != 0) 1423 if (phy_node == 0 || hwreset_get_by_ofw_idx(dev, phy_node, 0, 1424 &rst_ephy) != 0) 1425 rst_ephy = NULL; 1426 error = clk_get_by_ofw_name(dev, 0, "stmmaceth", &clk_ahb); 1427 if (error != 0) 1428 error = clk_get_by_ofw_name(dev, 0, "ahb", &clk_ahb); 1429 if (error != 0) { 1430 device_printf(dev, "cannot get ahb clock\n"); 1431 goto fail; 1432 } 1433 if (clk_get_by_ofw_name(dev, 0, "ephy", &clk_ephy) != 0) 1434 if (phy_node == 0 || clk_get_by_ofw_index(dev, phy_node, 0, 1435 &clk_ephy) != 0) 1436 clk_ephy = NULL; 1437 1438 if (OF_hasprop(node, "syscon") && syscon_get_by_ofw_property(dev, node, 1439 "syscon", &sc->syscon) != 0) { 1440 device_printf(dev, "cannot get syscon driver handle\n"); 1441 goto fail; 1442 } 1443 1444 /* Configure PHY for MII or RGMII mode */ 1445 if (awg_setup_phy(dev) != 0) 1446 goto fail; 1447 1448 /* Enable clocks */ 1449 error = clk_enable(clk_ahb); 1450 if (error != 0) { 1451 device_printf(dev, "cannot enable ahb clock\n"); 1452 goto fail; 1453 } 1454 if (clk_ephy != NULL) { 1455 error = clk_enable(clk_ephy); 1456 if (error != 0) { 1457 device_printf(dev, "cannot enable ephy clock\n"); 1458 goto fail; 1459 } 1460 } 1461 1462 /* De-assert reset */ 1463 error = hwreset_deassert(rst_ahb); 1464 if (error != 0) { 1465 device_printf(dev, "cannot de-assert ahb reset\n"); 1466 goto fail; 1467 } 1468 if (rst_ephy != NULL) { 1469 /* 1470 * The ephy reset is left de-asserted by U-Boot. Assert it 1471 * here to make sure that we're in a known good state going 1472 * into the PHY reset. 1473 */ 1474 hwreset_assert(rst_ephy); 1475 error = hwreset_deassert(rst_ephy); 1476 if (error != 0) { 1477 device_printf(dev, "cannot de-assert ephy reset\n"); 1478 goto fail; 1479 } 1480 } 1481 1482 /* Enable PHY regulator if applicable */ 1483 if (regulator_get_by_ofw_property(dev, 0, "phy-supply", ®) == 0) { 1484 error = regulator_enable(reg); 1485 if (error != 0) { 1486 device_printf(dev, "cannot enable PHY regulator\n"); 1487 goto fail; 1488 } 1489 } 1490 1491 /* Determine MDC clock divide ratio based on AHB clock */ 1492 error = clk_get_freq(clk_ahb, &freq); 1493 if (error != 0) { 1494 device_printf(dev, "cannot get AHB clock frequency\n"); 1495 goto fail; 1496 } 1497 div = freq / MDIO_FREQ; 1498 if (div <= 16) 1499 sc->mdc_div_ratio_m = MDC_DIV_RATIO_M_16; 1500 else if (div <= 32) 1501 sc->mdc_div_ratio_m = MDC_DIV_RATIO_M_32; 1502 else if (div <= 64) 1503 sc->mdc_div_ratio_m = MDC_DIV_RATIO_M_64; 1504 else if (div <= 128) 1505 sc->mdc_div_ratio_m = MDC_DIV_RATIO_M_128; 1506 else { 1507 device_printf(dev, "cannot determine MDC clock divide ratio\n"); 1508 error = ENXIO; 1509 goto fail; 1510 } 1511 1512 if (bootverbose) 1513 device_printf(dev, "AHB frequency %ju Hz, MDC div: 0x%x\n", 1514 (uintmax_t)freq, sc->mdc_div_ratio_m); 1515 1516 return (0); 1517 1518 fail: 1519 if (reg != NULL) 1520 regulator_release(reg); 1521 if (clk_ephy != NULL) 1522 clk_release(clk_ephy); 1523 if (clk_ahb != NULL) 1524 clk_release(clk_ahb); 1525 if (rst_ephy != NULL) 1526 hwreset_release(rst_ephy); 1527 if (rst_ahb != NULL) 1528 hwreset_release(rst_ahb); 1529 return (error); 1530 } 1531 1532 static void 1533 awg_get_eaddr(device_t dev, uint8_t *eaddr) 1534 { 1535 struct awg_softc *sc; 1536 uint32_t maclo, machi, rnd; 1537 u_char rootkey[16]; 1538 uint32_t rootkey_size; 1539 1540 sc = device_get_softc(dev); 1541 1542 machi = RD4(sc, EMAC_ADDR_HIGH(0)) & 0xffff; 1543 maclo = RD4(sc, EMAC_ADDR_LOW(0)); 1544 1545 rootkey_size = sizeof(rootkey); 1546 if (maclo == 0xffffffff && machi == 0xffff) { 1547 /* MAC address in hardware is invalid, create one */ 1548 if (aw_sid_get_fuse(AW_SID_FUSE_ROOTKEY, rootkey, 1549 &rootkey_size) == 0 && 1550 (rootkey[3] | rootkey[12] | rootkey[13] | rootkey[14] | 1551 rootkey[15]) != 0) { 1552 /* MAC address is derived from the root key in SID */ 1553 maclo = (rootkey[13] << 24) | (rootkey[12] << 16) | 1554 (rootkey[3] << 8) | 0x02; 1555 machi = (rootkey[15] << 8) | rootkey[14]; 1556 } else { 1557 /* Create one */ 1558 rnd = arc4random(); 1559 maclo = 0x00f2 | (rnd & 0xffff0000); 1560 machi = rnd & 0xffff; 1561 } 1562 } 1563 1564 eaddr[0] = maclo & 0xff; 1565 eaddr[1] = (maclo >> 8) & 0xff; 1566 eaddr[2] = (maclo >> 16) & 0xff; 1567 eaddr[3] = (maclo >> 24) & 0xff; 1568 eaddr[4] = machi & 0xff; 1569 eaddr[5] = (machi >> 8) & 0xff; 1570 } 1571 1572 #ifdef AWG_DEBUG 1573 static void 1574 awg_dump_regs(device_t dev) 1575 { 1576 static const struct { 1577 const char *name; 1578 u_int reg; 1579 } regs[] = { 1580 { "BASIC_CTL_0", EMAC_BASIC_CTL_0 }, 1581 { "BASIC_CTL_1", EMAC_BASIC_CTL_1 }, 1582 { "INT_STA", EMAC_INT_STA }, 1583 { "INT_EN", EMAC_INT_EN }, 1584 { "TX_CTL_0", EMAC_TX_CTL_0 }, 1585 { "TX_CTL_1", EMAC_TX_CTL_1 }, 1586 { "TX_FLOW_CTL", EMAC_TX_FLOW_CTL }, 1587 { "TX_DMA_LIST", EMAC_TX_DMA_LIST }, 1588 { "RX_CTL_0", EMAC_RX_CTL_0 }, 1589 { "RX_CTL_1", EMAC_RX_CTL_1 }, 1590 { "RX_DMA_LIST", EMAC_RX_DMA_LIST }, 1591 { "RX_FRM_FLT", EMAC_RX_FRM_FLT }, 1592 { "RX_HASH_0", EMAC_RX_HASH_0 }, 1593 { "RX_HASH_1", EMAC_RX_HASH_1 }, 1594 { "MII_CMD", EMAC_MII_CMD }, 1595 { "ADDR_HIGH0", EMAC_ADDR_HIGH(0) }, 1596 { "ADDR_LOW0", EMAC_ADDR_LOW(0) }, 1597 { "TX_DMA_STA", EMAC_TX_DMA_STA }, 1598 { "TX_DMA_CUR_DESC", EMAC_TX_DMA_CUR_DESC }, 1599 { "TX_DMA_CUR_BUF", EMAC_TX_DMA_CUR_BUF }, 1600 { "RX_DMA_STA", EMAC_RX_DMA_STA }, 1601 { "RX_DMA_CUR_DESC", EMAC_RX_DMA_CUR_DESC }, 1602 { "RX_DMA_CUR_BUF", EMAC_RX_DMA_CUR_BUF }, 1603 { "RGMII_STA", EMAC_RGMII_STA }, 1604 }; 1605 struct awg_softc *sc; 1606 unsigned int n; 1607 1608 sc = device_get_softc(dev); 1609 1610 for (n = 0; n < nitems(regs); n++) 1611 device_printf(dev, " %-20s %08x\n", regs[n].name, 1612 RD4(sc, regs[n].reg)); 1613 } 1614 #endif 1615 1616 #define GPIO_ACTIVE_LOW 1 1617 1618 static int 1619 awg_phy_reset(device_t dev) 1620 { 1621 pcell_t gpio_prop[4], delay_prop[3]; 1622 phandle_t node, gpio_node; 1623 device_t gpio; 1624 uint32_t pin, flags; 1625 uint32_t pin_value; 1626 1627 node = ofw_bus_get_node(dev); 1628 if (OF_getencprop(node, "allwinner,reset-gpio", gpio_prop, 1629 sizeof(gpio_prop)) <= 0) 1630 return (0); 1631 1632 if (OF_getencprop(node, "allwinner,reset-delays-us", delay_prop, 1633 sizeof(delay_prop)) <= 0) 1634 return (ENXIO); 1635 1636 gpio_node = OF_node_from_xref(gpio_prop[0]); 1637 if ((gpio = OF_device_from_xref(gpio_prop[0])) == NULL) 1638 return (ENXIO); 1639 1640 if (GPIO_MAP_GPIOS(gpio, node, gpio_node, nitems(gpio_prop) - 1, 1641 gpio_prop + 1, &pin, &flags) != 0) 1642 return (ENXIO); 1643 1644 pin_value = GPIO_PIN_LOW; 1645 if (OF_hasprop(node, "allwinner,reset-active-low")) 1646 pin_value = GPIO_PIN_HIGH; 1647 1648 if (flags & GPIO_ACTIVE_LOW) 1649 pin_value = !pin_value; 1650 1651 GPIO_PIN_SETFLAGS(gpio, pin, GPIO_PIN_OUTPUT); 1652 GPIO_PIN_SET(gpio, pin, pin_value); 1653 DELAY(delay_prop[0]); 1654 GPIO_PIN_SET(gpio, pin, !pin_value); 1655 DELAY(delay_prop[1]); 1656 GPIO_PIN_SET(gpio, pin, pin_value); 1657 DELAY(delay_prop[2]); 1658 1659 return (0); 1660 } 1661 1662 static int 1663 awg_reset(device_t dev) 1664 { 1665 struct awg_softc *sc; 1666 int retry; 1667 1668 sc = device_get_softc(dev); 1669 1670 /* Reset PHY if necessary */ 1671 if (awg_phy_reset(dev) != 0) { 1672 device_printf(dev, "failed to reset PHY\n"); 1673 return (ENXIO); 1674 } 1675 1676 /* Soft reset all registers and logic */ 1677 WR4(sc, EMAC_BASIC_CTL_1, BASIC_CTL_SOFT_RST); 1678 1679 /* Wait for soft reset bit to self-clear */ 1680 for (retry = SOFT_RST_RETRY; retry > 0; retry--) { 1681 if ((RD4(sc, EMAC_BASIC_CTL_1) & BASIC_CTL_SOFT_RST) == 0) 1682 break; 1683 DELAY(10); 1684 } 1685 if (retry == 0) { 1686 device_printf(dev, "soft reset timed out\n"); 1687 #ifdef AWG_DEBUG 1688 awg_dump_regs(dev); 1689 #endif 1690 return (ETIMEDOUT); 1691 } 1692 1693 return (0); 1694 } 1695 1696 static void 1697 awg_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1698 { 1699 if (error != 0) 1700 return; 1701 *(bus_addr_t *)arg = segs[0].ds_addr; 1702 } 1703 1704 static int 1705 awg_setup_dma(device_t dev) 1706 { 1707 struct awg_softc *sc; 1708 int error, i; 1709 1710 sc = device_get_softc(dev); 1711 1712 /* Setup TX ring */ 1713 error = bus_dma_tag_create( 1714 bus_get_dma_tag(dev), /* Parent tag */ 1715 DESC_ALIGN, 0, /* alignment, boundary */ 1716 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1717 BUS_SPACE_MAXADDR, /* highaddr */ 1718 NULL, NULL, /* filter, filterarg */ 1719 TX_DESC_SIZE, 1, /* maxsize, nsegs */ 1720 TX_DESC_SIZE, /* maxsegsize */ 1721 0, /* flags */ 1722 NULL, NULL, /* lockfunc, lockarg */ 1723 &sc->tx.desc_tag); 1724 if (error != 0) { 1725 device_printf(dev, "cannot create TX descriptor ring tag\n"); 1726 return (error); 1727 } 1728 1729 error = bus_dmamem_alloc(sc->tx.desc_tag, (void **)&sc->tx.desc_ring, 1730 BUS_DMA_COHERENT | BUS_DMA_WAITOK | BUS_DMA_ZERO, &sc->tx.desc_map); 1731 if (error != 0) { 1732 device_printf(dev, "cannot allocate TX descriptor ring\n"); 1733 return (error); 1734 } 1735 1736 error = bus_dmamap_load(sc->tx.desc_tag, sc->tx.desc_map, 1737 sc->tx.desc_ring, TX_DESC_SIZE, awg_dmamap_cb, 1738 &sc->tx.desc_ring_paddr, 0); 1739 if (error != 0) { 1740 device_printf(dev, "cannot load TX descriptor ring\n"); 1741 return (error); 1742 } 1743 1744 for (i = 0; i < TX_DESC_COUNT; i++) 1745 sc->tx.desc_ring[i].next = 1746 htole32(sc->tx.desc_ring_paddr + DESC_OFF(TX_NEXT(i))); 1747 1748 error = bus_dma_tag_create( 1749 bus_get_dma_tag(dev), /* Parent tag */ 1750 1, 0, /* alignment, boundary */ 1751 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1752 BUS_SPACE_MAXADDR, /* highaddr */ 1753 NULL, NULL, /* filter, filterarg */ 1754 MCLBYTES, TX_MAX_SEGS, /* maxsize, nsegs */ 1755 MCLBYTES, /* maxsegsize */ 1756 0, /* flags */ 1757 NULL, NULL, /* lockfunc, lockarg */ 1758 &sc->tx.buf_tag); 1759 if (error != 0) { 1760 device_printf(dev, "cannot create TX buffer tag\n"); 1761 return (error); 1762 } 1763 1764 sc->tx.queued = 0; 1765 for (i = 0; i < TX_DESC_COUNT; i++) { 1766 error = bus_dmamap_create(sc->tx.buf_tag, 0, 1767 &sc->tx.buf_map[i].map); 1768 if (error != 0) { 1769 device_printf(dev, "cannot create TX buffer map\n"); 1770 return (error); 1771 } 1772 } 1773 1774 /* Setup RX ring */ 1775 error = bus_dma_tag_create( 1776 bus_get_dma_tag(dev), /* Parent tag */ 1777 DESC_ALIGN, 0, /* alignment, boundary */ 1778 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1779 BUS_SPACE_MAXADDR, /* highaddr */ 1780 NULL, NULL, /* filter, filterarg */ 1781 RX_DESC_SIZE, 1, /* maxsize, nsegs */ 1782 RX_DESC_SIZE, /* maxsegsize */ 1783 0, /* flags */ 1784 NULL, NULL, /* lockfunc, lockarg */ 1785 &sc->rx.desc_tag); 1786 if (error != 0) { 1787 device_printf(dev, "cannot create RX descriptor ring tag\n"); 1788 return (error); 1789 } 1790 1791 error = bus_dmamem_alloc(sc->rx.desc_tag, (void **)&sc->rx.desc_ring, 1792 BUS_DMA_COHERENT | BUS_DMA_WAITOK | BUS_DMA_ZERO, &sc->rx.desc_map); 1793 if (error != 0) { 1794 device_printf(dev, "cannot allocate RX descriptor ring\n"); 1795 return (error); 1796 } 1797 1798 error = bus_dmamap_load(sc->rx.desc_tag, sc->rx.desc_map, 1799 sc->rx.desc_ring, RX_DESC_SIZE, awg_dmamap_cb, 1800 &sc->rx.desc_ring_paddr, 0); 1801 if (error != 0) { 1802 device_printf(dev, "cannot load RX descriptor ring\n"); 1803 return (error); 1804 } 1805 1806 error = bus_dma_tag_create( 1807 bus_get_dma_tag(dev), /* Parent tag */ 1808 1, 0, /* alignment, boundary */ 1809 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1810 BUS_SPACE_MAXADDR, /* highaddr */ 1811 NULL, NULL, /* filter, filterarg */ 1812 MCLBYTES, 1, /* maxsize, nsegs */ 1813 MCLBYTES, /* maxsegsize */ 1814 0, /* flags */ 1815 NULL, NULL, /* lockfunc, lockarg */ 1816 &sc->rx.buf_tag); 1817 if (error != 0) { 1818 device_printf(dev, "cannot create RX buffer tag\n"); 1819 return (error); 1820 } 1821 1822 error = bus_dmamap_create(sc->rx.buf_tag, 0, &sc->rx.buf_spare_map); 1823 if (error != 0) { 1824 device_printf(dev, 1825 "cannot create RX buffer spare map\n"); 1826 return (error); 1827 } 1828 1829 for (i = 0; i < RX_DESC_COUNT; i++) { 1830 sc->rx.desc_ring[i].next = 1831 htole32(sc->rx.desc_ring_paddr + DESC_OFF(RX_NEXT(i))); 1832 1833 error = bus_dmamap_create(sc->rx.buf_tag, 0, 1834 &sc->rx.buf_map[i].map); 1835 if (error != 0) { 1836 device_printf(dev, "cannot create RX buffer map\n"); 1837 return (error); 1838 } 1839 sc->rx.buf_map[i].mbuf = NULL; 1840 error = awg_newbuf_rx(sc, i); 1841 if (error != 0) { 1842 device_printf(dev, "cannot create RX buffer\n"); 1843 return (error); 1844 } 1845 } 1846 bus_dmamap_sync(sc->rx.desc_tag, sc->rx.desc_map, 1847 BUS_DMASYNC_PREWRITE); 1848 1849 /* Write transmit and receive descriptor base address registers */ 1850 WR4(sc, EMAC_TX_DMA_LIST, sc->tx.desc_ring_paddr); 1851 WR4(sc, EMAC_RX_DMA_LIST, sc->rx.desc_ring_paddr); 1852 1853 return (0); 1854 } 1855 1856 static int 1857 awg_probe(device_t dev) 1858 { 1859 if (!ofw_bus_status_okay(dev)) 1860 return (ENXIO); 1861 1862 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) 1863 return (ENXIO); 1864 1865 device_set_desc(dev, "Allwinner Gigabit Ethernet"); 1866 return (BUS_PROBE_DEFAULT); 1867 } 1868 1869 static int 1870 awg_attach(device_t dev) 1871 { 1872 uint8_t eaddr[ETHER_ADDR_LEN]; 1873 struct awg_softc *sc; 1874 int error; 1875 1876 sc = device_get_softc(dev); 1877 sc->dev = dev; 1878 sc->type = ofw_bus_search_compatible(dev, compat_data)->ocd_data; 1879 1880 if (bus_alloc_resources(dev, awg_spec, sc->res) != 0) { 1881 device_printf(dev, "cannot allocate resources for device\n"); 1882 return (ENXIO); 1883 } 1884 1885 mtx_init(&sc->mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, MTX_DEF); 1886 callout_init_mtx(&sc->stat_ch, &sc->mtx, 0); 1887 TASK_INIT(&sc->link_task, 0, awg_link_task, sc); 1888 1889 /* Setup clocks and regulators */ 1890 error = awg_setup_extres(dev); 1891 if (error != 0) 1892 return (error); 1893 1894 /* Read MAC address before resetting the chip */ 1895 awg_get_eaddr(dev, eaddr); 1896 1897 /* Soft reset EMAC core */ 1898 error = awg_reset(dev); 1899 if (error != 0) 1900 return (error); 1901 1902 /* Setup DMA descriptors */ 1903 error = awg_setup_dma(dev); 1904 if (error != 0) 1905 return (error); 1906 1907 /* Install interrupt handler */ 1908 error = bus_setup_intr(dev, sc->res[_RES_IRQ], 1909 INTR_TYPE_NET | INTR_MPSAFE, NULL, awg_intr, sc, &sc->ih); 1910 if (error != 0) { 1911 device_printf(dev, "cannot setup interrupt handler\n"); 1912 return (error); 1913 } 1914 1915 /* Setup ethernet interface */ 1916 sc->ifp = if_alloc(IFT_ETHER); 1917 if_setsoftc(sc->ifp, sc); 1918 if_initname(sc->ifp, device_get_name(dev), device_get_unit(dev)); 1919 if_setflags(sc->ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); 1920 if_setstartfn(sc->ifp, awg_start); 1921 if_setioctlfn(sc->ifp, awg_ioctl); 1922 if_setinitfn(sc->ifp, awg_init); 1923 if_setsendqlen(sc->ifp, TX_DESC_COUNT - 1); 1924 if_setsendqready(sc->ifp); 1925 if_sethwassist(sc->ifp, CSUM_IP | CSUM_UDP | CSUM_TCP); 1926 if_setcapabilities(sc->ifp, IFCAP_VLAN_MTU | IFCAP_HWCSUM); 1927 if_setcapenable(sc->ifp, if_getcapabilities(sc->ifp)); 1928 #ifdef DEVICE_POLLING 1929 if_setcapabilitiesbit(sc->ifp, IFCAP_POLLING, 0); 1930 #endif 1931 1932 /* Attach MII driver */ 1933 error = mii_attach(dev, &sc->miibus, sc->ifp, awg_media_change, 1934 awg_media_status, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, 1935 MIIF_DOPAUSE); 1936 if (error != 0) { 1937 device_printf(dev, "cannot attach PHY\n"); 1938 return (error); 1939 } 1940 1941 /* Attach ethernet interface */ 1942 ether_ifattach(sc->ifp, eaddr); 1943 1944 return (0); 1945 } 1946 1947 static device_method_t awg_methods[] = { 1948 /* Device interface */ 1949 DEVMETHOD(device_probe, awg_probe), 1950 DEVMETHOD(device_attach, awg_attach), 1951 1952 /* MII interface */ 1953 DEVMETHOD(miibus_readreg, awg_miibus_readreg), 1954 DEVMETHOD(miibus_writereg, awg_miibus_writereg), 1955 DEVMETHOD(miibus_statchg, awg_miibus_statchg), 1956 1957 DEVMETHOD_END 1958 }; 1959 1960 static driver_t awg_driver = { 1961 "awg", 1962 awg_methods, 1963 sizeof(struct awg_softc), 1964 }; 1965 1966 static devclass_t awg_devclass; 1967 1968 DRIVER_MODULE(awg, simplebus, awg_driver, awg_devclass, 0, 0); 1969 DRIVER_MODULE(miibus, awg, miibus_driver, miibus_devclass, 0, 0); 1970 1971 MODULE_DEPEND(awg, ether, 1, 1, 1); 1972 MODULE_DEPEND(awg, miibus, 1, 1, 1); 1973