1 /*- 2 * Copyright (c) 2016 Jared McNeill <jmcneill@invisible.ca> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 16 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 17 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 19 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 20 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 21 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 22 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 */ 28 29 /* 30 * Allwinner Gigabit Ethernet MAC (EMAC) controller 31 */ 32 33 #include "opt_device_polling.h" 34 35 #include <sys/cdefs.h> 36 __FBSDID("$FreeBSD$"); 37 38 #include <sys/param.h> 39 #include <sys/systm.h> 40 #include <sys/bus.h> 41 #include <sys/rman.h> 42 #include <sys/kernel.h> 43 #include <sys/endian.h> 44 #include <sys/mbuf.h> 45 #include <sys/socket.h> 46 #include <sys/sockio.h> 47 #include <sys/module.h> 48 #include <sys/taskqueue.h> 49 #include <sys/gpio.h> 50 51 #include <net/bpf.h> 52 #include <net/if.h> 53 #include <net/ethernet.h> 54 #include <net/if_dl.h> 55 #include <net/if_media.h> 56 #include <net/if_types.h> 57 #include <net/if_var.h> 58 59 #include <machine/bus.h> 60 61 #include <dev/ofw/ofw_bus.h> 62 #include <dev/ofw/ofw_bus_subr.h> 63 64 #include <arm/allwinner/if_awgreg.h> 65 #include <arm/allwinner/aw_sid.h> 66 #include <dev/mii/mii.h> 67 #include <dev/mii/miivar.h> 68 69 #include <dev/extres/clk/clk.h> 70 #include <dev/extres/hwreset/hwreset.h> 71 #include <dev/extres/regulator/regulator.h> 72 73 #include "miibus_if.h" 74 #include "gpio_if.h" 75 76 #define RD4(sc, reg) bus_read_4((sc)->res[_RES_EMAC], (reg)) 77 #define WR4(sc, reg, val) bus_write_4((sc)->res[_RES_EMAC], (reg), (val)) 78 79 #define AWG_LOCK(sc) mtx_lock(&(sc)->mtx) 80 #define AWG_UNLOCK(sc) mtx_unlock(&(sc)->mtx); 81 #define AWG_ASSERT_LOCKED(sc) mtx_assert(&(sc)->mtx, MA_OWNED) 82 #define AWG_ASSERT_UNLOCKED(sc) mtx_assert(&(sc)->mtx, MA_NOTOWNED) 83 84 #define DESC_ALIGN 4 85 #define TX_DESC_COUNT 1024 86 #define TX_DESC_SIZE (sizeof(struct emac_desc) * TX_DESC_COUNT) 87 #define RX_DESC_COUNT 256 88 #define RX_DESC_SIZE (sizeof(struct emac_desc) * RX_DESC_COUNT) 89 90 #define DESC_OFF(n) ((n) * sizeof(struct emac_desc)) 91 #define TX_NEXT(n) (((n) + 1) & (TX_DESC_COUNT - 1)) 92 #define TX_SKIP(n, o) (((n) + (o)) & (TX_DESC_COUNT - 1)) 93 #define RX_NEXT(n) (((n) + 1) & (RX_DESC_COUNT - 1)) 94 95 #define TX_MAX_SEGS 20 96 97 #define SOFT_RST_RETRY 1000 98 #define MII_BUSY_RETRY 1000 99 #define MDIO_FREQ 2500000 100 101 #define BURST_LEN_DEFAULT 8 102 #define RX_TX_PRI_DEFAULT 0 103 #define PAUSE_TIME_DEFAULT 0x400 104 #define TX_INTERVAL_DEFAULT 64 105 #define RX_BATCH_DEFAULT 64 106 107 /* syscon EMAC clock register */ 108 #define EMAC_CLK_EPHY_ADDR (0x1f << 20) /* H3 */ 109 #define EMAC_CLK_EPHY_ADDR_SHIFT 20 110 #define EMAC_CLK_EPHY_LED_POL (1 << 17) /* H3 */ 111 #define EMAC_CLK_EPHY_SHUTDOWN (1 << 16) /* H3 */ 112 #define EMAC_CLK_EPHY_SELECT (1 << 15) /* H3 */ 113 #define EMAC_CLK_RMII_EN (1 << 13) 114 #define EMAC_CLK_ETXDC (0x7 << 10) 115 #define EMAC_CLK_ETXDC_SHIFT 10 116 #define EMAC_CLK_ERXDC (0x1f << 5) 117 #define EMAC_CLK_ERXDC_SHIFT 5 118 #define EMAC_CLK_PIT (0x1 << 2) 119 #define EMAC_CLK_PIT_MII (0 << 2) 120 #define EMAC_CLK_PIT_RGMII (1 << 2) 121 #define EMAC_CLK_SRC (0x3 << 0) 122 #define EMAC_CLK_SRC_MII (0 << 0) 123 #define EMAC_CLK_SRC_EXT_RGMII (1 << 0) 124 #define EMAC_CLK_SRC_RGMII (2 << 0) 125 126 /* Burst length of RX and TX DMA transfers */ 127 static int awg_burst_len = BURST_LEN_DEFAULT; 128 TUNABLE_INT("hw.awg.burst_len", &awg_burst_len); 129 130 /* RX / TX DMA priority. If 1, RX DMA has priority over TX DMA. */ 131 static int awg_rx_tx_pri = RX_TX_PRI_DEFAULT; 132 TUNABLE_INT("hw.awg.rx_tx_pri", &awg_rx_tx_pri); 133 134 /* Pause time field in the transmitted control frame */ 135 static int awg_pause_time = PAUSE_TIME_DEFAULT; 136 TUNABLE_INT("hw.awg.pause_time", &awg_pause_time); 137 138 /* Request a TX interrupt every <n> descriptors */ 139 static int awg_tx_interval = TX_INTERVAL_DEFAULT; 140 TUNABLE_INT("hw.awg.tx_interval", &awg_tx_interval); 141 142 /* Maximum number of mbufs to send to if_input */ 143 static int awg_rx_batch = RX_BATCH_DEFAULT; 144 TUNABLE_INT("hw.awg.rx_batch", &awg_rx_batch); 145 146 enum awg_type { 147 EMAC_A83T = 1, 148 EMAC_H3, 149 EMAC_A64, 150 }; 151 152 static struct ofw_compat_data compat_data[] = { 153 { "allwinner,sun8i-a83t-emac", EMAC_A83T }, 154 { "allwinner,sun8i-h3-emac", EMAC_H3 }, 155 { "allwinner,sun50i-a64-emac", EMAC_A64 }, 156 { NULL, 0 } 157 }; 158 159 struct awg_bufmap { 160 bus_dmamap_t map; 161 struct mbuf *mbuf; 162 }; 163 164 struct awg_txring { 165 bus_dma_tag_t desc_tag; 166 bus_dmamap_t desc_map; 167 struct emac_desc *desc_ring; 168 bus_addr_t desc_ring_paddr; 169 bus_dma_tag_t buf_tag; 170 struct awg_bufmap buf_map[TX_DESC_COUNT]; 171 u_int cur, next, queued; 172 u_int segs; 173 }; 174 175 struct awg_rxring { 176 bus_dma_tag_t desc_tag; 177 bus_dmamap_t desc_map; 178 struct emac_desc *desc_ring; 179 bus_addr_t desc_ring_paddr; 180 bus_dma_tag_t buf_tag; 181 struct awg_bufmap buf_map[RX_DESC_COUNT]; 182 bus_dmamap_t buf_spare_map; 183 u_int cur; 184 }; 185 186 enum { 187 _RES_EMAC, 188 _RES_IRQ, 189 _RES_SYSCON, 190 _RES_NITEMS 191 }; 192 193 struct awg_softc { 194 struct resource *res[_RES_NITEMS]; 195 struct mtx mtx; 196 if_t ifp; 197 device_t dev; 198 device_t miibus; 199 struct callout stat_ch; 200 struct task link_task; 201 void *ih; 202 u_int mdc_div_ratio_m; 203 int link; 204 int if_flags; 205 enum awg_type type; 206 207 struct awg_txring tx; 208 struct awg_rxring rx; 209 }; 210 211 static struct resource_spec awg_spec[] = { 212 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 213 { SYS_RES_IRQ, 0, RF_ACTIVE }, 214 { SYS_RES_MEMORY, 1, RF_ACTIVE | RF_OPTIONAL }, 215 { -1, 0 } 216 }; 217 218 static void awg_txeof(struct awg_softc *sc); 219 220 static int 221 awg_miibus_readreg(device_t dev, int phy, int reg) 222 { 223 struct awg_softc *sc; 224 int retry, val; 225 226 sc = device_get_softc(dev); 227 val = 0; 228 229 WR4(sc, EMAC_MII_CMD, 230 (sc->mdc_div_ratio_m << MDC_DIV_RATIO_M_SHIFT) | 231 (phy << PHY_ADDR_SHIFT) | 232 (reg << PHY_REG_ADDR_SHIFT) | 233 MII_BUSY); 234 for (retry = MII_BUSY_RETRY; retry > 0; retry--) { 235 if ((RD4(sc, EMAC_MII_CMD) & MII_BUSY) == 0) { 236 val = RD4(sc, EMAC_MII_DATA); 237 break; 238 } 239 DELAY(10); 240 } 241 242 if (retry == 0) 243 device_printf(dev, "phy read timeout, phy=%d reg=%d\n", 244 phy, reg); 245 246 return (val); 247 } 248 249 static int 250 awg_miibus_writereg(device_t dev, int phy, int reg, int val) 251 { 252 struct awg_softc *sc; 253 int retry; 254 255 sc = device_get_softc(dev); 256 257 WR4(sc, EMAC_MII_DATA, val); 258 WR4(sc, EMAC_MII_CMD, 259 (sc->mdc_div_ratio_m << MDC_DIV_RATIO_M_SHIFT) | 260 (phy << PHY_ADDR_SHIFT) | 261 (reg << PHY_REG_ADDR_SHIFT) | 262 MII_WR | MII_BUSY); 263 for (retry = MII_BUSY_RETRY; retry > 0; retry--) { 264 if ((RD4(sc, EMAC_MII_CMD) & MII_BUSY) == 0) 265 break; 266 DELAY(10); 267 } 268 269 if (retry == 0) 270 device_printf(dev, "phy write timeout, phy=%d reg=%d\n", 271 phy, reg); 272 273 return (0); 274 } 275 276 static void 277 awg_update_link_locked(struct awg_softc *sc) 278 { 279 struct mii_data *mii; 280 uint32_t val; 281 282 AWG_ASSERT_LOCKED(sc); 283 284 if ((if_getdrvflags(sc->ifp) & IFF_DRV_RUNNING) == 0) 285 return; 286 mii = device_get_softc(sc->miibus); 287 288 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 289 (IFM_ACTIVE | IFM_AVALID)) { 290 switch (IFM_SUBTYPE(mii->mii_media_active)) { 291 case IFM_1000_T: 292 case IFM_1000_SX: 293 case IFM_100_TX: 294 case IFM_10_T: 295 sc->link = 1; 296 break; 297 default: 298 sc->link = 0; 299 break; 300 } 301 } else 302 sc->link = 0; 303 304 if (sc->link == 0) 305 return; 306 307 val = RD4(sc, EMAC_BASIC_CTL_0); 308 val &= ~(BASIC_CTL_SPEED | BASIC_CTL_DUPLEX); 309 310 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T || 311 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) 312 val |= BASIC_CTL_SPEED_1000 << BASIC_CTL_SPEED_SHIFT; 313 else if (IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) 314 val |= BASIC_CTL_SPEED_100 << BASIC_CTL_SPEED_SHIFT; 315 else 316 val |= BASIC_CTL_SPEED_10 << BASIC_CTL_SPEED_SHIFT; 317 318 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) 319 val |= BASIC_CTL_DUPLEX; 320 321 WR4(sc, EMAC_BASIC_CTL_0, val); 322 323 val = RD4(sc, EMAC_RX_CTL_0); 324 val &= ~RX_FLOW_CTL_EN; 325 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 326 val |= RX_FLOW_CTL_EN; 327 WR4(sc, EMAC_RX_CTL_0, val); 328 329 val = RD4(sc, EMAC_TX_FLOW_CTL); 330 val &= ~(PAUSE_TIME|TX_FLOW_CTL_EN); 331 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 332 val |= TX_FLOW_CTL_EN; 333 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) 334 val |= awg_pause_time << PAUSE_TIME_SHIFT; 335 WR4(sc, EMAC_TX_FLOW_CTL, val); 336 } 337 338 static void 339 awg_link_task(void *arg, int pending) 340 { 341 struct awg_softc *sc; 342 343 sc = arg; 344 345 AWG_LOCK(sc); 346 awg_update_link_locked(sc); 347 AWG_UNLOCK(sc); 348 } 349 350 static void 351 awg_miibus_statchg(device_t dev) 352 { 353 struct awg_softc *sc; 354 355 sc = device_get_softc(dev); 356 357 taskqueue_enqueue(taskqueue_swi, &sc->link_task); 358 } 359 360 static void 361 awg_media_status(if_t ifp, struct ifmediareq *ifmr) 362 { 363 struct awg_softc *sc; 364 struct mii_data *mii; 365 366 sc = if_getsoftc(ifp); 367 mii = device_get_softc(sc->miibus); 368 369 AWG_LOCK(sc); 370 mii_pollstat(mii); 371 ifmr->ifm_active = mii->mii_media_active; 372 ifmr->ifm_status = mii->mii_media_status; 373 AWG_UNLOCK(sc); 374 } 375 376 static int 377 awg_media_change(if_t ifp) 378 { 379 struct awg_softc *sc; 380 struct mii_data *mii; 381 int error; 382 383 sc = if_getsoftc(ifp); 384 mii = device_get_softc(sc->miibus); 385 386 AWG_LOCK(sc); 387 error = mii_mediachg(mii); 388 AWG_UNLOCK(sc); 389 390 return (error); 391 } 392 393 static int 394 awg_encap(struct awg_softc *sc, struct mbuf **mp) 395 { 396 bus_dmamap_t map; 397 bus_dma_segment_t segs[TX_MAX_SEGS]; 398 int error, nsegs, cur, first, last, i; 399 u_int csum_flags; 400 uint32_t flags, status; 401 struct mbuf *m; 402 403 cur = first = sc->tx.cur; 404 map = sc->tx.buf_map[first].map; 405 406 m = *mp; 407 error = bus_dmamap_load_mbuf_sg(sc->tx.buf_tag, map, m, segs, 408 &nsegs, BUS_DMA_NOWAIT); 409 if (error == EFBIG) { 410 m = m_collapse(m, M_NOWAIT, TX_MAX_SEGS); 411 if (m == NULL) { 412 device_printf(sc->dev, "awg_encap: m_collapse failed\n"); 413 m_freem(*mp); 414 *mp = NULL; 415 return (ENOMEM); 416 } 417 *mp = m; 418 error = bus_dmamap_load_mbuf_sg(sc->tx.buf_tag, map, m, 419 segs, &nsegs, BUS_DMA_NOWAIT); 420 if (error != 0) { 421 m_freem(*mp); 422 *mp = NULL; 423 } 424 } 425 if (error != 0) { 426 device_printf(sc->dev, "awg_encap: bus_dmamap_load_mbuf_sg failed\n"); 427 return (error); 428 } 429 if (nsegs == 0) { 430 m_freem(*mp); 431 *mp = NULL; 432 return (EIO); 433 } 434 435 if (sc->tx.queued + nsegs > TX_DESC_COUNT) { 436 bus_dmamap_unload(sc->tx.buf_tag, map); 437 return (ENOBUFS); 438 } 439 440 bus_dmamap_sync(sc->tx.buf_tag, map, BUS_DMASYNC_PREWRITE); 441 442 flags = TX_FIR_DESC; 443 status = 0; 444 if ((m->m_pkthdr.csum_flags & CSUM_IP) != 0) { 445 if ((m->m_pkthdr.csum_flags & (CSUM_TCP|CSUM_UDP)) != 0) 446 csum_flags = TX_CHECKSUM_CTL_FULL; 447 else 448 csum_flags = TX_CHECKSUM_CTL_IP; 449 flags |= (csum_flags << TX_CHECKSUM_CTL_SHIFT); 450 } 451 452 for (i = 0; i < nsegs; i++) { 453 sc->tx.segs++; 454 if (i == nsegs - 1) { 455 flags |= TX_LAST_DESC; 456 /* 457 * Can only request TX completion 458 * interrupt on last descriptor. 459 */ 460 if (sc->tx.segs >= awg_tx_interval) { 461 sc->tx.segs = 0; 462 flags |= TX_INT_CTL; 463 } 464 } 465 466 sc->tx.desc_ring[cur].addr = htole32((uint32_t)segs[i].ds_addr); 467 sc->tx.desc_ring[cur].size = htole32(flags | segs[i].ds_len); 468 sc->tx.desc_ring[cur].status = htole32(status); 469 470 flags &= ~TX_FIR_DESC; 471 /* 472 * Setting of the valid bit in the first descriptor is 473 * deferred until the whole chain is fully set up. 474 */ 475 status = TX_DESC_CTL; 476 477 ++sc->tx.queued; 478 cur = TX_NEXT(cur); 479 } 480 481 sc->tx.cur = cur; 482 483 /* Store mapping and mbuf in the last segment */ 484 last = TX_SKIP(cur, TX_DESC_COUNT - 1); 485 sc->tx.buf_map[first].map = sc->tx.buf_map[last].map; 486 sc->tx.buf_map[last].map = map; 487 sc->tx.buf_map[last].mbuf = m; 488 489 /* 490 * The whole mbuf chain has been DMA mapped, 491 * fix the first descriptor. 492 */ 493 sc->tx.desc_ring[first].status = htole32(TX_DESC_CTL); 494 495 return (0); 496 } 497 498 static void 499 awg_clean_txbuf(struct awg_softc *sc, int index) 500 { 501 struct awg_bufmap *bmap; 502 503 --sc->tx.queued; 504 505 bmap = &sc->tx.buf_map[index]; 506 if (bmap->mbuf != NULL) { 507 bus_dmamap_sync(sc->tx.buf_tag, bmap->map, 508 BUS_DMASYNC_POSTWRITE); 509 bus_dmamap_unload(sc->tx.buf_tag, bmap->map); 510 m_freem(bmap->mbuf); 511 bmap->mbuf = NULL; 512 } 513 } 514 515 static void 516 awg_setup_rxdesc(struct awg_softc *sc, int index, bus_addr_t paddr) 517 { 518 uint32_t status, size; 519 520 status = RX_DESC_CTL; 521 size = MCLBYTES - 1; 522 523 sc->rx.desc_ring[index].addr = htole32((uint32_t)paddr); 524 sc->rx.desc_ring[index].size = htole32(size); 525 sc->rx.desc_ring[index].status = htole32(status); 526 } 527 528 static void 529 awg_reuse_rxdesc(struct awg_softc *sc, int index) 530 { 531 532 sc->rx.desc_ring[index].status = htole32(RX_DESC_CTL); 533 } 534 535 static int 536 awg_newbuf_rx(struct awg_softc *sc, int index) 537 { 538 struct mbuf *m; 539 bus_dma_segment_t seg; 540 bus_dmamap_t map; 541 int nsegs; 542 543 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 544 if (m == NULL) 545 return (ENOBUFS); 546 547 m->m_pkthdr.len = m->m_len = m->m_ext.ext_size; 548 m_adj(m, ETHER_ALIGN); 549 550 if (bus_dmamap_load_mbuf_sg(sc->rx.buf_tag, sc->rx.buf_spare_map, 551 m, &seg, &nsegs, BUS_DMA_NOWAIT) != 0) { 552 m_freem(m); 553 return (ENOBUFS); 554 } 555 556 if (sc->rx.buf_map[index].mbuf != NULL) { 557 bus_dmamap_sync(sc->rx.buf_tag, sc->rx.buf_map[index].map, 558 BUS_DMASYNC_POSTREAD); 559 bus_dmamap_unload(sc->rx.buf_tag, sc->rx.buf_map[index].map); 560 } 561 map = sc->rx.buf_map[index].map; 562 sc->rx.buf_map[index].map = sc->rx.buf_spare_map; 563 sc->rx.buf_spare_map = map; 564 bus_dmamap_sync(sc->rx.buf_tag, sc->rx.buf_map[index].map, 565 BUS_DMASYNC_PREREAD); 566 567 sc->rx.buf_map[index].mbuf = m; 568 awg_setup_rxdesc(sc, index, seg.ds_addr); 569 570 return (0); 571 } 572 573 static void 574 awg_start_locked(struct awg_softc *sc) 575 { 576 struct mbuf *m; 577 uint32_t val; 578 if_t ifp; 579 int cnt, err; 580 581 AWG_ASSERT_LOCKED(sc); 582 583 if (!sc->link) 584 return; 585 586 ifp = sc->ifp; 587 588 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING|IFF_DRV_OACTIVE)) != 589 IFF_DRV_RUNNING) 590 return; 591 592 for (cnt = 0; ; cnt++) { 593 m = if_dequeue(ifp); 594 if (m == NULL) 595 break; 596 597 err = awg_encap(sc, &m); 598 if (err != 0) { 599 if (err == ENOBUFS) 600 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0); 601 if (m != NULL) 602 if_sendq_prepend(ifp, m); 603 break; 604 } 605 if_bpfmtap(ifp, m); 606 } 607 608 if (cnt != 0) { 609 bus_dmamap_sync(sc->tx.desc_tag, sc->tx.desc_map, 610 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 611 612 /* Start and run TX DMA */ 613 val = RD4(sc, EMAC_TX_CTL_1); 614 WR4(sc, EMAC_TX_CTL_1, val | TX_DMA_START); 615 } 616 } 617 618 static void 619 awg_start(if_t ifp) 620 { 621 struct awg_softc *sc; 622 623 sc = if_getsoftc(ifp); 624 625 AWG_LOCK(sc); 626 awg_start_locked(sc); 627 AWG_UNLOCK(sc); 628 } 629 630 static void 631 awg_tick(void *softc) 632 { 633 struct awg_softc *sc; 634 struct mii_data *mii; 635 if_t ifp; 636 int link; 637 638 sc = softc; 639 ifp = sc->ifp; 640 mii = device_get_softc(sc->miibus); 641 642 AWG_ASSERT_LOCKED(sc); 643 644 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) 645 return; 646 647 link = sc->link; 648 mii_tick(mii); 649 if (sc->link && !link) 650 awg_start_locked(sc); 651 652 callout_reset(&sc->stat_ch, hz, awg_tick, sc); 653 } 654 655 /* Bit Reversal - http://aggregate.org/MAGIC/#Bit%20Reversal */ 656 static uint32_t 657 bitrev32(uint32_t x) 658 { 659 x = (((x & 0xaaaaaaaa) >> 1) | ((x & 0x55555555) << 1)); 660 x = (((x & 0xcccccccc) >> 2) | ((x & 0x33333333) << 2)); 661 x = (((x & 0xf0f0f0f0) >> 4) | ((x & 0x0f0f0f0f) << 4)); 662 x = (((x & 0xff00ff00) >> 8) | ((x & 0x00ff00ff) << 8)); 663 664 return (x >> 16) | (x << 16); 665 } 666 667 static void 668 awg_setup_rxfilter(struct awg_softc *sc) 669 { 670 uint32_t val, crc, hashreg, hashbit, hash[2], machi, maclo; 671 int mc_count, mcnt, i; 672 uint8_t *eaddr, *mta; 673 if_t ifp; 674 675 AWG_ASSERT_LOCKED(sc); 676 677 ifp = sc->ifp; 678 val = 0; 679 hash[0] = hash[1] = 0; 680 681 mc_count = if_multiaddr_count(ifp, -1); 682 683 if (if_getflags(ifp) & IFF_PROMISC) 684 val |= DIS_ADDR_FILTER; 685 else if (if_getflags(ifp) & IFF_ALLMULTI) { 686 val |= RX_ALL_MULTICAST; 687 hash[0] = hash[1] = ~0; 688 } else if (mc_count > 0) { 689 val |= HASH_MULTICAST; 690 691 mta = malloc(sizeof(unsigned char) * ETHER_ADDR_LEN * mc_count, 692 M_DEVBUF, M_NOWAIT); 693 if (mta == NULL) { 694 if_printf(ifp, 695 "failed to allocate temporary multicast list\n"); 696 return; 697 } 698 699 if_multiaddr_array(ifp, mta, &mcnt, mc_count); 700 for (i = 0; i < mcnt; i++) { 701 crc = ether_crc32_le(mta + (i * ETHER_ADDR_LEN), 702 ETHER_ADDR_LEN) & 0x7f; 703 crc = bitrev32(~crc) >> 26; 704 hashreg = (crc >> 5); 705 hashbit = (crc & 0x1f); 706 hash[hashreg] |= (1 << hashbit); 707 } 708 709 free(mta, M_DEVBUF); 710 } 711 712 /* Write our unicast address */ 713 eaddr = IF_LLADDR(ifp); 714 machi = (eaddr[5] << 8) | eaddr[4]; 715 maclo = (eaddr[3] << 24) | (eaddr[2] << 16) | (eaddr[1] << 8) | 716 (eaddr[0] << 0); 717 WR4(sc, EMAC_ADDR_HIGH(0), machi); 718 WR4(sc, EMAC_ADDR_LOW(0), maclo); 719 720 /* Multicast hash filters */ 721 WR4(sc, EMAC_RX_HASH_0, hash[1]); 722 WR4(sc, EMAC_RX_HASH_1, hash[0]); 723 724 /* RX frame filter config */ 725 WR4(sc, EMAC_RX_FRM_FLT, val); 726 } 727 728 static void 729 awg_enable_intr(struct awg_softc *sc) 730 { 731 /* Enable interrupts */ 732 WR4(sc, EMAC_INT_EN, RX_INT_EN | TX_INT_EN | TX_BUF_UA_INT_EN); 733 } 734 735 static void 736 awg_disable_intr(struct awg_softc *sc) 737 { 738 /* Disable interrupts */ 739 WR4(sc, EMAC_INT_EN, 0); 740 } 741 742 static void 743 awg_init_locked(struct awg_softc *sc) 744 { 745 struct mii_data *mii; 746 uint32_t val; 747 if_t ifp; 748 749 mii = device_get_softc(sc->miibus); 750 ifp = sc->ifp; 751 752 AWG_ASSERT_LOCKED(sc); 753 754 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) 755 return; 756 757 awg_setup_rxfilter(sc); 758 759 /* Configure DMA burst length and priorities */ 760 val = awg_burst_len << BASIC_CTL_BURST_LEN_SHIFT; 761 if (awg_rx_tx_pri) 762 val |= BASIC_CTL_RX_TX_PRI; 763 WR4(sc, EMAC_BASIC_CTL_1, val); 764 765 /* Enable interrupts */ 766 #ifdef DEVICE_POLLING 767 if ((if_getcapenable(ifp) & IFCAP_POLLING) == 0) 768 awg_enable_intr(sc); 769 else 770 awg_disable_intr(sc); 771 #else 772 awg_enable_intr(sc); 773 #endif 774 775 /* Enable transmit DMA */ 776 val = RD4(sc, EMAC_TX_CTL_1); 777 WR4(sc, EMAC_TX_CTL_1, val | TX_DMA_EN | TX_MD | TX_NEXT_FRAME); 778 779 /* Enable receive DMA */ 780 val = RD4(sc, EMAC_RX_CTL_1); 781 WR4(sc, EMAC_RX_CTL_1, val | RX_DMA_EN | RX_MD); 782 783 /* Enable transmitter */ 784 val = RD4(sc, EMAC_TX_CTL_0); 785 WR4(sc, EMAC_TX_CTL_0, val | TX_EN); 786 787 /* Enable receiver */ 788 val = RD4(sc, EMAC_RX_CTL_0); 789 WR4(sc, EMAC_RX_CTL_0, val | RX_EN | CHECK_CRC); 790 791 if_setdrvflagbits(ifp, IFF_DRV_RUNNING, IFF_DRV_OACTIVE); 792 793 mii_mediachg(mii); 794 callout_reset(&sc->stat_ch, hz, awg_tick, sc); 795 } 796 797 static void 798 awg_init(void *softc) 799 { 800 struct awg_softc *sc; 801 802 sc = softc; 803 804 AWG_LOCK(sc); 805 awg_init_locked(sc); 806 AWG_UNLOCK(sc); 807 } 808 809 static void 810 awg_stop(struct awg_softc *sc) 811 { 812 if_t ifp; 813 uint32_t val; 814 int i; 815 816 AWG_ASSERT_LOCKED(sc); 817 818 ifp = sc->ifp; 819 820 callout_stop(&sc->stat_ch); 821 822 /* Stop transmit DMA and flush data in the TX FIFO */ 823 val = RD4(sc, EMAC_TX_CTL_1); 824 val &= ~TX_DMA_EN; 825 val |= FLUSH_TX_FIFO; 826 WR4(sc, EMAC_TX_CTL_1, val); 827 828 /* Disable transmitter */ 829 val = RD4(sc, EMAC_TX_CTL_0); 830 WR4(sc, EMAC_TX_CTL_0, val & ~TX_EN); 831 832 /* Disable receiver */ 833 val = RD4(sc, EMAC_RX_CTL_0); 834 WR4(sc, EMAC_RX_CTL_0, val & ~RX_EN); 835 836 /* Disable interrupts */ 837 awg_disable_intr(sc); 838 839 /* Disable transmit DMA */ 840 val = RD4(sc, EMAC_TX_CTL_1); 841 WR4(sc, EMAC_TX_CTL_1, val & ~TX_DMA_EN); 842 843 /* Disable receive DMA */ 844 val = RD4(sc, EMAC_RX_CTL_1); 845 WR4(sc, EMAC_RX_CTL_1, val & ~RX_DMA_EN); 846 847 sc->link = 0; 848 849 /* Finish handling transmitted buffers */ 850 awg_txeof(sc); 851 852 /* Release any untransmitted buffers. */ 853 for (i = sc->tx.next; sc->tx.queued > 0; i = TX_NEXT(i)) { 854 val = le32toh(sc->tx.desc_ring[i].status); 855 if ((val & TX_DESC_CTL) != 0) 856 break; 857 awg_clean_txbuf(sc, i); 858 } 859 sc->tx.next = i; 860 for (; sc->tx.queued > 0; i = TX_NEXT(i)) { 861 sc->tx.desc_ring[i].status = 0; 862 awg_clean_txbuf(sc, i); 863 } 864 sc->tx.cur = sc->tx.next; 865 bus_dmamap_sync(sc->tx.desc_tag, sc->tx.desc_map, 866 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 867 868 /* Setup RX buffers for reuse */ 869 bus_dmamap_sync(sc->rx.desc_tag, sc->rx.desc_map, 870 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 871 872 for (i = sc->rx.cur; ; i = RX_NEXT(i)) { 873 val = le32toh(sc->rx.desc_ring[i].status); 874 if ((val & RX_DESC_CTL) != 0) 875 break; 876 awg_reuse_rxdesc(sc, i); 877 } 878 sc->rx.cur = i; 879 bus_dmamap_sync(sc->rx.desc_tag, sc->rx.desc_map, 880 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 881 882 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 883 } 884 885 static int 886 awg_rxintr(struct awg_softc *sc) 887 { 888 if_t ifp; 889 struct mbuf *m, *mh, *mt; 890 int error, index, len, cnt, npkt; 891 uint32_t status; 892 893 ifp = sc->ifp; 894 mh = mt = NULL; 895 cnt = 0; 896 npkt = 0; 897 898 bus_dmamap_sync(sc->rx.desc_tag, sc->rx.desc_map, 899 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 900 901 for (index = sc->rx.cur; ; index = RX_NEXT(index)) { 902 status = le32toh(sc->rx.desc_ring[index].status); 903 if ((status & RX_DESC_CTL) != 0) 904 break; 905 906 len = (status & RX_FRM_LEN) >> RX_FRM_LEN_SHIFT; 907 908 if (len == 0) { 909 if ((status & (RX_NO_ENOUGH_BUF_ERR | RX_OVERFLOW_ERR)) != 0) 910 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 911 awg_reuse_rxdesc(sc, index); 912 continue; 913 } 914 915 m = sc->rx.buf_map[index].mbuf; 916 917 error = awg_newbuf_rx(sc, index); 918 if (error != 0) { 919 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 920 awg_reuse_rxdesc(sc, index); 921 continue; 922 } 923 924 m->m_pkthdr.rcvif = ifp; 925 m->m_pkthdr.len = len; 926 m->m_len = len; 927 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); 928 929 if ((if_getcapenable(ifp) & IFCAP_RXCSUM) != 0 && 930 (status & RX_FRM_TYPE) != 0) { 931 m->m_pkthdr.csum_flags = CSUM_IP_CHECKED; 932 if ((status & RX_HEADER_ERR) == 0) 933 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 934 if ((status & RX_PAYLOAD_ERR) == 0) { 935 m->m_pkthdr.csum_flags |= 936 CSUM_DATA_VALID | CSUM_PSEUDO_HDR; 937 m->m_pkthdr.csum_data = 0xffff; 938 } 939 } 940 941 m->m_nextpkt = NULL; 942 if (mh == NULL) 943 mh = m; 944 else 945 mt->m_nextpkt = m; 946 mt = m; 947 ++cnt; 948 ++npkt; 949 950 if (cnt == awg_rx_batch) { 951 AWG_UNLOCK(sc); 952 if_input(ifp, mh); 953 AWG_LOCK(sc); 954 mh = mt = NULL; 955 cnt = 0; 956 } 957 } 958 959 if (index != sc->rx.cur) { 960 bus_dmamap_sync(sc->rx.desc_tag, sc->rx.desc_map, 961 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 962 } 963 964 if (mh != NULL) { 965 AWG_UNLOCK(sc); 966 if_input(ifp, mh); 967 AWG_LOCK(sc); 968 } 969 970 sc->rx.cur = index; 971 972 return (npkt); 973 } 974 975 static void 976 awg_txeof(struct awg_softc *sc) 977 { 978 struct emac_desc *desc; 979 uint32_t status, size; 980 if_t ifp; 981 int i, prog; 982 983 AWG_ASSERT_LOCKED(sc); 984 985 bus_dmamap_sync(sc->tx.desc_tag, sc->tx.desc_map, 986 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 987 988 ifp = sc->ifp; 989 990 prog = 0; 991 for (i = sc->tx.next; sc->tx.queued > 0; i = TX_NEXT(i)) { 992 desc = &sc->tx.desc_ring[i]; 993 status = le32toh(desc->status); 994 if ((status & TX_DESC_CTL) != 0) 995 break; 996 size = le32toh(desc->size); 997 if (size & TX_LAST_DESC) { 998 if ((status & (TX_HEADER_ERR | TX_PAYLOAD_ERR)) != 0) 999 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 1000 else 1001 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); 1002 } 1003 prog++; 1004 awg_clean_txbuf(sc, i); 1005 } 1006 1007 if (prog > 0) { 1008 sc->tx.next = i; 1009 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 1010 } 1011 } 1012 1013 static void 1014 awg_intr(void *arg) 1015 { 1016 struct awg_softc *sc; 1017 uint32_t val; 1018 1019 sc = arg; 1020 1021 AWG_LOCK(sc); 1022 val = RD4(sc, EMAC_INT_STA); 1023 WR4(sc, EMAC_INT_STA, val); 1024 1025 if (val & RX_INT) 1026 awg_rxintr(sc); 1027 1028 if (val & TX_INT) 1029 awg_txeof(sc); 1030 1031 if (val & (TX_INT | TX_BUF_UA_INT)) { 1032 if (!if_sendq_empty(sc->ifp)) 1033 awg_start_locked(sc); 1034 } 1035 1036 AWG_UNLOCK(sc); 1037 } 1038 1039 #ifdef DEVICE_POLLING 1040 static int 1041 awg_poll(if_t ifp, enum poll_cmd cmd, int count) 1042 { 1043 struct awg_softc *sc; 1044 uint32_t val; 1045 int rx_npkts; 1046 1047 sc = if_getsoftc(ifp); 1048 rx_npkts = 0; 1049 1050 AWG_LOCK(sc); 1051 1052 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) { 1053 AWG_UNLOCK(sc); 1054 return (0); 1055 } 1056 1057 rx_npkts = awg_rxintr(sc); 1058 awg_txeof(sc); 1059 if (!if_sendq_empty(ifp)) 1060 awg_start_locked(sc); 1061 1062 if (cmd == POLL_AND_CHECK_STATUS) { 1063 val = RD4(sc, EMAC_INT_STA); 1064 if (val != 0) 1065 WR4(sc, EMAC_INT_STA, val); 1066 } 1067 1068 AWG_UNLOCK(sc); 1069 1070 return (rx_npkts); 1071 } 1072 #endif 1073 1074 static int 1075 awg_ioctl(if_t ifp, u_long cmd, caddr_t data) 1076 { 1077 struct awg_softc *sc; 1078 struct mii_data *mii; 1079 struct ifreq *ifr; 1080 int flags, mask, error; 1081 1082 sc = if_getsoftc(ifp); 1083 mii = device_get_softc(sc->miibus); 1084 ifr = (struct ifreq *)data; 1085 error = 0; 1086 1087 switch (cmd) { 1088 case SIOCSIFFLAGS: 1089 AWG_LOCK(sc); 1090 if (if_getflags(ifp) & IFF_UP) { 1091 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 1092 flags = if_getflags(ifp) ^ sc->if_flags; 1093 if ((flags & (IFF_PROMISC|IFF_ALLMULTI)) != 0) 1094 awg_setup_rxfilter(sc); 1095 } else 1096 awg_init_locked(sc); 1097 } else { 1098 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) 1099 awg_stop(sc); 1100 } 1101 sc->if_flags = if_getflags(ifp); 1102 AWG_UNLOCK(sc); 1103 break; 1104 case SIOCADDMULTI: 1105 case SIOCDELMULTI: 1106 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 1107 AWG_LOCK(sc); 1108 awg_setup_rxfilter(sc); 1109 AWG_UNLOCK(sc); 1110 } 1111 break; 1112 case SIOCSIFMEDIA: 1113 case SIOCGIFMEDIA: 1114 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 1115 break; 1116 case SIOCSIFCAP: 1117 mask = ifr->ifr_reqcap ^ if_getcapenable(ifp); 1118 #ifdef DEVICE_POLLING 1119 if (mask & IFCAP_POLLING) { 1120 if ((ifr->ifr_reqcap & IFCAP_POLLING) != 0) { 1121 error = ether_poll_register(awg_poll, ifp); 1122 if (error != 0) 1123 break; 1124 AWG_LOCK(sc); 1125 awg_disable_intr(sc); 1126 if_setcapenablebit(ifp, IFCAP_POLLING, 0); 1127 AWG_UNLOCK(sc); 1128 } else { 1129 error = ether_poll_deregister(ifp); 1130 AWG_LOCK(sc); 1131 awg_enable_intr(sc); 1132 if_setcapenablebit(ifp, 0, IFCAP_POLLING); 1133 AWG_UNLOCK(sc); 1134 } 1135 } 1136 #endif 1137 if (mask & IFCAP_VLAN_MTU) 1138 if_togglecapenable(ifp, IFCAP_VLAN_MTU); 1139 if (mask & IFCAP_RXCSUM) 1140 if_togglecapenable(ifp, IFCAP_RXCSUM); 1141 if (mask & IFCAP_TXCSUM) 1142 if_togglecapenable(ifp, IFCAP_TXCSUM); 1143 if ((if_getcapenable(ifp) & IFCAP_TXCSUM) != 0) 1144 if_sethwassistbits(ifp, CSUM_IP | CSUM_UDP | CSUM_TCP, 0); 1145 else 1146 if_sethwassistbits(ifp, 0, CSUM_IP | CSUM_UDP | CSUM_TCP); 1147 break; 1148 default: 1149 error = ether_ioctl(ifp, cmd, data); 1150 break; 1151 } 1152 1153 return (error); 1154 } 1155 1156 static int 1157 awg_setup_phy(device_t dev) 1158 { 1159 struct awg_softc *sc; 1160 clk_t clk_tx, clk_tx_parent; 1161 const char *tx_parent_name; 1162 char *phy_type; 1163 phandle_t node; 1164 uint32_t reg, tx_delay, rx_delay; 1165 int error; 1166 1167 sc = device_get_softc(dev); 1168 node = ofw_bus_get_node(dev); 1169 1170 if (OF_getprop_alloc(node, "phy-mode", 1, (void **)&phy_type) == 0) 1171 return (0); 1172 1173 if (bootverbose) 1174 device_printf(dev, "PHY type: %s, conf mode: %s\n", phy_type, 1175 sc->res[_RES_SYSCON] != NULL ? "reg" : "clk"); 1176 1177 if (sc->res[_RES_SYSCON] != NULL) { 1178 reg = bus_read_4(sc->res[_RES_SYSCON], 0); 1179 reg &= ~(EMAC_CLK_PIT | EMAC_CLK_SRC | EMAC_CLK_RMII_EN); 1180 if (strcmp(phy_type, "rgmii") == 0) 1181 reg |= EMAC_CLK_PIT_RGMII | EMAC_CLK_SRC_RGMII; 1182 else if (strcmp(phy_type, "rmii") == 0) 1183 reg |= EMAC_CLK_RMII_EN; 1184 else 1185 reg |= EMAC_CLK_PIT_MII | EMAC_CLK_SRC_MII; 1186 1187 if (OF_getencprop(node, "tx-delay", &tx_delay, 1188 sizeof(tx_delay)) > 0) { 1189 reg &= ~EMAC_CLK_ETXDC; 1190 reg |= (tx_delay << EMAC_CLK_ETXDC_SHIFT); 1191 } 1192 if (OF_getencprop(node, "rx-delay", &rx_delay, 1193 sizeof(rx_delay)) > 0) { 1194 reg &= ~EMAC_CLK_ERXDC; 1195 reg |= (rx_delay << EMAC_CLK_ERXDC_SHIFT); 1196 } 1197 1198 if (sc->type == EMAC_H3) { 1199 if (OF_hasprop(node, "allwinner,use-internal-phy")) { 1200 reg |= EMAC_CLK_EPHY_SELECT; 1201 reg &= ~EMAC_CLK_EPHY_SHUTDOWN; 1202 if (OF_hasprop(node, 1203 "allwinner,leds-active-low")) 1204 reg |= EMAC_CLK_EPHY_LED_POL; 1205 else 1206 reg &= ~EMAC_CLK_EPHY_LED_POL; 1207 1208 /* Set internal PHY addr to 1 */ 1209 reg &= ~EMAC_CLK_EPHY_ADDR; 1210 reg |= (1 << EMAC_CLK_EPHY_ADDR_SHIFT); 1211 } else { 1212 reg &= ~EMAC_CLK_EPHY_SELECT; 1213 } 1214 } 1215 1216 if (bootverbose) 1217 device_printf(dev, "EMAC clock: 0x%08x\n", reg); 1218 bus_write_4(sc->res[_RES_SYSCON], 0, reg); 1219 } else { 1220 if (strcmp(phy_type, "rgmii") == 0) 1221 tx_parent_name = "emac_int_tx"; 1222 else 1223 tx_parent_name = "mii_phy_tx"; 1224 1225 /* Get the TX clock */ 1226 error = clk_get_by_ofw_name(dev, 0, "tx", &clk_tx); 1227 if (error != 0) { 1228 device_printf(dev, "cannot get tx clock\n"); 1229 goto fail; 1230 } 1231 1232 /* Find the desired parent clock based on phy-mode property */ 1233 error = clk_get_by_name(dev, tx_parent_name, &clk_tx_parent); 1234 if (error != 0) { 1235 device_printf(dev, "cannot get clock '%s'\n", 1236 tx_parent_name); 1237 goto fail; 1238 } 1239 1240 /* Set TX clock parent */ 1241 error = clk_set_parent_by_clk(clk_tx, clk_tx_parent); 1242 if (error != 0) { 1243 device_printf(dev, "cannot set tx clock parent\n"); 1244 goto fail; 1245 } 1246 1247 /* Enable TX clock */ 1248 error = clk_enable(clk_tx); 1249 if (error != 0) { 1250 device_printf(dev, "cannot enable tx clock\n"); 1251 goto fail; 1252 } 1253 } 1254 1255 error = 0; 1256 1257 fail: 1258 OF_prop_free(phy_type); 1259 return (error); 1260 } 1261 1262 static int 1263 awg_setup_extres(device_t dev) 1264 { 1265 struct awg_softc *sc; 1266 hwreset_t rst_ahb, rst_ephy; 1267 clk_t clk_ahb, clk_ephy; 1268 regulator_t reg; 1269 phandle_t node; 1270 uint64_t freq; 1271 int error, div; 1272 1273 sc = device_get_softc(dev); 1274 node = ofw_bus_get_node(dev); 1275 rst_ahb = rst_ephy = NULL; 1276 clk_ahb = clk_ephy = NULL; 1277 reg = NULL; 1278 1279 /* Get AHB clock and reset resources */ 1280 error = hwreset_get_by_ofw_name(dev, 0, "ahb", &rst_ahb); 1281 if (error != 0) { 1282 device_printf(dev, "cannot get ahb reset\n"); 1283 goto fail; 1284 } 1285 if (hwreset_get_by_ofw_name(dev, 0, "ephy", &rst_ephy) != 0) 1286 rst_ephy = NULL; 1287 error = clk_get_by_ofw_name(dev, 0, "ahb", &clk_ahb); 1288 if (error != 0) { 1289 device_printf(dev, "cannot get ahb clock\n"); 1290 goto fail; 1291 } 1292 if (clk_get_by_ofw_name(dev, 0, "ephy", &clk_ephy) != 0) 1293 clk_ephy = NULL; 1294 1295 /* Configure PHY for MII or RGMII mode */ 1296 if (awg_setup_phy(dev) != 0) 1297 goto fail; 1298 1299 /* Enable clocks */ 1300 error = clk_enable(clk_ahb); 1301 if (error != 0) { 1302 device_printf(dev, "cannot enable ahb clock\n"); 1303 goto fail; 1304 } 1305 if (clk_ephy != NULL) { 1306 error = clk_enable(clk_ephy); 1307 if (error != 0) { 1308 device_printf(dev, "cannot enable ephy clock\n"); 1309 goto fail; 1310 } 1311 } 1312 1313 /* De-assert reset */ 1314 error = hwreset_deassert(rst_ahb); 1315 if (error != 0) { 1316 device_printf(dev, "cannot de-assert ahb reset\n"); 1317 goto fail; 1318 } 1319 if (rst_ephy != NULL) { 1320 error = hwreset_deassert(rst_ephy); 1321 if (error != 0) { 1322 device_printf(dev, "cannot de-assert ephy reset\n"); 1323 goto fail; 1324 } 1325 } 1326 1327 /* Enable PHY regulator if applicable */ 1328 if (regulator_get_by_ofw_property(dev, 0, "phy-supply", ®) == 0) { 1329 error = regulator_enable(reg); 1330 if (error != 0) { 1331 device_printf(dev, "cannot enable PHY regulator\n"); 1332 goto fail; 1333 } 1334 } 1335 1336 /* Determine MDC clock divide ratio based on AHB clock */ 1337 error = clk_get_freq(clk_ahb, &freq); 1338 if (error != 0) { 1339 device_printf(dev, "cannot get AHB clock frequency\n"); 1340 goto fail; 1341 } 1342 div = freq / MDIO_FREQ; 1343 if (div <= 16) 1344 sc->mdc_div_ratio_m = MDC_DIV_RATIO_M_16; 1345 else if (div <= 32) 1346 sc->mdc_div_ratio_m = MDC_DIV_RATIO_M_32; 1347 else if (div <= 64) 1348 sc->mdc_div_ratio_m = MDC_DIV_RATIO_M_64; 1349 else if (div <= 128) 1350 sc->mdc_div_ratio_m = MDC_DIV_RATIO_M_128; 1351 else { 1352 device_printf(dev, "cannot determine MDC clock divide ratio\n"); 1353 error = ENXIO; 1354 goto fail; 1355 } 1356 1357 if (bootverbose) 1358 device_printf(dev, "AHB frequency %ju Hz, MDC div: 0x%x\n", 1359 (uintmax_t)freq, sc->mdc_div_ratio_m); 1360 1361 return (0); 1362 1363 fail: 1364 if (reg != NULL) 1365 regulator_release(reg); 1366 if (clk_ephy != NULL) 1367 clk_release(clk_ephy); 1368 if (clk_ahb != NULL) 1369 clk_release(clk_ahb); 1370 if (rst_ephy != NULL) 1371 hwreset_release(rst_ephy); 1372 if (rst_ahb != NULL) 1373 hwreset_release(rst_ahb); 1374 return (error); 1375 } 1376 1377 static void 1378 awg_get_eaddr(device_t dev, uint8_t *eaddr) 1379 { 1380 struct awg_softc *sc; 1381 uint32_t maclo, machi, rnd; 1382 u_char rootkey[16]; 1383 1384 sc = device_get_softc(dev); 1385 1386 machi = RD4(sc, EMAC_ADDR_HIGH(0)) & 0xffff; 1387 maclo = RD4(sc, EMAC_ADDR_LOW(0)); 1388 1389 if (maclo == 0xffffffff && machi == 0xffff) { 1390 /* MAC address in hardware is invalid, create one */ 1391 if (aw_sid_get_rootkey(rootkey) == 0 && 1392 (rootkey[3] | rootkey[12] | rootkey[13] | rootkey[14] | 1393 rootkey[15]) != 0) { 1394 /* MAC address is derived from the root key in SID */ 1395 maclo = (rootkey[13] << 24) | (rootkey[12] << 16) | 1396 (rootkey[3] << 8) | 0x02; 1397 machi = (rootkey[15] << 8) | rootkey[14]; 1398 } else { 1399 /* Create one */ 1400 rnd = arc4random(); 1401 maclo = 0x00f2 | (rnd & 0xffff0000); 1402 machi = rnd & 0xffff; 1403 } 1404 } 1405 1406 eaddr[0] = maclo & 0xff; 1407 eaddr[1] = (maclo >> 8) & 0xff; 1408 eaddr[2] = (maclo >> 16) & 0xff; 1409 eaddr[3] = (maclo >> 24) & 0xff; 1410 eaddr[4] = machi & 0xff; 1411 eaddr[5] = (machi >> 8) & 0xff; 1412 } 1413 1414 #ifdef AWG_DEBUG 1415 static void 1416 awg_dump_regs(device_t dev) 1417 { 1418 static const struct { 1419 const char *name; 1420 u_int reg; 1421 } regs[] = { 1422 { "BASIC_CTL_0", EMAC_BASIC_CTL_0 }, 1423 { "BASIC_CTL_1", EMAC_BASIC_CTL_1 }, 1424 { "INT_STA", EMAC_INT_STA }, 1425 { "INT_EN", EMAC_INT_EN }, 1426 { "TX_CTL_0", EMAC_TX_CTL_0 }, 1427 { "TX_CTL_1", EMAC_TX_CTL_1 }, 1428 { "TX_FLOW_CTL", EMAC_TX_FLOW_CTL }, 1429 { "TX_DMA_LIST", EMAC_TX_DMA_LIST }, 1430 { "RX_CTL_0", EMAC_RX_CTL_0 }, 1431 { "RX_CTL_1", EMAC_RX_CTL_1 }, 1432 { "RX_DMA_LIST", EMAC_RX_DMA_LIST }, 1433 { "RX_FRM_FLT", EMAC_RX_FRM_FLT }, 1434 { "RX_HASH_0", EMAC_RX_HASH_0 }, 1435 { "RX_HASH_1", EMAC_RX_HASH_1 }, 1436 { "MII_CMD", EMAC_MII_CMD }, 1437 { "ADDR_HIGH0", EMAC_ADDR_HIGH(0) }, 1438 { "ADDR_LOW0", EMAC_ADDR_LOW(0) }, 1439 { "TX_DMA_STA", EMAC_TX_DMA_STA }, 1440 { "TX_DMA_CUR_DESC", EMAC_TX_DMA_CUR_DESC }, 1441 { "TX_DMA_CUR_BUF", EMAC_TX_DMA_CUR_BUF }, 1442 { "RX_DMA_STA", EMAC_RX_DMA_STA }, 1443 { "RX_DMA_CUR_DESC", EMAC_RX_DMA_CUR_DESC }, 1444 { "RX_DMA_CUR_BUF", EMAC_RX_DMA_CUR_BUF }, 1445 { "RGMII_STA", EMAC_RGMII_STA }, 1446 }; 1447 struct awg_softc *sc; 1448 unsigned int n; 1449 1450 sc = device_get_softc(dev); 1451 1452 for (n = 0; n < nitems(regs); n++) 1453 device_printf(dev, " %-20s %08x\n", regs[n].name, 1454 RD4(sc, regs[n].reg)); 1455 } 1456 #endif 1457 1458 #define GPIO_ACTIVE_LOW 1 1459 1460 static int 1461 awg_phy_reset(device_t dev) 1462 { 1463 pcell_t gpio_prop[4], delay_prop[3]; 1464 phandle_t node, gpio_node; 1465 device_t gpio; 1466 uint32_t pin, flags; 1467 uint32_t pin_value; 1468 1469 node = ofw_bus_get_node(dev); 1470 if (OF_getencprop(node, "allwinner,reset-gpio", gpio_prop, 1471 sizeof(gpio_prop)) <= 0) 1472 return (0); 1473 1474 if (OF_getencprop(node, "allwinner,reset-delays-us", delay_prop, 1475 sizeof(delay_prop)) <= 0) 1476 return (ENXIO); 1477 1478 gpio_node = OF_node_from_xref(gpio_prop[0]); 1479 if ((gpio = OF_device_from_xref(gpio_prop[0])) == NULL) 1480 return (ENXIO); 1481 1482 if (GPIO_MAP_GPIOS(gpio, node, gpio_node, nitems(gpio_prop) - 1, 1483 gpio_prop + 1, &pin, &flags) != 0) 1484 return (ENXIO); 1485 1486 pin_value = GPIO_PIN_LOW; 1487 if (OF_hasprop(node, "allwinner,reset-active-low")) 1488 pin_value = GPIO_PIN_HIGH; 1489 1490 if (flags & GPIO_ACTIVE_LOW) 1491 pin_value = !pin_value; 1492 1493 GPIO_PIN_SETFLAGS(gpio, pin, GPIO_PIN_OUTPUT); 1494 GPIO_PIN_SET(gpio, pin, pin_value); 1495 DELAY(delay_prop[0]); 1496 GPIO_PIN_SET(gpio, pin, !pin_value); 1497 DELAY(delay_prop[1]); 1498 GPIO_PIN_SET(gpio, pin, pin_value); 1499 DELAY(delay_prop[2]); 1500 1501 return (0); 1502 } 1503 1504 static int 1505 awg_reset(device_t dev) 1506 { 1507 struct awg_softc *sc; 1508 int retry; 1509 1510 sc = device_get_softc(dev); 1511 1512 /* Reset PHY if necessary */ 1513 if (awg_phy_reset(dev) != 0) { 1514 device_printf(dev, "failed to reset PHY\n"); 1515 return (ENXIO); 1516 } 1517 1518 /* Soft reset all registers and logic */ 1519 WR4(sc, EMAC_BASIC_CTL_1, BASIC_CTL_SOFT_RST); 1520 1521 /* Wait for soft reset bit to self-clear */ 1522 for (retry = SOFT_RST_RETRY; retry > 0; retry--) { 1523 if ((RD4(sc, EMAC_BASIC_CTL_1) & BASIC_CTL_SOFT_RST) == 0) 1524 break; 1525 DELAY(10); 1526 } 1527 if (retry == 0) { 1528 device_printf(dev, "soft reset timed out\n"); 1529 #ifdef AWG_DEBUG 1530 awg_dump_regs(dev); 1531 #endif 1532 return (ETIMEDOUT); 1533 } 1534 1535 return (0); 1536 } 1537 1538 static void 1539 awg_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1540 { 1541 if (error != 0) 1542 return; 1543 *(bus_addr_t *)arg = segs[0].ds_addr; 1544 } 1545 1546 static int 1547 awg_setup_dma(device_t dev) 1548 { 1549 struct awg_softc *sc; 1550 int error, i; 1551 1552 sc = device_get_softc(dev); 1553 1554 /* Setup TX ring */ 1555 error = bus_dma_tag_create( 1556 bus_get_dma_tag(dev), /* Parent tag */ 1557 DESC_ALIGN, 0, /* alignment, boundary */ 1558 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1559 BUS_SPACE_MAXADDR, /* highaddr */ 1560 NULL, NULL, /* filter, filterarg */ 1561 TX_DESC_SIZE, 1, /* maxsize, nsegs */ 1562 TX_DESC_SIZE, /* maxsegsize */ 1563 0, /* flags */ 1564 NULL, NULL, /* lockfunc, lockarg */ 1565 &sc->tx.desc_tag); 1566 if (error != 0) { 1567 device_printf(dev, "cannot create TX descriptor ring tag\n"); 1568 return (error); 1569 } 1570 1571 error = bus_dmamem_alloc(sc->tx.desc_tag, (void **)&sc->tx.desc_ring, 1572 BUS_DMA_COHERENT | BUS_DMA_WAITOK | BUS_DMA_ZERO, &sc->tx.desc_map); 1573 if (error != 0) { 1574 device_printf(dev, "cannot allocate TX descriptor ring\n"); 1575 return (error); 1576 } 1577 1578 error = bus_dmamap_load(sc->tx.desc_tag, sc->tx.desc_map, 1579 sc->tx.desc_ring, TX_DESC_SIZE, awg_dmamap_cb, 1580 &sc->tx.desc_ring_paddr, 0); 1581 if (error != 0) { 1582 device_printf(dev, "cannot load TX descriptor ring\n"); 1583 return (error); 1584 } 1585 1586 for (i = 0; i < TX_DESC_COUNT; i++) 1587 sc->tx.desc_ring[i].next = 1588 htole32(sc->tx.desc_ring_paddr + DESC_OFF(TX_NEXT(i))); 1589 1590 error = bus_dma_tag_create( 1591 bus_get_dma_tag(dev), /* Parent tag */ 1592 1, 0, /* alignment, boundary */ 1593 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1594 BUS_SPACE_MAXADDR, /* highaddr */ 1595 NULL, NULL, /* filter, filterarg */ 1596 MCLBYTES, TX_MAX_SEGS, /* maxsize, nsegs */ 1597 MCLBYTES, /* maxsegsize */ 1598 0, /* flags */ 1599 NULL, NULL, /* lockfunc, lockarg */ 1600 &sc->tx.buf_tag); 1601 if (error != 0) { 1602 device_printf(dev, "cannot create TX buffer tag\n"); 1603 return (error); 1604 } 1605 1606 sc->tx.queued = 0; 1607 for (i = 0; i < TX_DESC_COUNT; i++) { 1608 error = bus_dmamap_create(sc->tx.buf_tag, 0, 1609 &sc->tx.buf_map[i].map); 1610 if (error != 0) { 1611 device_printf(dev, "cannot create TX buffer map\n"); 1612 return (error); 1613 } 1614 } 1615 1616 /* Setup RX ring */ 1617 error = bus_dma_tag_create( 1618 bus_get_dma_tag(dev), /* Parent tag */ 1619 DESC_ALIGN, 0, /* alignment, boundary */ 1620 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1621 BUS_SPACE_MAXADDR, /* highaddr */ 1622 NULL, NULL, /* filter, filterarg */ 1623 RX_DESC_SIZE, 1, /* maxsize, nsegs */ 1624 RX_DESC_SIZE, /* maxsegsize */ 1625 0, /* flags */ 1626 NULL, NULL, /* lockfunc, lockarg */ 1627 &sc->rx.desc_tag); 1628 if (error != 0) { 1629 device_printf(dev, "cannot create RX descriptor ring tag\n"); 1630 return (error); 1631 } 1632 1633 error = bus_dmamem_alloc(sc->rx.desc_tag, (void **)&sc->rx.desc_ring, 1634 BUS_DMA_COHERENT | BUS_DMA_WAITOK | BUS_DMA_ZERO, &sc->rx.desc_map); 1635 if (error != 0) { 1636 device_printf(dev, "cannot allocate RX descriptor ring\n"); 1637 return (error); 1638 } 1639 1640 error = bus_dmamap_load(sc->rx.desc_tag, sc->rx.desc_map, 1641 sc->rx.desc_ring, RX_DESC_SIZE, awg_dmamap_cb, 1642 &sc->rx.desc_ring_paddr, 0); 1643 if (error != 0) { 1644 device_printf(dev, "cannot load RX descriptor ring\n"); 1645 return (error); 1646 } 1647 1648 error = bus_dma_tag_create( 1649 bus_get_dma_tag(dev), /* Parent tag */ 1650 1, 0, /* alignment, boundary */ 1651 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1652 BUS_SPACE_MAXADDR, /* highaddr */ 1653 NULL, NULL, /* filter, filterarg */ 1654 MCLBYTES, 1, /* maxsize, nsegs */ 1655 MCLBYTES, /* maxsegsize */ 1656 0, /* flags */ 1657 NULL, NULL, /* lockfunc, lockarg */ 1658 &sc->rx.buf_tag); 1659 if (error != 0) { 1660 device_printf(dev, "cannot create RX buffer tag\n"); 1661 return (error); 1662 } 1663 1664 error = bus_dmamap_create(sc->rx.buf_tag, 0, &sc->rx.buf_spare_map); 1665 if (error != 0) { 1666 device_printf(dev, 1667 "cannot create RX buffer spare map\n"); 1668 return (error); 1669 } 1670 1671 for (i = 0; i < RX_DESC_COUNT; i++) { 1672 sc->rx.desc_ring[i].next = 1673 htole32(sc->rx.desc_ring_paddr + DESC_OFF(RX_NEXT(i))); 1674 1675 error = bus_dmamap_create(sc->rx.buf_tag, 0, 1676 &sc->rx.buf_map[i].map); 1677 if (error != 0) { 1678 device_printf(dev, "cannot create RX buffer map\n"); 1679 return (error); 1680 } 1681 sc->rx.buf_map[i].mbuf = NULL; 1682 error = awg_newbuf_rx(sc, i); 1683 if (error != 0) { 1684 device_printf(dev, "cannot create RX buffer\n"); 1685 return (error); 1686 } 1687 } 1688 bus_dmamap_sync(sc->rx.desc_tag, sc->rx.desc_map, 1689 BUS_DMASYNC_PREWRITE); 1690 1691 /* Write transmit and receive descriptor base address registers */ 1692 WR4(sc, EMAC_TX_DMA_LIST, sc->tx.desc_ring_paddr); 1693 WR4(sc, EMAC_RX_DMA_LIST, sc->rx.desc_ring_paddr); 1694 1695 return (0); 1696 } 1697 1698 static int 1699 awg_probe(device_t dev) 1700 { 1701 if (!ofw_bus_status_okay(dev)) 1702 return (ENXIO); 1703 1704 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) 1705 return (ENXIO); 1706 1707 device_set_desc(dev, "Allwinner Gigabit Ethernet"); 1708 return (BUS_PROBE_DEFAULT); 1709 } 1710 1711 static int 1712 awg_attach(device_t dev) 1713 { 1714 uint8_t eaddr[ETHER_ADDR_LEN]; 1715 struct awg_softc *sc; 1716 phandle_t node; 1717 int error; 1718 1719 sc = device_get_softc(dev); 1720 sc->dev = dev; 1721 sc->type = ofw_bus_search_compatible(dev, compat_data)->ocd_data; 1722 node = ofw_bus_get_node(dev); 1723 1724 if (bus_alloc_resources(dev, awg_spec, sc->res) != 0) { 1725 device_printf(dev, "cannot allocate resources for device\n"); 1726 return (ENXIO); 1727 } 1728 1729 mtx_init(&sc->mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, MTX_DEF); 1730 callout_init_mtx(&sc->stat_ch, &sc->mtx, 0); 1731 TASK_INIT(&sc->link_task, 0, awg_link_task, sc); 1732 1733 /* Setup clocks and regulators */ 1734 error = awg_setup_extres(dev); 1735 if (error != 0) 1736 return (error); 1737 1738 /* Read MAC address before resetting the chip */ 1739 awg_get_eaddr(dev, eaddr); 1740 1741 /* Soft reset EMAC core */ 1742 error = awg_reset(dev); 1743 if (error != 0) 1744 return (error); 1745 1746 /* Setup DMA descriptors */ 1747 error = awg_setup_dma(dev); 1748 if (error != 0) 1749 return (error); 1750 1751 /* Install interrupt handler */ 1752 error = bus_setup_intr(dev, sc->res[_RES_IRQ], 1753 INTR_TYPE_NET | INTR_MPSAFE, NULL, awg_intr, sc, &sc->ih); 1754 if (error != 0) { 1755 device_printf(dev, "cannot setup interrupt handler\n"); 1756 return (error); 1757 } 1758 1759 /* Setup ethernet interface */ 1760 sc->ifp = if_alloc(IFT_ETHER); 1761 if_setsoftc(sc->ifp, sc); 1762 if_initname(sc->ifp, device_get_name(dev), device_get_unit(dev)); 1763 if_setflags(sc->ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); 1764 if_setstartfn(sc->ifp, awg_start); 1765 if_setioctlfn(sc->ifp, awg_ioctl); 1766 if_setinitfn(sc->ifp, awg_init); 1767 if_setsendqlen(sc->ifp, TX_DESC_COUNT - 1); 1768 if_setsendqready(sc->ifp); 1769 if_sethwassist(sc->ifp, CSUM_IP | CSUM_UDP | CSUM_TCP); 1770 if_setcapabilities(sc->ifp, IFCAP_VLAN_MTU | IFCAP_HWCSUM); 1771 if_setcapenable(sc->ifp, if_getcapabilities(sc->ifp)); 1772 #ifdef DEVICE_POLLING 1773 if_setcapabilitiesbit(sc->ifp, IFCAP_POLLING, 0); 1774 #endif 1775 1776 /* Attach MII driver */ 1777 error = mii_attach(dev, &sc->miibus, sc->ifp, awg_media_change, 1778 awg_media_status, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, 1779 MIIF_DOPAUSE); 1780 if (error != 0) { 1781 device_printf(dev, "cannot attach PHY\n"); 1782 return (error); 1783 } 1784 1785 /* Attach ethernet interface */ 1786 ether_ifattach(sc->ifp, eaddr); 1787 1788 return (0); 1789 } 1790 1791 static device_method_t awg_methods[] = { 1792 /* Device interface */ 1793 DEVMETHOD(device_probe, awg_probe), 1794 DEVMETHOD(device_attach, awg_attach), 1795 1796 /* MII interface */ 1797 DEVMETHOD(miibus_readreg, awg_miibus_readreg), 1798 DEVMETHOD(miibus_writereg, awg_miibus_writereg), 1799 DEVMETHOD(miibus_statchg, awg_miibus_statchg), 1800 1801 DEVMETHOD_END 1802 }; 1803 1804 static driver_t awg_driver = { 1805 "awg", 1806 awg_methods, 1807 sizeof(struct awg_softc), 1808 }; 1809 1810 static devclass_t awg_devclass; 1811 1812 DRIVER_MODULE(awg, simplebus, awg_driver, awg_devclass, 0, 0); 1813 DRIVER_MODULE(miibus, awg, miibus_driver, miibus_devclass, 0, 0); 1814 1815 MODULE_DEPEND(awg, ether, 1, 1, 1); 1816 MODULE_DEPEND(awg, miibus, 1, 1, 1); 1817