1 /*- 2 * Copyright (c) 2014-2017 Ruslan Bukin <br@bsdpad.com> 3 * All rights reserved. 4 * 5 * This software was developed by SRI International and the University of 6 * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237) 7 * ("CTSRD"), as part of the DARPA CRASH research programme. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 #include "opt_platform.h" 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD$"); 35 36 #include <sys/param.h> 37 #include <sys/systm.h> 38 #include <sys/bus.h> 39 #include <sys/devmap.h> 40 41 #include <vm/vm.h> 42 43 #include <dev/ofw/openfirm.h> 44 45 #include <machine/armreg.h> 46 #include <machine/bus.h> 47 #include <machine/fdt.h> 48 #include <machine/machdep.h> 49 #include <machine/platform.h> 50 #include <machine/platformvar.h> 51 52 #include <arm/altera/socfpga/socfpga_mp.h> 53 #include <arm/altera/socfpga/socfpga_rstmgr.h> 54 55 #include "platform_if.h" 56 57 #if defined(SOC_ALTERA_CYCLONE5) 58 static int 59 socfpga_devmap_init(platform_t plat) 60 { 61 62 /* UART */ 63 devmap_add_entry(0xffc00000, 0x100000); 64 65 /* 66 * USB OTG 67 * 68 * We use static device map for USB due to some bug in the Altera 69 * which throws Translation Fault (P) exception on high load. 70 * It might be caused due to some power save options being turned 71 * on or something else. 72 */ 73 devmap_add_entry(0xffb00000, 0x100000); 74 75 /* dwmmc */ 76 devmap_add_entry(0xff700000, 0x100000); 77 78 /* scu */ 79 devmap_add_entry(0xfff00000, 0x100000); 80 81 /* FPGA memory window, 256MB */ 82 devmap_add_entry(0xd0000000, 0x10000000); 83 84 return (0); 85 } 86 #endif 87 88 #if defined(SOC_ALTERA_ARRIA10) 89 static int 90 socfpga_a10_devmap_init(platform_t plat) 91 { 92 93 /* UART */ 94 devmap_add_entry(0xffc00000, 0x100000); 95 96 /* USB OTG */ 97 devmap_add_entry(0xffb00000, 0x100000); 98 99 /* dwmmc */ 100 devmap_add_entry(0xff800000, 0x100000); 101 102 /* scu */ 103 devmap_add_entry(0xfff00000, 0x100000); 104 105 return (0); 106 } 107 #endif 108 109 static void 110 _socfpga_cpu_reset(bus_size_t reg) 111 { 112 uint32_t paddr; 113 bus_addr_t vaddr; 114 phandle_t node; 115 116 if (rstmgr_warmreset(reg) == 0) 117 goto end; 118 119 node = OF_finddevice("/soc/rstmgr"); 120 if (node == -1) 121 goto end; 122 123 if ((OF_getencprop(node, "reg", &paddr, sizeof(paddr))) > 0) { 124 if (bus_space_map(fdtbus_bs_tag, paddr, 0x8, 0, &vaddr) == 0) { 125 bus_space_write_4(fdtbus_bs_tag, vaddr, 126 reg, CTRL_SWWARMRSTREQ); 127 } 128 } 129 130 end: 131 while (1); 132 } 133 134 #if defined(SOC_ALTERA_CYCLONE5) 135 static void 136 socfpga_cpu_reset(platform_t plat) 137 { 138 139 _socfpga_cpu_reset(RSTMGR_CTRL); 140 } 141 #endif 142 143 #if defined(SOC_ALTERA_ARRIA10) 144 static void 145 socfpga_a10_cpu_reset(platform_t plat) 146 { 147 148 _socfpga_cpu_reset(RSTMGR_A10_CTRL); 149 } 150 #endif 151 152 #if defined(SOC_ALTERA_CYCLONE5) 153 static platform_method_t socfpga_methods[] = { 154 PLATFORMMETHOD(platform_devmap_init, socfpga_devmap_init), 155 PLATFORMMETHOD(platform_cpu_reset, socfpga_cpu_reset), 156 #ifdef SMP 157 PLATFORMMETHOD(platform_mp_setmaxid, socfpga_mp_setmaxid), 158 PLATFORMMETHOD(platform_mp_start_ap, socfpga_mp_start_ap), 159 #endif 160 PLATFORMMETHOD_END, 161 }; 162 FDT_PLATFORM_DEF(socfpga, "socfpga", 0, "altr,socfpga-cyclone5", 200); 163 #endif 164 165 #if defined(SOC_ALTERA_ARRIA10) 166 static platform_method_t socfpga_a10_methods[] = { 167 PLATFORMMETHOD(platform_devmap_init, socfpga_a10_devmap_init), 168 PLATFORMMETHOD(platform_cpu_reset, socfpga_a10_cpu_reset), 169 #ifdef SMP 170 PLATFORMMETHOD(platform_mp_setmaxid, socfpga_mp_setmaxid), 171 PLATFORMMETHOD(platform_mp_start_ap, socfpga_a10_mp_start_ap), 172 #endif 173 PLATFORMMETHOD_END, 174 }; 175 FDT_PLATFORM_DEF(socfpga_a10, "socfpga", 0, "altr,socfpga-arria10", 200); 176 #endif 177