1 /*- 2 * Copyright (c) 2014-2017 Ruslan Bukin <br@bsdpad.com> 3 * All rights reserved. 4 * 5 * This software was developed by SRI International and the University of 6 * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237) 7 * ("CTSRD"), as part of the DARPA CRASH research programme. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 #include "opt_platform.h" 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/bus.h> 36 #include <sys/kernel.h> 37 #include <sys/lock.h> 38 #include <sys/mutex.h> 39 #include <sys/smp.h> 40 41 #include <vm/vm.h> 42 #include <vm/pmap.h> 43 44 #include <machine/cpu.h> 45 #include <machine/smp.h> 46 #include <machine/fdt.h> 47 #include <machine/intr.h> 48 #include <machine/platformvar.h> 49 50 #include <arm/altera/socfpga/socfpga_mp.h> 51 #include <arm/altera/socfpga/socfpga_rstmgr.h> 52 53 #define SCU_PHYSBASE 0xFFFEC000 54 #define SCU_PHYSBASE_A10 0xFFFFC000 55 #define SCU_SIZE 0x100 56 57 #define SCU_CONTROL_REG 0x00 58 #define SCU_CONTROL_ENABLE (1 << 0) 59 #define SCU_CONFIG_REG 0x04 60 #define SCU_CONFIG_REG_NCPU_MASK 0x03 61 #define SCU_CPUPOWER_REG 0x08 62 #define SCU_INV_TAGS_REG 0x0c 63 #define SCU_DIAG_CONTROL 0x30 64 #define SCU_DIAG_DISABLE_MIGBIT (1 << 0) 65 #define SCU_FILTER_START_REG 0x40 66 #define SCU_FILTER_END_REG 0x44 67 #define SCU_SECURE_ACCESS_REG 0x50 68 #define SCU_NONSECURE_ACCESS_REG 0x54 69 70 #define RSTMGR_PHYSBASE 0xFFD05000 71 #define RSTMGR_SIZE 0x100 72 73 #define RAM_PHYSBASE 0x0 74 #define RAM_SIZE 0x1000 75 76 #define SOCFPGA_ARRIA10 1 77 #define SOCFPGA_CYCLONE5 2 78 79 extern char *mpentry_addr; 80 static void socfpga_trampoline(void); 81 82 static void 83 socfpga_trampoline(void) 84 { 85 86 __asm __volatile( 87 "ldr pc, 1f\n" 88 ".globl mpentry_addr\n" 89 "mpentry_addr:\n" 90 "1: .space 4\n"); 91 } 92 93 void 94 socfpga_mp_setmaxid(platform_t plat) 95 { 96 int hwcpu, ncpu; 97 98 /* If we've already set this don't bother to do it again. */ 99 if (mp_ncpus != 0) 100 return; 101 102 hwcpu = 2; 103 104 ncpu = hwcpu; 105 TUNABLE_INT_FETCH("hw.ncpu", &ncpu); 106 if (ncpu < 1 || ncpu > hwcpu) 107 ncpu = hwcpu; 108 109 mp_ncpus = ncpu; 110 mp_maxid = ncpu - 1; 111 } 112 113 static void 114 _socfpga_mp_start_ap(uint32_t platid) 115 { 116 bus_space_handle_t scu, rst, ram; 117 int reg; 118 119 switch (platid) { 120 #if defined(SOC_ALTERA_ARRIA10) 121 case SOCFPGA_ARRIA10: 122 if (bus_space_map(fdtbus_bs_tag, SCU_PHYSBASE_A10, 123 SCU_SIZE, 0, &scu) != 0) 124 panic("Couldn't map the SCU\n"); 125 break; 126 #endif 127 #if defined(SOC_ALTERA_CYCLONE5) 128 case SOCFPGA_CYCLONE5: 129 if (bus_space_map(fdtbus_bs_tag, SCU_PHYSBASE, 130 SCU_SIZE, 0, &scu) != 0) 131 panic("Couldn't map the SCU\n"); 132 break; 133 #endif 134 default: 135 panic("Unknown platform id %d\n", platid); 136 } 137 138 if (bus_space_map(fdtbus_bs_tag, RSTMGR_PHYSBASE, 139 RSTMGR_SIZE, 0, &rst) != 0) 140 panic("Couldn't map the reset manager (RSTMGR)\n"); 141 if (bus_space_map(fdtbus_bs_tag, RAM_PHYSBASE, 142 RAM_SIZE, 0, &ram) != 0) 143 panic("Couldn't map the first physram page\n"); 144 145 /* Invalidate SCU cache tags */ 146 bus_space_write_4(fdtbus_bs_tag, scu, 147 SCU_INV_TAGS_REG, 0x0000ffff); 148 149 /* 150 * Erratum ARM/MP: 764369 (problems with cache maintenance). 151 * Setting the "disable-migratory bit" in the undocumented SCU 152 * Diagnostic Control Register helps work around the problem. 153 */ 154 reg = bus_space_read_4(fdtbus_bs_tag, scu, SCU_DIAG_CONTROL); 155 reg |= (SCU_DIAG_DISABLE_MIGBIT); 156 bus_space_write_4(fdtbus_bs_tag, scu, SCU_DIAG_CONTROL, reg); 157 158 /* Put CPU1 to reset state */ 159 switch (platid) { 160 #if defined(SOC_ALTERA_ARRIA10) 161 case SOCFPGA_ARRIA10: 162 bus_space_write_4(fdtbus_bs_tag, rst, 163 RSTMGR_A10_MPUMODRST, MPUMODRST_CPU1); 164 break; 165 #endif 166 #if defined(SOC_ALTERA_CYCLONE5) 167 case SOCFPGA_CYCLONE5: 168 bus_space_write_4(fdtbus_bs_tag, rst, 169 RSTMGR_MPUMODRST, MPUMODRST_CPU1); 170 break; 171 #endif 172 default: 173 panic("Unknown platform id %d\n", platid); 174 } 175 176 /* Enable the SCU, then clean the cache on this core */ 177 reg = bus_space_read_4(fdtbus_bs_tag, scu, SCU_CONTROL_REG); 178 reg |= (SCU_CONTROL_ENABLE); 179 bus_space_write_4(fdtbus_bs_tag, scu, SCU_CONTROL_REG, reg); 180 181 /* Set up trampoline code */ 182 mpentry_addr = (char *)pmap_kextract((vm_offset_t)mpentry); 183 bus_space_write_region_4(fdtbus_bs_tag, ram, 0, 184 (uint32_t *)&socfpga_trampoline, 8); 185 186 dcache_wbinv_poc_all(); 187 188 /* Put CPU1 out from reset */ 189 switch (platid) { 190 #if defined(SOC_ALTERA_ARRIA10) 191 case SOCFPGA_ARRIA10: 192 bus_space_write_4(fdtbus_bs_tag, rst, 193 RSTMGR_A10_MPUMODRST, 0); 194 break; 195 #endif 196 #if defined(SOC_ALTERA_CYCLONE5) 197 case SOCFPGA_CYCLONE5: 198 bus_space_write_4(fdtbus_bs_tag, rst, 199 RSTMGR_MPUMODRST, 0); 200 break; 201 #endif 202 default: 203 panic("Unknown platform id %d\n", platid); 204 } 205 206 dsb(); 207 sev(); 208 209 bus_space_unmap(fdtbus_bs_tag, scu, SCU_SIZE); 210 bus_space_unmap(fdtbus_bs_tag, rst, RSTMGR_SIZE); 211 bus_space_unmap(fdtbus_bs_tag, ram, RAM_SIZE); 212 } 213 214 #if defined(SOC_ALTERA_ARRIA10) 215 void 216 socfpga_a10_mp_start_ap(platform_t plat) 217 { 218 219 _socfpga_mp_start_ap(SOCFPGA_ARRIA10); 220 } 221 #endif 222 223 #if defined(SOC_ALTERA_CYCLONE5) 224 void 225 socfpga_mp_start_ap(platform_t plat) 226 { 227 228 _socfpga_mp_start_ap(SOCFPGA_CYCLONE5); 229 } 230 #endif 231