1/* $NetBSD: cpufunc_asm.S,v 1.12 2003/09/06 09:14:52 rearnsha Exp $ */ 2 3/*- 4 * Copyright (c) 1997,1998 Mark Brinicombe. 5 * Copyright (c) 1997 Causality Limited 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Causality Limited. 19 * 4. The name of Causality Limited may not be used to endorse or promote 20 * products derived from this software without specific prior written 21 * permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY CAUSALITY LIMITED ``AS IS'' AND ANY EXPRESS 24 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 26 * DISCLAIMED. IN NO EVENT SHALL CAUSALITY LIMITED BE LIABLE FOR ANY DIRECT, 27 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 29 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 * 35 * RiscBSD kernel project 36 * 37 * cpufunc.S 38 * 39 * Assembly functions for CPU / MMU / TLB specific operations 40 * 41 * Created : 30/01/97 42 * 43 */ 44 45#include <machine/asm.h> 46__FBSDID("$FreeBSD$"); 47 48 .text 49 .align 2 50 51ENTRY(cpufunc_nullop) 52 RET 53END(cpufunc_nullop) 54 55/* 56 * Generic functions to write the internal coprocessor registers 57 * 58 * Currently these registers are 59 * c1 - CPU Control 60 * c3 - Domain Access Control 61 * 62 * All other registers are CPU architecture specific 63 */ 64 65ENTRY(cpu_domains) 66 mcr p15, 0, r0, c3, c0, 0 67 RET 68END(cpu_domains) 69 70/* 71 * Generic functions to read/modify/write the internal coprocessor registers 72 * 73 * 74 * Currently these registers are 75 * c1 - CPU Control 76 * 77 * All other registers are CPU architecture specific 78 */ 79 80ENTRY(cpufunc_control) 81 mrc CP15_SCTLR(r3) /* Read the control register */ 82 bic r2, r3, r0 /* Clear bits */ 83 eor r2, r2, r1 /* XOR bits */ 84 85 86 teq r2, r3 /* Only write if there is a change */ 87 mcrne CP15_SCTLR(r2) /* Write new control register */ 88 mov r0, r3 /* Return old value */ 89 90 RET 91END(cpufunc_control) 92 93/* 94 * other potentially useful software functions are: 95 * clean D cache entry and flush I cache entry 96 * for the moment use cache_purgeID_E 97 */ 98 99/* Random odd functions */ 100 101/* Allocate and lock a cacheline for the specified address. */ 102 103#define CPWAIT_BRANCH \ 104 sub pc, pc, #4 105#define CPWAIT() \ 106 mrc p15, 0, r2, c2, c0, 0; \ 107 mov r2, r2; \ 108 CPWAIT_BRANCH 109 110ENTRY(arm_lock_cache_line) 111 mcr p15, 0, r0, c7, c10, 4 /* Drain write buffer */ 112 mov r1, #1 113 mcr p15, 0, r1, c9, c2, 0 /* Enable data cache lock mode */ 114 CPWAIT() 115 mcr p15, 0, r0, c7, c2, 5 /* Allocate the cache line */ 116 mcr p15, 0, r0, c7, c10, 4 /* Drain write buffer */ 117 mov r1, #0 118 str r1, [r0] 119 mcr p15, 0, r0, c7, c10, 4 /* Drain write buffer */ 120 mcr p15, 0, r1, c9, c2, 0 /* Disable data cache lock mode */ 121 CPWAIT() 122 RET 123END(arm_lock_cache_line) 124 125