1/*- 2 * Copyright (C) 2011 MARVELL INTERNATIONAL LTD. 3 * All rights reserved. 4 * 5 * Developed by Semihalf. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. Neither the name of MARVELL nor the names of contributors 16 * may be used to endorse or promote products derived from this software 17 * without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 */ 31 32#include <machine/asm.h> 33#include <machine/param.h> 34 35.Lpj4b_sf_ctrl_reg: 36 .word 0xf1021820 37 38ENTRY(pj4b_config) 39 40 /* Set Auxiliary Debug Modes Control 0 register */ 41 mrc p15, 1, r0, c15, c1, 0 42 /* ARMADAXP errata fix: ARM-CPU-6136 */ 43 bic r0, r0, #(1 << 12) /* LDSTM first issue is single word */ 44 45 orr r0, r0, #(1 << 22) /* DVM_WAKEUP disable */ 46 mcr p15, 1, r0, c15, c1, 0 47 48 /* Set Auxiliary Debug Modes Control 1 register */ 49 mrc p15, 1, r0, c15, c1, 1 50 /* ARMADAXP errata fix: ARM-CPU-6409 */ 51 bic r0, r0, #(1 << 2) /* Disable static branch prediction */ 52 53 orr r0, r0, #(1 << 5) /* STREX backoff disable */ 54 orr r0, r0, #(1 << 8) /* Internal parity handling disable */ 55 orr r0, r0, #(1 << 16) /* Disable data transfer for clean line */ 56 mcr p15, 1, r0, c15, c1, 1 57 58 /* Set Auxiliary Function Modes Control 0 register */ 59 mrc p15, 1, r0, c15, c2, 0 60#if defined(SMP) 61 orr r0, r0, #(1 << 1) /* SMP/nAMP enabled (coherency) */ 62#endif 63 orr r0, r0, #(1 << 2) /* L1 parite enable */ 64 orr r0, r0, #(1 << 8) /* Cache and TLB maintenance broadcast enable */ 65 mcr p15, 1, r0, c15, c2, 0 66 67 /* Set Auxiliary Debug Modes Control 2 register */ 68 mrc p15, 1, r0, c15, c1, 2 69 bic r0, r0, #(1 << 23) /* Enable fast LDR */ 70 orr r0, r0, #(1 << 25) /* Intervention Interleave disable */ 71 orr r0, r0, #(1 << 27) /* Critical word first sequencing disable */ 72 orr r0, r0, #(1 << 29) /* Disable MO device read / write */ 73 orr r0, r0, #(1 << 30) /* L1 cache strict round-robin replacement policy*/ 74 orr r0, r0, #(1 << 31) /* Enable write evict */ 75 mcr p15, 1, r0, c15, c1, 2 76#if defined(SMP) 77 /* Set SMP mode in Auxiliary Control Register */ 78 mrc p15, 0, r0, c1, c0, 1 79 orr r0, r0, #(1 << 5) 80 mcr p15, 0, r0, c1, c0, 1 81#endif 82 83 /* Load CPU number */ 84 mrc p15, 0, r0, c0, c0, 5 85 and r0, r0, #0xf 86 87 /* SF Enable and invalidate */ 88 ldr r1, .Lpj4b_sf_ctrl_reg 89 ldr r2, [r1, r0, lsl #8] 90 orr r2, r2, #(1 << 0) 91 bic r2, r2, #(1 << 8) 92 str r2, [r1, r0, lsl #8] 93 94 RET 95END(pj4b_config) 96 97