12b71562fSIan Lepore /*- 22b71562fSIan Lepore * Copyright 2014 Svatopluk Kraus <onwahe@gmail.com> 32b71562fSIan Lepore * Copyright 2014 Michal Meloun <meloun@miracle.cz> 42b71562fSIan Lepore * All rights reserved. 52b71562fSIan Lepore * 62b71562fSIan Lepore * Redistribution and use in source and binary forms, with or without 72b71562fSIan Lepore * modification, are permitted provided that the following conditions 82b71562fSIan Lepore * are met: 92b71562fSIan Lepore * 1. Redistributions of source code must retain the above copyright 102b71562fSIan Lepore * notice, this list of conditions and the following disclaimer. 112b71562fSIan Lepore * 2. Redistributions in binary form must reproduce the above copyright 122b71562fSIan Lepore * notice, this list of conditions and the following disclaimer in the 132b71562fSIan Lepore * documentation and/or other materials provided with the distribution. 142b71562fSIan Lepore * 152b71562fSIan Lepore * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 162b71562fSIan Lepore * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 172b71562fSIan Lepore * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 182b71562fSIan Lepore * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 192b71562fSIan Lepore * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 202b71562fSIan Lepore * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 212b71562fSIan Lepore * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 222b71562fSIan Lepore * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 232b71562fSIan Lepore * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 242b71562fSIan Lepore * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 252b71562fSIan Lepore * SUCH DAMAGE. 262b71562fSIan Lepore */ 272b71562fSIan Lepore 282b71562fSIan Lepore #include <sys/cdefs.h> 292b71562fSIan Lepore __FBSDID("$FreeBSD$"); 302b71562fSIan Lepore 312b71562fSIan Lepore #include <sys/param.h> 322b71562fSIan Lepore #include <sys/systm.h> 332b71562fSIan Lepore 342b71562fSIan Lepore #include <machine/cpuinfo.h> 352b71562fSIan Lepore #include <machine/cpu-v6.h> 362b71562fSIan Lepore 372b71562fSIan Lepore struct cpuinfo cpuinfo; 382b71562fSIan Lepore 392b71562fSIan Lepore /* Read and parse CPU id scheme */ 402b71562fSIan Lepore void 412b71562fSIan Lepore cpuinfo_init(void) 422b71562fSIan Lepore { 432b71562fSIan Lepore 442b71562fSIan Lepore cpuinfo.midr = cp15_midr_get(); 452b71562fSIan Lepore /* Test old version id schemes first */ 462b71562fSIan Lepore if ((cpuinfo.midr & CPU_ID_IMPLEMENTOR_MASK) == CPU_ID_ARM_LTD) { 472b71562fSIan Lepore if (CPU_ID_ISOLD(cpuinfo.midr)) { 482b71562fSIan Lepore /* obsolete ARMv2 or ARMv3 CPU */ 492b71562fSIan Lepore cpuinfo.midr = 0; 502b71562fSIan Lepore return; 512b71562fSIan Lepore } 522b71562fSIan Lepore if (CPU_ID_IS7(cpuinfo.midr)) { 532b71562fSIan Lepore if ((cpuinfo.midr & (1 << 23)) == 0) { 542b71562fSIan Lepore /* obsolete ARMv3 CPU */ 552b71562fSIan Lepore cpuinfo.midr = 0; 562b71562fSIan Lepore return; 572b71562fSIan Lepore } 582b71562fSIan Lepore /* ARMv4T CPU */ 592b71562fSIan Lepore cpuinfo.architecture = 1; 602b71562fSIan Lepore cpuinfo.revision = (cpuinfo.midr >> 16) & 0x7F; 612b71562fSIan Lepore } 622b71562fSIan Lepore } else { 632b71562fSIan Lepore /* must be new id scheme */ 642b71562fSIan Lepore cpuinfo.architecture = (cpuinfo.midr >> 16) & 0x0F; 652b71562fSIan Lepore cpuinfo.revision = (cpuinfo.midr >> 20) & 0x0F; 662b71562fSIan Lepore } 672b71562fSIan Lepore /* Parse rest of MIDR */ 682b71562fSIan Lepore cpuinfo.implementer = (cpuinfo.midr >> 24) & 0xFF; 692b71562fSIan Lepore cpuinfo.part_number = (cpuinfo.midr >> 4) & 0xFFF; 702b71562fSIan Lepore cpuinfo.patch = cpuinfo.midr & 0x0F; 712b71562fSIan Lepore 722b71562fSIan Lepore /* CP15 c0,c0 regs 0-7 exist on all CPUs (although aliased with MIDR) */ 732b71562fSIan Lepore cpuinfo.ctr = cp15_ctr_get(); 742b71562fSIan Lepore cpuinfo.tcmtr = cp15_tcmtr_get(); 752b71562fSIan Lepore cpuinfo.tlbtr = cp15_tlbtr_get(); 762b71562fSIan Lepore cpuinfo.mpidr = cp15_mpidr_get(); 772b71562fSIan Lepore cpuinfo.revidr = cp15_revidr_get(); 782b71562fSIan Lepore 792b71562fSIan Lepore /* if CPU is not v7 cpu id scheme */ 802b71562fSIan Lepore if (cpuinfo.architecture != 0xF) 812b71562fSIan Lepore return; 822b71562fSIan Lepore 832b71562fSIan Lepore cpuinfo.id_pfr0 = cp15_id_pfr0_get(); 842b71562fSIan Lepore cpuinfo.id_pfr1 = cp15_id_pfr1_get(); 852b71562fSIan Lepore cpuinfo.id_dfr0 = cp15_id_dfr0_get(); 862b71562fSIan Lepore cpuinfo.id_afr0 = cp15_id_afr0_get(); 872b71562fSIan Lepore cpuinfo.id_mmfr0 = cp15_id_mmfr0_get(); 882b71562fSIan Lepore cpuinfo.id_mmfr1 = cp15_id_mmfr1_get(); 892b71562fSIan Lepore cpuinfo.id_mmfr2 = cp15_id_mmfr2_get(); 902b71562fSIan Lepore cpuinfo.id_mmfr3 = cp15_id_mmfr3_get(); 912b71562fSIan Lepore cpuinfo.id_isar0 = cp15_id_isar0_get(); 922b71562fSIan Lepore cpuinfo.id_isar1 = cp15_id_isar1_get(); 932b71562fSIan Lepore cpuinfo.id_isar2 = cp15_id_isar2_get(); 942b71562fSIan Lepore cpuinfo.id_isar3 = cp15_id_isar3_get(); 952b71562fSIan Lepore cpuinfo.id_isar4 = cp15_id_isar4_get(); 962b71562fSIan Lepore cpuinfo.id_isar5 = cp15_id_isar5_get(); 972b71562fSIan Lepore 982b71562fSIan Lepore /* Not yet - CBAR only exist on ARM SMP Cortex A CPUs 992b71562fSIan Lepore cpuinfo.cbar = cp15_cbar_get(); 1002b71562fSIan Lepore */ 1012b71562fSIan Lepore 1022b71562fSIan Lepore /* Test if revidr is implemented */ 1032b71562fSIan Lepore if (cpuinfo.revidr == cpuinfo.midr) 1042b71562fSIan Lepore cpuinfo.revidr = 0; 1052b71562fSIan Lepore 1062b71562fSIan Lepore /* parsed bits of above registers */ 1072b71562fSIan Lepore /* id_mmfr0 */ 1082b71562fSIan Lepore cpuinfo.outermost_shareability = (cpuinfo.id_mmfr0 >> 8) & 0xF; 1092b71562fSIan Lepore cpuinfo.shareability_levels = (cpuinfo.id_mmfr0 >> 12) & 0xF; 1102b71562fSIan Lepore cpuinfo.auxiliary_registers = (cpuinfo.id_mmfr0 >> 20) & 0xF; 1112b71562fSIan Lepore cpuinfo.innermost_shareability = (cpuinfo.id_mmfr0 >> 28) & 0xF; 1122b71562fSIan Lepore /* id_mmfr2 */ 1132b71562fSIan Lepore cpuinfo.mem_barrier = (cpuinfo.id_mmfr2 >> 20) & 0xF; 1142b71562fSIan Lepore /* id_mmfr3 */ 1152b71562fSIan Lepore cpuinfo.coherent_walk = (cpuinfo.id_mmfr3 >> 20) & 0xF; 1162b71562fSIan Lepore cpuinfo.maintenance_broadcast =(cpuinfo.id_mmfr3 >> 12) & 0xF; 1172b71562fSIan Lepore /* id_pfr1 */ 1182b71562fSIan Lepore cpuinfo.generic_timer_ext = (cpuinfo.id_pfr1 >> 16) & 0xF; 1192b71562fSIan Lepore cpuinfo.virtualization_ext = (cpuinfo.id_pfr1 >> 12) & 0xF; 1202b71562fSIan Lepore cpuinfo.security_ext = (cpuinfo.id_pfr1 >> 4) & 0xF; 1212b71562fSIan Lepore } 122