1 /*- 2 * Copyright 2014 Svatopluk Kraus <onwahe@gmail.com> 3 * Copyright 2014 Michal Meloun <meloun@miracle.cz> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 #include <sys/param.h> 32 #include <sys/systm.h> 33 34 #include <machine/cpuinfo.h> 35 #include <machine/cpu-v6.h> 36 37 struct cpuinfo cpuinfo; 38 39 /* Read and parse CPU id scheme */ 40 void 41 cpuinfo_init(void) 42 { 43 44 cpuinfo.midr = cp15_midr_get(); 45 /* Test old version id schemes first */ 46 if ((cpuinfo.midr & CPU_ID_IMPLEMENTOR_MASK) == CPU_ID_ARM_LTD) { 47 if (CPU_ID_ISOLD(cpuinfo.midr)) { 48 /* obsolete ARMv2 or ARMv3 CPU */ 49 cpuinfo.midr = 0; 50 return; 51 } 52 if (CPU_ID_IS7(cpuinfo.midr)) { 53 if ((cpuinfo.midr & (1 << 23)) == 0) { 54 /* obsolete ARMv3 CPU */ 55 cpuinfo.midr = 0; 56 return; 57 } 58 /* ARMv4T CPU */ 59 cpuinfo.architecture = 1; 60 cpuinfo.revision = (cpuinfo.midr >> 16) & 0x7F; 61 } else { 62 /* ARM new id scheme */ 63 cpuinfo.architecture = (cpuinfo.midr >> 16) & 0x0F; 64 cpuinfo.revision = (cpuinfo.midr >> 20) & 0x0F; 65 } 66 } else { 67 /* non ARM -> must be new id scheme */ 68 cpuinfo.architecture = (cpuinfo.midr >> 16) & 0x0F; 69 cpuinfo.revision = (cpuinfo.midr >> 20) & 0x0F; 70 } 71 /* Parse rest of MIDR */ 72 cpuinfo.implementer = (cpuinfo.midr >> 24) & 0xFF; 73 cpuinfo.part_number = (cpuinfo.midr >> 4) & 0xFFF; 74 cpuinfo.patch = cpuinfo.midr & 0x0F; 75 76 /* CP15 c0,c0 regs 0-7 exist on all CPUs (although aliased with MIDR) */ 77 cpuinfo.ctr = cp15_ctr_get(); 78 cpuinfo.tcmtr = cp15_tcmtr_get(); 79 cpuinfo.tlbtr = cp15_tlbtr_get(); 80 cpuinfo.mpidr = cp15_mpidr_get(); 81 cpuinfo.revidr = cp15_revidr_get(); 82 83 /* if CPU is not v7 cpu id scheme */ 84 if (cpuinfo.architecture != 0xF) 85 return; 86 87 cpuinfo.id_pfr0 = cp15_id_pfr0_get(); 88 cpuinfo.id_pfr1 = cp15_id_pfr1_get(); 89 cpuinfo.id_dfr0 = cp15_id_dfr0_get(); 90 cpuinfo.id_afr0 = cp15_id_afr0_get(); 91 cpuinfo.id_mmfr0 = cp15_id_mmfr0_get(); 92 cpuinfo.id_mmfr1 = cp15_id_mmfr1_get(); 93 cpuinfo.id_mmfr2 = cp15_id_mmfr2_get(); 94 cpuinfo.id_mmfr3 = cp15_id_mmfr3_get(); 95 cpuinfo.id_isar0 = cp15_id_isar0_get(); 96 cpuinfo.id_isar1 = cp15_id_isar1_get(); 97 cpuinfo.id_isar2 = cp15_id_isar2_get(); 98 cpuinfo.id_isar3 = cp15_id_isar3_get(); 99 cpuinfo.id_isar4 = cp15_id_isar4_get(); 100 cpuinfo.id_isar5 = cp15_id_isar5_get(); 101 102 /* Not yet - CBAR only exist on ARM SMP Cortex A CPUs 103 cpuinfo.cbar = cp15_cbar_get(); 104 */ 105 106 /* Test if revidr is implemented */ 107 if (cpuinfo.revidr == cpuinfo.midr) 108 cpuinfo.revidr = 0; 109 110 /* parsed bits of above registers */ 111 /* id_mmfr0 */ 112 cpuinfo.outermost_shareability = (cpuinfo.id_mmfr0 >> 8) & 0xF; 113 cpuinfo.shareability_levels = (cpuinfo.id_mmfr0 >> 12) & 0xF; 114 cpuinfo.auxiliary_registers = (cpuinfo.id_mmfr0 >> 20) & 0xF; 115 cpuinfo.innermost_shareability = (cpuinfo.id_mmfr0 >> 28) & 0xF; 116 /* id_mmfr2 */ 117 cpuinfo.mem_barrier = (cpuinfo.id_mmfr2 >> 20) & 0xF; 118 /* id_mmfr3 */ 119 cpuinfo.coherent_walk = (cpuinfo.id_mmfr3 >> 20) & 0xF; 120 cpuinfo.maintenance_broadcast =(cpuinfo.id_mmfr3 >> 12) & 0xF; 121 /* id_pfr1 */ 122 cpuinfo.generic_timer_ext = (cpuinfo.id_pfr1 >> 16) & 0xF; 123 cpuinfo.virtualization_ext = (cpuinfo.id_pfr1 >> 12) & 0xF; 124 cpuinfo.security_ext = (cpuinfo.id_pfr1 >> 4) & 0xF; 125 } 126