1/* $NetBSD: exception.S,v 1.13 2003/10/31 16:30:15 scw Exp $ */ 2 3/*- 4 * Copyright (c) 1994-1997 Mark Brinicombe. 5 * Copyright (c) 1994 Brini. 6 * All rights reserved. 7 * 8 * This code is derived from software written for Brini by Mark Brinicombe 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by Brini. 21 * 4. The name of the company nor the name of the author may be used to 22 * endorse or promote products derived from this software without specific 23 * prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED 26 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 27 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 28 * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 29 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 30 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 31 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 35 * SUCH DAMAGE. 36 * 37 * RiscBSD kernel project 38 * 39 * exception.S 40 * 41 * Low level handlers for exception vectors 42 * 43 * Created : 24/09/94 44 * 45 * Based on kate/display/abort.s 46 * 47 */ 48 49#include "assym.s" 50 51#include "opt_kdtrace.h" 52#include <machine/asm.h> 53#include <machine/armreg.h> 54#include <machine/asmacros.h> 55__FBSDID("$FreeBSD$"); 56 57#ifdef KDTRACE_HOOKS 58 .bss 59 .align 4 60 .global _C_LABEL(dtrace_invop_calltrap_addr) 61_C_LABEL(dtrace_invop_calltrap_addr): 62 .word 0 63 .word 0 64#endif 65 66 .text 67 .align 2 68 69/* 70 * ASM macros for pushing and pulling trapframes from the stack 71 * 72 * These macros are used to handle the irqframe and trapframe structures 73 * defined above. 74 */ 75 76/* 77 * PUSHFRAME - macro to push a trap frame on the stack in the current mode 78 * Since the current mode is used, the SVC lr field is not defined. 79 * 80 * NOTE: r13 and r14 are stored separately as a work around for the 81 * SA110 rev 2 STM^ bug 82 */ 83#ifdef ARM_TP_ADDRESS 84#define PUSHFRAME \ 85 sub sp, sp, #4; /* Align the stack */ \ 86 str lr, [sp, #-4]!; /* Push the return address */ \ 87 sub sp, sp, #(4*17); /* Adjust the stack pointer */ \ 88 stmia sp, {r0-r12}; /* Push the user mode registers */ \ 89 add r0, sp, #(4*13); /* Adjust the stack pointer */ \ 90 stmia r0, {r13-r14}^; /* Push the user mode registers */ \ 91 mov r0, r0; /* NOP for previous instruction */ \ 92 mrs r0, spsr; /* Put the SPSR on the stack */ \ 93 str r0, [sp, #-4]!; \ 94 ldr r0, =ARM_RAS_START; \ 95 mov r1, #0; \ 96 str r1, [r0]; \ 97 mov r1, #0xffffffff; \ 98 str r1, [r0, #4]; 99#else 100#define PUSHFRAME \ 101 sub sp, sp, #4; /* Align the stack */ \ 102 str lr, [sp, #-4]!; /* Push the return address */ \ 103 sub sp, sp, #(4*17); /* Adjust the stack pointer */ \ 104 stmia sp, {r0-r12}; /* Push the user mode registers */ \ 105 add r0, sp, #(4*13); /* Adjust the stack pointer */ \ 106 stmia r0, {r13-r14}^; /* Push the user mode registers */ \ 107 mov r0, r0; /* NOP for previous instruction */ \ 108 mrs r0, spsr; /* Put the SPSR on the stack */ \ 109 str r0, [sp, #-4]!; 110#endif 111 112/* 113 * PULLFRAME - macro to pull a trap frame from the stack in the current mode 114 * Since the current mode is used, the SVC lr field is ignored. 115 */ 116 117#ifdef ARM_TP_ADDRESS 118#define PULLFRAME \ 119 ldr r0, [sp], #4; /* Get the SPSR from stack */ \ 120 msr spsr_fsxc, r0; \ 121 ldmia sp, {r0-r14}^; /* Restore registers (usr mode) */ \ 122 mov r0, r0; /* NOP for previous instruction */ \ 123 add sp, sp, #(4*17); /* Adjust the stack pointer */ \ 124 ldr lr, [sp], #4; /* Pull the return address */ \ 125 add sp, sp, #4 /* Align the stack */ 126#else 127#define PULLFRAME \ 128 ldr r0, [sp], #4 ; /* Get the SPSR from stack */ \ 129 msr spsr_fsxc, r0; \ 130 clrex; \ 131 ldmia sp, {r0-r14}^; /* Restore registers (usr mode) */ \ 132 mov r0, r0; /* NOP for previous instruction */ \ 133 add sp, sp, #(4*17); /* Adjust the stack pointer */ \ 134 ldr lr, [sp], #4; /* Pull the return address */ \ 135 add sp, sp, #4 /* Align the stack */ 136#endif 137 138/* 139 * PUSHFRAMEINSVC - macro to push a trap frame on the stack in SVC32 mode 140 * This should only be used if the processor is not currently in SVC32 141 * mode. The processor mode is switched to SVC mode and the trap frame is 142 * stored. The SVC lr field is used to store the previous value of 143 * lr in SVC mode. 144 * 145 * NOTE: r13 and r14 are stored separately as a work around for the 146 * SA110 rev 2 STM^ bug 147 */ 148#ifdef ARM_TP_ADDRESS 149#define PUSHFRAMEINSVC \ 150 stmdb sp, {r0-r3}; /* Save 4 registers */ \ 151 mov r0, lr; /* Save xxx32 r14 */ \ 152 mov r1, sp; /* Save xxx32 sp */ \ 153 mrs r3, spsr; /* Save xxx32 spsr */ \ 154 mrs r2, cpsr; /* Get the CPSR */ \ 155 bic r2, r2, #(PSR_MODE); /* Fix for SVC mode */ \ 156 orr r2, r2, #(PSR_SVC32_MODE); \ 157 msr cpsr_c, r2; /* Punch into SVC mode */ \ 158 mov r2, sp; /* Save SVC sp */ \ 159 bic sp, sp, #7; /* Align sp to an 8-byte addrress */ \ 160 sub sp, sp, #(4 * 17); /* Pad trapframe to keep alignment */ \ 161 /* and for dtrace to emulate push/pop */ \ 162 str r0, [sp, #-4]!; /* Push return address */ \ 163 str lr, [sp, #-4]!; /* Push SVC lr */ \ 164 str r2, [sp, #-4]!; /* Push SVC sp */ \ 165 msr spsr_fsxc, r3; /* Restore correct spsr */ \ 166 ldmdb r1, {r0-r3}; /* Restore 4 regs from xxx mode */ \ 167 sub sp, sp, #(4*15); /* Adjust the stack pointer */ \ 168 stmia sp, {r0-r12}; /* Push the user mode registers */ \ 169 add r0, sp, #(4*13); /* Adjust the stack pointer */ \ 170 stmia r0, {r13-r14}^; /* Push the user mode registers */ \ 171 mov r0, r0; /* NOP for previous instruction */ \ 172 ldr r5, =ARM_RAS_START; /* Check if there's any RAS */ \ 173 ldr r4, [r5, #4]; /* reset it to point at the */ \ 174 cmp r4, #0xffffffff; /* end of memory if necessary; */ \ 175 movne r1, #0xffffffff; /* leave value in r4 for later */ \ 176 strne r1, [r5, #4]; /* comparision against PC. */ \ 177 ldr r3, [r5]; /* Retrieve global RAS_START */ \ 178 cmp r3, #0; /* and reset it if non-zero. */ \ 179 movne r1, #0; /* If non-zero RAS_START and */ \ 180 strne r1, [r5]; /* PC was lower than RAS_END, */ \ 181 ldrne r1, [r0, #16]; /* adjust the saved PC so that */ \ 182 cmpne r4, r1; /* execution later resumes at */ \ 183 strhi r3, [r0, #16]; /* the RAS_START location. */ \ 184 mrs r0, spsr; \ 185 str r0, [sp, #-4]! 186#else 187#define PUSHFRAMEINSVC \ 188 stmdb sp, {r0-r3}; /* Save 4 registers */ \ 189 mov r0, lr; /* Save xxx32 r14 */ \ 190 mov r1, sp; /* Save xxx32 sp */ \ 191 mrs r3, spsr; /* Save xxx32 spsr */ \ 192 mrs r2, cpsr; /* Get the CPSR */ \ 193 bic r2, r2, #(PSR_MODE); /* Fix for SVC mode */ \ 194 orr r2, r2, #(PSR_SVC32_MODE); \ 195 msr cpsr_c, r2; /* Punch into SVC mode */ \ 196 mov r2, sp; /* Save SVC sp */ \ 197 bic sp, sp, #7; /* Align sp to an 8-byte addrress */ \ 198 sub sp, sp, #(4 * 17); /* Pad trapframe to keep alignment */ \ 199 /* and for dtrace to emulate push/pop */ \ 200 str r0, [sp, #-4]!; /* Push return address */ \ 201 str lr, [sp, #-4]!; /* Push SVC lr */ \ 202 str r2, [sp, #-4]!; /* Push SVC sp */ \ 203 msr spsr_fsxc, r3; /* Restore correct spsr */ \ 204 ldmdb r1, {r0-r3}; /* Restore 4 regs from xxx mode */ \ 205 sub sp, sp, #(4*15); /* Adjust the stack pointer */ \ 206 stmia sp, {r0-r12}; /* Push the user mode registers */ \ 207 add r0, sp, #(4*13); /* Adjust the stack pointer */ \ 208 stmia r0, {r13-r14}^; /* Push the user mode registers */ \ 209 mov r0, r0; /* NOP for previous instruction */ \ 210 mrs r0, spsr; /* Put the SPSR on the stack */ \ 211 str r0, [sp, #-4]! 212#endif 213 214/* 215 * PULLFRAMEFROMSVCANDEXIT - macro to pull a trap frame from the stack 216 * in SVC32 mode and restore the saved processor mode and PC. 217 * This should be used when the SVC lr register needs to be restored on 218 * exit. 219 */ 220 221#ifdef ARM_TP_ADDRESS 222#define PULLFRAMEFROMSVCANDEXIT \ 223 ldr r0, [sp], #4; /* Get the SPSR from stack */ \ 224 msr spsr_fsxc, r0; /* restore SPSR */ \ 225 ldmia sp, {r0-r14}^; /* Restore registers (usr mode) */ \ 226 mov r0, r0; /* NOP for previous instruction */ \ 227 add sp, sp, #(4*15); /* Adjust the stack pointer */ \ 228 ldmia sp, {sp, lr, pc}^ /* Restore lr and exit */ 229#else 230#define PULLFRAMEFROMSVCANDEXIT \ 231 ldr r0, [sp], #4; /* Get the SPSR from stack */ \ 232 msr spsr_fsxc, r0; /* restore SPSR */ \ 233 clrex; \ 234 ldmia sp, {r0-r14}^; /* Restore registers (usr mode) */ \ 235 mov r0, r0; /* NOP for previous instruction */ \ 236 add sp, sp, #(4*15); /* Adjust the stack pointer */ \ 237 ldmia sp, {sp, lr, pc}^ /* Restore lr and exit */ 238#endif 239 240#if defined(__ARM_EABI__) 241/* 242 * Unwind hints so we can unwind past functions that use 243 * PULLFRAMEFROMSVCANDEXIT. They are run in reverse order. 244 * As the last thing we do is restore the stack pointer 245 * we can ignore the padding at the end of struct trapframe. 246 */ 247#define UNWINDSVCFRAME \ 248 .save {r13-r15}; /* Restore sp, lr, pc */ \ 249 .pad #(2*4); /* Skip user sp and lr */ \ 250 .save {r0-r12}; /* Restore r0-r12 */ \ 251 .pad #(4) /* Skip spsr */ 252#else 253#define UNWINDSVCFRAME 254#endif 255 256#define DO_AST \ 257 ldr r0, [sp]; /* Get the SPSR from stack */ \ 258 mrs r4, cpsr; /* save CPSR */ \ 259 orr r1, r4, #(PSR_I|PSR_F); \ 260 msr cpsr_c, r1; /* Disable interrupts */ \ 261 and r0, r0, #(PSR_MODE); /* Returning to USR mode? */ \ 262 teq r0, #(PSR_USR32_MODE); \ 263 bne 2f; /* Nope, get out now */ \ 264 bic r4, r4, #(PSR_I|PSR_F); \ 2651: GET_CURTHREAD_PTR(r5); \ 266 ldr r1, [r5, #(TD_FLAGS)]; \ 267 and r1, r1, #(TDF_ASTPENDING|TDF_NEEDRESCHED); \ 268 teq r1, #0; \ 269 beq 2f; /* Nope. Just bail */ \ 270 msr cpsr_c, r4; /* Restore interrupts */ \ 271 mov r0, sp; \ 272 bl _C_LABEL(ast); /* ast(frame) */ \ 273 orr r0, r4, #(PSR_I|PSR_F); \ 274 msr cpsr_c, r0; \ 275 b 1b; \ 2762: 277 278 279/* 280 * Entry point for a Software Interrupt (SWI). 281 * 282 * The hardware switches to svc32 mode on a swi, so we're already on the 283 * right stack; just build a trapframe and call the handler. 284 */ 285ASENTRY_NP(swi_entry) 286 PUSHFRAME /* Build the trapframe on the */ 287 mov r0, sp /* scv32 stack, pass it to the */ 288 bl _C_LABEL(swi_handler) /* swi handler. */ 289 /* 290 * The fork_trampoline() code in swtch.S aranges for the MI fork_exit() 291 * to return to swi_exit here, to return to userland. The net effect is 292 * that a newly created thread appears to return from a SWI just like 293 * the parent thread that created it. 294 */ 295ASEENTRY_NP(swi_exit) 296 DO_AST /* Handle pending signals. */ 297 PULLFRAME /* Deallocate trapframe. */ 298 movs pc, lr /* Return to userland. */ 299 STOP_UNWINDING /* Don't unwind into user mode. */ 300EEND(swi_exit) 301END(swi_entry) 302 303/* 304 * Standard exception exit handler. 305 * 306 * This is used to return from all exceptions except SWI. It uses DO_AST and 307 * PULLFRAMEFROMSVCANDEXIT and can only be called if the exception entry code 308 * used PUSHFRAMEINSVC. 309 * 310 * If the return is to user mode, this uses DO_AST to deliver any pending 311 * signals and/or handle TDF_NEEDRESCHED first. 312 */ 313ASENTRY_NP(exception_exit) 314 DO_AST /* Handle pending signals. */ 315 PULLFRAMEFROMSVCANDEXIT /* Return. */ 316 UNWINDSVCFRAME /* Special unwinding for exceptions. */ 317END(exception_exit) 318 319/* 320 * Entry point for a Prefetch Abort exception. 321 * 322 * The hardware switches to the abort mode stack; we switch to svc32 before 323 * calling the handler, then return directly to the original mode/stack 324 * on exit (without transitioning back through the abort mode stack). 325 */ 326ASENTRY_NP(prefetch_abort_entry) 327#ifdef __XSCALE__ 328 nop /* Make absolutely sure any pending */ 329 nop /* imprecise aborts have occurred. */ 330#endif 331 sub lr, lr, #4 /* Adjust the lr. Transition to scv32 */ 332 PUSHFRAMEINSVC /* mode stack, build trapframe there. */ 333 adr lr, exception_exit /* Return from handler via standard */ 334 mov r0, sp /* exception exit routine. Pass the */ 335 mov r1, #1 /* Type flag */ 336 b _C_LABEL(abort_handler) 337END(prefetch_abort_entry) 338 339/* 340 * Entry point for a Data Abort exception. 341 * 342 * The hardware switches to the abort mode stack; we switch to svc32 before 343 * calling the handler, then return directly to the original mode/stack 344 * on exit (without transitioning back through the abort mode stack). 345 */ 346ASENTRY_NP(data_abort_entry) 347#ifdef __XSCALE__ 348 nop /* Make absolutely sure any pending */ 349 nop /* imprecise aborts have occurred. */ 350#endif 351 sub lr, lr, #8 /* Adjust the lr. Transition to scv32 */ 352 PUSHFRAMEINSVC /* mode stack, build trapframe there. */ 353 adr lr, exception_exit /* Exception exit routine */ 354 mov r0, sp /* Trapframe to the handler */ 355 mov r1, #0 /* Type flag */ 356 b _C_LABEL(abort_handler) 357END(data_abort_entry) 358 359/* 360 * Entry point for an Undefined Instruction exception. 361 * 362 * The hardware switches to the undefined mode stack; we switch to svc32 before 363 * calling the handler, then return directly to the original mode/stack 364 * on exit (without transitioning back through the undefined mode stack). 365 */ 366ASENTRY_NP(undefined_entry) 367 PUSHFRAMEINSVC /* mode stack, build trapframe there. */ 368 adr lr, exception_exit /* Return from handler via standard */ 369 mov r0, sp /* exception exit routine. Pass the */ 370 b undefinedinstruction /* trapframe to the handler. */ 371END(undefined_entry) 372 373/* 374 * Entry point for a normal IRQ. 375 * 376 * The hardware switches to the IRQ mode stack; we switch to svc32 before 377 * calling the handler, then return directly to the original mode/stack 378 * on exit (without transitioning back through the IRQ mode stack). 379 */ 380ASENTRY_NP(irq_entry) 381 sub lr, lr, #4 /* Adjust the lr. Transition to scv32 */ 382 PUSHFRAMEINSVC /* mode stack, build trapframe there. */ 383 adr lr, exception_exit /* Return from handler via standard */ 384 mov r0, sp /* exception exit routine. Pass the */ 385 b _C_LABEL(arm_irq_handler)/* trapframe to the handler. */ 386END(irq_entry) 387 388/* 389 * Entry point for an FIQ interrupt. 390 * 391 * We don't currently support FIQ handlers very much. Something can 392 * install itself in the FIQ vector using code (that may or may not work 393 * these days) in fiq.c. If nobody does that and an FIQ happens, this 394 * default handler just disables FIQs and otherwise ignores it. 395 */ 396ASENTRY_NP(fiq_entry) 397 mrs r8, cpsr /* FIQ handling isn't supported, */ 398 bic r8, #(PSR_F) /* just disable FIQ and return. */ 399 msr cpsr_c, r8 /* The r8 we trash here is the */ 400 subs pc, lr, #4 /* banked FIQ-mode r8. */ 401END(fiq_entry) 402 403/* 404 * Entry point for an Address Exception exception. 405 * This is an arm26 exception that should never happen. 406 */ 407ASENTRY_NP(addr_exception_entry) 408 mov r3, lr 409 mrs r2, spsr 410 mrs r1, cpsr 411 adr r0, Laddr_exception_msg 412 b _C_LABEL(panic) 413Laddr_exception_msg: 414 .asciz "Address Exception CPSR=0x%08x SPSR=0x%08x LR=0x%08x\n" 415 .balign 4 416END(addr_exception_entry) 417 418/* 419 * Entry point for the system Reset vector. 420 * This should never happen, so panic. 421 */ 422ASENTRY_NP(reset_entry) 423 mov r1, lr 424 adr r0, Lreset_panicmsg 425 b _C_LABEL(panic) 426 /* NOTREACHED */ 427Lreset_panicmsg: 428 .asciz "Reset vector called, LR = 0x%08x" 429 .balign 4 430END(reset_entry) 431 432/* 433 * page0 and page0_data -- An image of the ARM vectors which is copied to 434 * the ARM vectors page (high or low) as part of CPU initialization. The 435 * code that does the copy assumes that page0_data holds one 32-bit word 436 * of data for each of the predefined ARM vectors. It also assumes that 437 * page0_data follows the vectors in page0, but other stuff can appear 438 * between the two. We currently leave room between the two for some fiq 439 * handler code to be copied in. 440 */ 441 .global _C_LABEL(page0), _C_LABEL(page0_data) 442 443_C_LABEL(page0): 444 ldr pc, .Lreset_entry 445 ldr pc, .Lundefined_entry 446 ldr pc, .Lswi_entry 447 ldr pc, .Lprefetch_abort_entry 448 ldr pc, .Ldata_abort_entry 449 ldr pc, .Laddr_exception_entry 450 ldr pc, .Lirq_entry 451.fiqv: ldr pc, .Lfiq_entry 452 .space 256 /* room for some fiq handler code */ 453 454_C_LABEL(page0_data): 455.Lreset_entry: .word reset_entry 456.Lundefined_entry: .word undefined_entry 457.Lswi_entry: .word swi_entry 458.Lprefetch_abort_entry: .word prefetch_abort_entry 459.Ldata_abort_entry: .word data_abort_entry 460.Laddr_exception_entry: .word addr_exception_entry 461.Lirq_entry: .word irq_entry 462.Lfiq_entry: .word fiq_entry 463 464/* 465 * These items are used by the code in fiq.c to install what it calls the 466 * "null" handler. It's actually our default vector entry that just jumps 467 * to the default handler which just disables FIQs and returns. 468 */ 469 .global _C_LABEL(fiq_nullhandler_code), _C_LABEL(fiq_nullhandler_size) 470 471_C_LABEL(fiq_nullhandler_code): 472 .word .fiqv 473_C_LABEL(fiq_nullhandler_size): 474 .word 4 475 476 477