1 /* $NetBSD: arm32_machdep.c,v 1.44 2004/03/24 15:34:47 atatat Exp $ */ 2 3 /*- 4 * SPDX-License-Identifier: BSD-4-Clause 5 * 6 * Copyright (c) 2004 Olivier Houchard 7 * Copyright (c) 1994-1998 Mark Brinicombe. 8 * Copyright (c) 1994 Brini. 9 * All rights reserved. 10 * 11 * This code is derived from software written for Brini by Mark Brinicombe 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 1. Redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer. 18 * 2. Redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution. 21 * 3. All advertising materials mentioning features or use of this software 22 * must display the following acknowledgement: 23 * This product includes software developed by Mark Brinicombe 24 * for the NetBSD Project. 25 * 4. The name of the company nor the name of the author may be used to 26 * endorse or promote products derived from this software without specific 27 * prior written permission. 28 * 29 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 30 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 31 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 32 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 33 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 34 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 35 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 36 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 37 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 38 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 39 * SUCH DAMAGE. 40 * 41 * Machine dependent functions for kernel setup 42 * 43 * Created : 17/09/94 44 * Updated : 18/04/01 updated for new wscons 45 */ 46 47 #include "opt_ddb.h" 48 #include "opt_kstack_pages.h" 49 #include "opt_platform.h" 50 #include "opt_sched.h" 51 #include "opt_timer.h" 52 53 #include <sys/cdefs.h> 54 __FBSDID("$FreeBSD$"); 55 56 #include <sys/param.h> 57 #include <sys/buf.h> 58 #include <sys/bus.h> 59 #include <sys/cons.h> 60 #include <sys/cpu.h> 61 #include <sys/devmap.h> 62 #include <sys/efi.h> 63 #include <sys/imgact.h> 64 #include <sys/kdb.h> 65 #include <sys/kernel.h> 66 #include <sys/linker.h> 67 #include <sys/msgbuf.h> 68 #include <sys/reboot.h> 69 #include <sys/rwlock.h> 70 #include <sys/sched.h> 71 #include <sys/syscallsubr.h> 72 #include <sys/sysent.h> 73 #include <sys/sysproto.h> 74 #include <sys/vmmeter.h> 75 76 #include <vm/vm_object.h> 77 #include <vm/vm_page.h> 78 #include <vm/vm_pager.h> 79 80 #include <machine/asm.h> 81 #include <machine/debug_monitor.h> 82 #include <machine/machdep.h> 83 #include <machine/metadata.h> 84 #include <machine/pcb.h> 85 #include <machine/physmem.h> 86 #include <machine/platform.h> 87 #include <machine/sysarch.h> 88 #include <machine/undefined.h> 89 #include <machine/vfp.h> 90 #include <machine/vmparam.h> 91 92 #ifdef FDT 93 #include <dev/fdt/fdt_common.h> 94 #include <machine/ofw_machdep.h> 95 #endif 96 97 #ifdef DEBUG 98 #define debugf(fmt, args...) printf(fmt, ##args) 99 #else 100 #define debugf(fmt, args...) 101 #endif 102 103 #if defined(COMPAT_FREEBSD4) || defined(COMPAT_FREEBSD5) || \ 104 defined(COMPAT_FREEBSD6) || defined(COMPAT_FREEBSD7) || \ 105 defined(COMPAT_FREEBSD9) 106 #error FreeBSD/arm doesn't provide compatibility with releases prior to 10 107 #endif 108 109 #if __ARM_ARCH >= 6 && !defined(INTRNG) 110 #error armv6 requires INTRNG 111 #endif 112 113 #ifndef _ARM_ARCH_5E 114 #error FreeBSD requires ARMv5 or later 115 #endif 116 117 struct pcpu __pcpu[MAXCPU]; 118 struct pcpu *pcpup = &__pcpu[0]; 119 120 static struct trapframe proc0_tf; 121 uint32_t cpu_reset_address = 0; 122 int cold = 1; 123 vm_offset_t vector_page; 124 125 int (*_arm_memcpy)(void *, void *, int, int) = NULL; 126 int (*_arm_bzero)(void *, int, int) = NULL; 127 int _min_memcpy_size = 0; 128 int _min_bzero_size = 0; 129 130 extern int *end; 131 132 #ifdef FDT 133 vm_paddr_t pmap_pa; 134 #if __ARM_ARCH >= 6 135 vm_offset_t systempage; 136 vm_offset_t irqstack; 137 vm_offset_t undstack; 138 vm_offset_t abtstack; 139 #else 140 /* 141 * This is the number of L2 page tables required for covering max 142 * (hypothetical) memsize of 4GB and all kernel mappings (vectors, msgbuf, 143 * stacks etc.), uprounded to be divisible by 4. 144 */ 145 #define KERNEL_PT_MAX 78 146 static struct pv_addr kernel_pt_table[KERNEL_PT_MAX]; 147 struct pv_addr systempage; 148 static struct pv_addr msgbufpv; 149 struct pv_addr irqstack; 150 struct pv_addr undstack; 151 struct pv_addr abtstack; 152 static struct pv_addr kernelstack; 153 #endif /* __ARM_ARCH >= 6 */ 154 #endif /* FDT */ 155 156 #ifdef PLATFORM 157 static delay_func *delay_impl; 158 static void *delay_arg; 159 #endif 160 161 struct kva_md_info kmi; 162 163 /* 164 * arm32_vector_init: 165 * 166 * Initialize the vector page, and select whether or not to 167 * relocate the vectors. 168 * 169 * NOTE: We expect the vector page to be mapped at its expected 170 * destination. 171 */ 172 173 extern unsigned int page0[], page0_data[]; 174 void 175 arm_vector_init(vm_offset_t va, int which) 176 { 177 unsigned int *vectors = (int *) va; 178 unsigned int *vectors_data = vectors + (page0_data - page0); 179 int vec; 180 181 /* 182 * Loop through the vectors we're taking over, and copy the 183 * vector's insn and data word. 184 */ 185 for (vec = 0; vec < ARM_NVEC; vec++) { 186 if ((which & (1 << vec)) == 0) { 187 /* Don't want to take over this vector. */ 188 continue; 189 } 190 vectors[vec] = page0[vec]; 191 vectors_data[vec] = page0_data[vec]; 192 } 193 194 /* Now sync the vectors. */ 195 icache_sync(va, (ARM_NVEC * 2) * sizeof(u_int)); 196 197 vector_page = va; 198 #if __ARM_ARCH < 6 199 if (va == ARM_VECTORS_HIGH) { 200 /* 201 * Enable high vectors in the system control reg (SCTLR). 202 * 203 * Assume the MD caller knows what it's doing here, and really 204 * does want the vector page relocated. 205 * 206 * Note: This has to be done here (and not just in 207 * cpu_setup()) because the vector page needs to be 208 * accessible *before* cpu_startup() is called. 209 * Think ddb(9) ... 210 */ 211 cpu_control(CPU_CONTROL_VECRELOC, CPU_CONTROL_VECRELOC); 212 } 213 #endif 214 } 215 216 static void 217 cpu_startup(void *dummy) 218 { 219 struct pcb *pcb = thread0.td_pcb; 220 const unsigned int mbyte = 1024 * 1024; 221 #if __ARM_ARCH < 6 && !defined(ARM_CACHE_LOCK_ENABLE) 222 vm_page_t m; 223 #endif 224 225 identify_arm_cpu(); 226 227 vm_ksubmap_init(&kmi); 228 229 /* 230 * Display the RAM layout. 231 */ 232 printf("real memory = %ju (%ju MB)\n", 233 (uintmax_t)arm32_ptob(realmem), 234 (uintmax_t)arm32_ptob(realmem) / mbyte); 235 printf("avail memory = %ju (%ju MB)\n", 236 (uintmax_t)arm32_ptob(vm_free_count()), 237 (uintmax_t)arm32_ptob(vm_free_count()) / mbyte); 238 if (bootverbose) { 239 arm_physmem_print_tables(); 240 devmap_print_table(); 241 } 242 243 bufinit(); 244 vm_pager_bufferinit(); 245 pcb->pcb_regs.sf_sp = (u_int)thread0.td_kstack + 246 USPACE_SVC_STACK_TOP; 247 pmap_set_pcb_pagedir(kernel_pmap, pcb); 248 #if __ARM_ARCH < 6 249 vector_page_setprot(VM_PROT_READ); 250 pmap_postinit(); 251 #ifdef ARM_CACHE_LOCK_ENABLE 252 pmap_kenter_user(ARM_TP_ADDRESS, ARM_TP_ADDRESS); 253 arm_lock_cache_line(ARM_TP_ADDRESS); 254 #else 255 m = vm_page_alloc(NULL, 0, VM_ALLOC_NOOBJ | VM_ALLOC_ZERO); 256 pmap_kenter_user(ARM_TP_ADDRESS, VM_PAGE_TO_PHYS(m)); 257 #endif 258 *(uint32_t *)ARM_RAS_START = 0; 259 *(uint32_t *)ARM_RAS_END = 0xffffffff; 260 #endif 261 } 262 263 SYSINIT(cpu, SI_SUB_CPU, SI_ORDER_FIRST, cpu_startup, NULL); 264 265 /* 266 * Flush the D-cache for non-DMA I/O so that the I-cache can 267 * be made coherent later. 268 */ 269 void 270 cpu_flush_dcache(void *ptr, size_t len) 271 { 272 273 dcache_wb_poc((vm_offset_t)ptr, (vm_paddr_t)vtophys(ptr), len); 274 } 275 276 /* Get current clock frequency for the given cpu id. */ 277 int 278 cpu_est_clockrate(int cpu_id, uint64_t *rate) 279 { 280 #if __ARM_ARCH >= 6 281 struct pcpu *pc; 282 283 pc = pcpu_find(cpu_id); 284 if (pc == NULL || rate == NULL) 285 return (EINVAL); 286 287 if (pc->pc_clock == 0) 288 return (EOPNOTSUPP); 289 290 *rate = pc->pc_clock; 291 292 return (0); 293 #else 294 return (ENXIO); 295 #endif 296 } 297 298 void 299 cpu_idle(int busy) 300 { 301 302 CTR2(KTR_SPARE2, "cpu_idle(%d) at %d", busy, curcpu); 303 spinlock_enter(); 304 #ifndef NO_EVENTTIMERS 305 if (!busy) 306 cpu_idleclock(); 307 #endif 308 if (!sched_runnable()) 309 cpu_sleep(0); 310 #ifndef NO_EVENTTIMERS 311 if (!busy) 312 cpu_activeclock(); 313 #endif 314 spinlock_exit(); 315 CTR2(KTR_SPARE2, "cpu_idle(%d) at %d done", busy, curcpu); 316 } 317 318 int 319 cpu_idle_wakeup(int cpu) 320 { 321 322 return (0); 323 } 324 325 #ifdef NO_EVENTTIMERS 326 /* 327 * Most ARM platforms don't need to do anything special to init their clocks 328 * (they get intialized during normal device attachment), and by not defining a 329 * cpu_initclocks() function they get this generic one. Any platform that needs 330 * to do something special can just provide their own implementation, which will 331 * override this one due to the weak linkage. 332 */ 333 void 334 arm_generic_initclocks(void) 335 { 336 } 337 __weak_reference(arm_generic_initclocks, cpu_initclocks); 338 339 #else 340 void 341 cpu_initclocks(void) 342 { 343 344 #ifdef SMP 345 if (PCPU_GET(cpuid) == 0) 346 cpu_initclocks_bsp(); 347 else 348 cpu_initclocks_ap(); 349 #else 350 cpu_initclocks_bsp(); 351 #endif 352 } 353 #endif 354 355 #ifdef PLATFORM 356 void 357 arm_set_delay(delay_func *impl, void *arg) 358 { 359 360 KASSERT(impl != NULL, ("No DELAY implementation")); 361 delay_impl = impl; 362 delay_arg = arg; 363 } 364 365 void 366 DELAY(int usec) 367 { 368 369 TSENTER(); 370 delay_impl(usec, delay_arg); 371 TSEXIT(); 372 } 373 #endif 374 375 void 376 cpu_pcpu_init(struct pcpu *pcpu, int cpuid, size_t size) 377 { 378 } 379 380 void 381 spinlock_enter(void) 382 { 383 struct thread *td; 384 register_t cspr; 385 386 td = curthread; 387 if (td->td_md.md_spinlock_count == 0) { 388 cspr = disable_interrupts(PSR_I | PSR_F); 389 td->td_md.md_spinlock_count = 1; 390 td->td_md.md_saved_cspr = cspr; 391 } else 392 td->td_md.md_spinlock_count++; 393 critical_enter(); 394 } 395 396 void 397 spinlock_exit(void) 398 { 399 struct thread *td; 400 register_t cspr; 401 402 td = curthread; 403 critical_exit(); 404 cspr = td->td_md.md_saved_cspr; 405 td->td_md.md_spinlock_count--; 406 if (td->td_md.md_spinlock_count == 0) 407 restore_interrupts(cspr); 408 } 409 410 /* 411 * Clear registers on exec 412 */ 413 void 414 exec_setregs(struct thread *td, struct image_params *imgp, u_long stack) 415 { 416 struct trapframe *tf = td->td_frame; 417 418 memset(tf, 0, sizeof(*tf)); 419 tf->tf_usr_sp = stack; 420 tf->tf_usr_lr = imgp->entry_addr; 421 tf->tf_svc_lr = 0x77777777; 422 tf->tf_pc = imgp->entry_addr; 423 tf->tf_spsr = PSR_USR32_MODE; 424 } 425 426 427 #ifdef VFP 428 /* 429 * Get machine VFP context. 430 */ 431 void 432 get_vfpcontext(struct thread *td, mcontext_vfp_t *vfp) 433 { 434 struct pcb *pcb; 435 436 pcb = td->td_pcb; 437 if (td == curthread) { 438 critical_enter(); 439 vfp_store(&pcb->pcb_vfpstate, false); 440 critical_exit(); 441 } else 442 MPASS(TD_IS_SUSPENDED(td)); 443 memcpy(vfp->mcv_reg, pcb->pcb_vfpstate.reg, 444 sizeof(vfp->mcv_reg)); 445 vfp->mcv_fpscr = pcb->pcb_vfpstate.fpscr; 446 } 447 448 /* 449 * Set machine VFP context. 450 */ 451 void 452 set_vfpcontext(struct thread *td, mcontext_vfp_t *vfp) 453 { 454 struct pcb *pcb; 455 456 pcb = td->td_pcb; 457 if (td == curthread) { 458 critical_enter(); 459 vfp_discard(td); 460 critical_exit(); 461 } else 462 MPASS(TD_IS_SUSPENDED(td)); 463 memcpy(pcb->pcb_vfpstate.reg, vfp->mcv_reg, 464 sizeof(pcb->pcb_vfpstate.reg)); 465 pcb->pcb_vfpstate.fpscr = vfp->mcv_fpscr; 466 } 467 #endif 468 469 int 470 arm_get_vfpstate(struct thread *td, void *args) 471 { 472 int rv; 473 struct arm_get_vfpstate_args ua; 474 mcontext_vfp_t mcontext_vfp; 475 476 rv = copyin(args, &ua, sizeof(ua)); 477 if (rv != 0) 478 return (rv); 479 if (ua.mc_vfp_size != sizeof(mcontext_vfp_t)) 480 return (EINVAL); 481 #ifdef VFP 482 get_vfpcontext(td, &mcontext_vfp); 483 #else 484 bzero(&mcontext_vfp, sizeof(mcontext_vfp)); 485 #endif 486 487 rv = copyout(&mcontext_vfp, ua.mc_vfp, sizeof(mcontext_vfp)); 488 if (rv != 0) 489 return (rv); 490 return (0); 491 } 492 493 /* 494 * Get machine context. 495 */ 496 int 497 get_mcontext(struct thread *td, mcontext_t *mcp, int clear_ret) 498 { 499 struct trapframe *tf = td->td_frame; 500 __greg_t *gr = mcp->__gregs; 501 502 if (clear_ret & GET_MC_CLEAR_RET) { 503 gr[_REG_R0] = 0; 504 gr[_REG_CPSR] = tf->tf_spsr & ~PSR_C; 505 } else { 506 gr[_REG_R0] = tf->tf_r0; 507 gr[_REG_CPSR] = tf->tf_spsr; 508 } 509 gr[_REG_R1] = tf->tf_r1; 510 gr[_REG_R2] = tf->tf_r2; 511 gr[_REG_R3] = tf->tf_r3; 512 gr[_REG_R4] = tf->tf_r4; 513 gr[_REG_R5] = tf->tf_r5; 514 gr[_REG_R6] = tf->tf_r6; 515 gr[_REG_R7] = tf->tf_r7; 516 gr[_REG_R8] = tf->tf_r8; 517 gr[_REG_R9] = tf->tf_r9; 518 gr[_REG_R10] = tf->tf_r10; 519 gr[_REG_R11] = tf->tf_r11; 520 gr[_REG_R12] = tf->tf_r12; 521 gr[_REG_SP] = tf->tf_usr_sp; 522 gr[_REG_LR] = tf->tf_usr_lr; 523 gr[_REG_PC] = tf->tf_pc; 524 525 mcp->mc_vfp_size = 0; 526 mcp->mc_vfp_ptr = NULL; 527 memset(&mcp->mc_spare, 0, sizeof(mcp->mc_spare)); 528 529 return (0); 530 } 531 532 /* 533 * Set machine context. 534 * 535 * However, we don't set any but the user modifiable flags, and we won't 536 * touch the cs selector. 537 */ 538 int 539 set_mcontext(struct thread *td, mcontext_t *mcp) 540 { 541 mcontext_vfp_t mc_vfp, *vfp; 542 struct trapframe *tf = td->td_frame; 543 const __greg_t *gr = mcp->__gregs; 544 int spsr; 545 546 /* 547 * Make sure the processor mode has not been tampered with and 548 * interrupts have not been disabled. 549 */ 550 spsr = gr[_REG_CPSR]; 551 if ((spsr & PSR_MODE) != PSR_USR32_MODE || 552 (spsr & (PSR_I | PSR_F)) != 0) 553 return (EINVAL); 554 555 #ifdef WITNESS 556 if (mcp->mc_vfp_size != 0 && mcp->mc_vfp_size != sizeof(mc_vfp)) { 557 printf("%s: %s: Malformed mc_vfp_size: %d (0x%08X)\n", 558 td->td_proc->p_comm, __func__, 559 mcp->mc_vfp_size, mcp->mc_vfp_size); 560 } else if (mcp->mc_vfp_size != 0 && mcp->mc_vfp_ptr == NULL) { 561 printf("%s: %s: c_vfp_size != 0 but mc_vfp_ptr == NULL\n", 562 td->td_proc->p_comm, __func__); 563 } 564 #endif 565 566 if (mcp->mc_vfp_size == sizeof(mc_vfp) && mcp->mc_vfp_ptr != NULL) { 567 if (copyin(mcp->mc_vfp_ptr, &mc_vfp, sizeof(mc_vfp)) != 0) 568 return (EFAULT); 569 vfp = &mc_vfp; 570 } else { 571 vfp = NULL; 572 } 573 574 tf->tf_r0 = gr[_REG_R0]; 575 tf->tf_r1 = gr[_REG_R1]; 576 tf->tf_r2 = gr[_REG_R2]; 577 tf->tf_r3 = gr[_REG_R3]; 578 tf->tf_r4 = gr[_REG_R4]; 579 tf->tf_r5 = gr[_REG_R5]; 580 tf->tf_r6 = gr[_REG_R6]; 581 tf->tf_r7 = gr[_REG_R7]; 582 tf->tf_r8 = gr[_REG_R8]; 583 tf->tf_r9 = gr[_REG_R9]; 584 tf->tf_r10 = gr[_REG_R10]; 585 tf->tf_r11 = gr[_REG_R11]; 586 tf->tf_r12 = gr[_REG_R12]; 587 tf->tf_usr_sp = gr[_REG_SP]; 588 tf->tf_usr_lr = gr[_REG_LR]; 589 tf->tf_pc = gr[_REG_PC]; 590 tf->tf_spsr = gr[_REG_CPSR]; 591 #ifdef VFP 592 if (vfp != NULL) 593 set_vfpcontext(td, vfp); 594 #endif 595 return (0); 596 } 597 598 void 599 sendsig(catcher, ksi, mask) 600 sig_t catcher; 601 ksiginfo_t *ksi; 602 sigset_t *mask; 603 { 604 struct thread *td; 605 struct proc *p; 606 struct trapframe *tf; 607 struct sigframe *fp, frame; 608 struct sigacts *psp; 609 struct sysentvec *sysent; 610 int onstack; 611 int sig; 612 int code; 613 614 td = curthread; 615 p = td->td_proc; 616 PROC_LOCK_ASSERT(p, MA_OWNED); 617 sig = ksi->ksi_signo; 618 code = ksi->ksi_code; 619 psp = p->p_sigacts; 620 mtx_assert(&psp->ps_mtx, MA_OWNED); 621 tf = td->td_frame; 622 onstack = sigonstack(tf->tf_usr_sp); 623 624 CTR4(KTR_SIG, "sendsig: td=%p (%s) catcher=%p sig=%d", td, p->p_comm, 625 catcher, sig); 626 627 /* Allocate and validate space for the signal handler context. */ 628 if ((td->td_pflags & TDP_ALTSTACK) != 0 && !(onstack) && 629 SIGISMEMBER(psp->ps_sigonstack, sig)) { 630 fp = (struct sigframe *)((uintptr_t)td->td_sigstk.ss_sp + 631 td->td_sigstk.ss_size); 632 #if defined(COMPAT_43) 633 td->td_sigstk.ss_flags |= SS_ONSTACK; 634 #endif 635 } else 636 fp = (struct sigframe *)td->td_frame->tf_usr_sp; 637 638 /* make room on the stack */ 639 fp--; 640 641 /* make the stack aligned */ 642 fp = (struct sigframe *)STACKALIGN(fp); 643 /* Populate the siginfo frame. */ 644 bzero(&frame, sizeof(frame)); 645 get_mcontext(td, &frame.sf_uc.uc_mcontext, 0); 646 #ifdef VFP 647 get_vfpcontext(td, &frame.sf_vfp); 648 frame.sf_uc.uc_mcontext.mc_vfp_size = sizeof(fp->sf_vfp); 649 frame.sf_uc.uc_mcontext.mc_vfp_ptr = &fp->sf_vfp; 650 #else 651 frame.sf_uc.uc_mcontext.mc_vfp_size = 0; 652 frame.sf_uc.uc_mcontext.mc_vfp_ptr = NULL; 653 #endif 654 frame.sf_si = ksi->ksi_info; 655 frame.sf_uc.uc_sigmask = *mask; 656 frame.sf_uc.uc_stack = td->td_sigstk; 657 frame.sf_uc.uc_stack.ss_flags = (td->td_pflags & TDP_ALTSTACK) != 0 ? 658 (onstack ? SS_ONSTACK : 0) : SS_DISABLE; 659 mtx_unlock(&psp->ps_mtx); 660 PROC_UNLOCK(td->td_proc); 661 662 /* Copy the sigframe out to the user's stack. */ 663 if (copyout(&frame, fp, sizeof(*fp)) != 0) { 664 /* Process has trashed its stack. Kill it. */ 665 CTR2(KTR_SIG, "sendsig: sigexit td=%p fp=%p", td, fp); 666 PROC_LOCK(p); 667 sigexit(td, SIGILL); 668 } 669 670 /* 671 * Build context to run handler in. We invoke the handler 672 * directly, only returning via the trampoline. Note the 673 * trampoline version numbers are coordinated with machine- 674 * dependent code in libc. 675 */ 676 677 tf->tf_r0 = sig; 678 tf->tf_r1 = (register_t)&fp->sf_si; 679 tf->tf_r2 = (register_t)&fp->sf_uc; 680 681 /* the trampoline uses r5 as the uc address */ 682 tf->tf_r5 = (register_t)&fp->sf_uc; 683 tf->tf_pc = (register_t)catcher; 684 tf->tf_usr_sp = (register_t)fp; 685 sysent = p->p_sysent; 686 if (sysent->sv_sigcode_base != 0) 687 tf->tf_usr_lr = (register_t)sysent->sv_sigcode_base; 688 else 689 tf->tf_usr_lr = (register_t)(sysent->sv_psstrings - 690 *(sysent->sv_szsigcode)); 691 /* Set the mode to enter in the signal handler */ 692 #if __ARM_ARCH >= 7 693 if ((register_t)catcher & 1) 694 tf->tf_spsr |= PSR_T; 695 else 696 tf->tf_spsr &= ~PSR_T; 697 #endif 698 699 CTR3(KTR_SIG, "sendsig: return td=%p pc=%#x sp=%#x", td, tf->tf_usr_lr, 700 tf->tf_usr_sp); 701 702 PROC_LOCK(p); 703 mtx_lock(&psp->ps_mtx); 704 } 705 706 int 707 sys_sigreturn(td, uap) 708 struct thread *td; 709 struct sigreturn_args /* { 710 const struct __ucontext *sigcntxp; 711 } */ *uap; 712 { 713 ucontext_t uc; 714 int error; 715 716 if (uap == NULL) 717 return (EFAULT); 718 if (copyin(uap->sigcntxp, &uc, sizeof(uc))) 719 return (EFAULT); 720 /* Restore register context. */ 721 error = set_mcontext(td, &uc.uc_mcontext); 722 if (error != 0) 723 return (error); 724 725 /* Restore signal mask. */ 726 kern_sigprocmask(td, SIG_SETMASK, &uc.uc_sigmask, NULL, 0); 727 728 return (EJUSTRETURN); 729 } 730 731 /* 732 * Construct a PCB from a trapframe. This is called from kdb_trap() where 733 * we want to start a backtrace from the function that caused us to enter 734 * the debugger. We have the context in the trapframe, but base the trace 735 * on the PCB. The PCB doesn't have to be perfect, as long as it contains 736 * enough for a backtrace. 737 */ 738 void 739 makectx(struct trapframe *tf, struct pcb *pcb) 740 { 741 pcb->pcb_regs.sf_r4 = tf->tf_r4; 742 pcb->pcb_regs.sf_r5 = tf->tf_r5; 743 pcb->pcb_regs.sf_r6 = tf->tf_r6; 744 pcb->pcb_regs.sf_r7 = tf->tf_r7; 745 pcb->pcb_regs.sf_r8 = tf->tf_r8; 746 pcb->pcb_regs.sf_r9 = tf->tf_r9; 747 pcb->pcb_regs.sf_r10 = tf->tf_r10; 748 pcb->pcb_regs.sf_r11 = tf->tf_r11; 749 pcb->pcb_regs.sf_r12 = tf->tf_r12; 750 pcb->pcb_regs.sf_pc = tf->tf_pc; 751 pcb->pcb_regs.sf_lr = tf->tf_usr_lr; 752 pcb->pcb_regs.sf_sp = tf->tf_usr_sp; 753 } 754 755 void 756 pcpu0_init(void) 757 { 758 #if __ARM_ARCH >= 6 759 set_curthread(&thread0); 760 #endif 761 pcpu_init(pcpup, 0, sizeof(struct pcpu)); 762 PCPU_SET(curthread, &thread0); 763 } 764 765 /* 766 * Initialize proc0 767 */ 768 void 769 init_proc0(vm_offset_t kstack) 770 { 771 proc_linkup0(&proc0, &thread0); 772 thread0.td_kstack = kstack; 773 thread0.td_pcb = (struct pcb *) 774 (thread0.td_kstack + kstack_pages * PAGE_SIZE) - 1; 775 thread0.td_pcb->pcb_flags = 0; 776 thread0.td_pcb->pcb_vfpcpu = -1; 777 thread0.td_pcb->pcb_vfpstate.fpscr = VFPSCR_DN; 778 thread0.td_frame = &proc0_tf; 779 pcpup->pc_curpcb = thread0.td_pcb; 780 } 781 782 #if __ARM_ARCH >= 6 783 void 784 set_stackptrs(int cpu) 785 { 786 787 set_stackptr(PSR_IRQ32_MODE, 788 irqstack + ((IRQ_STACK_SIZE * PAGE_SIZE) * (cpu + 1))); 789 set_stackptr(PSR_ABT32_MODE, 790 abtstack + ((ABT_STACK_SIZE * PAGE_SIZE) * (cpu + 1))); 791 set_stackptr(PSR_UND32_MODE, 792 undstack + ((UND_STACK_SIZE * PAGE_SIZE) * (cpu + 1))); 793 } 794 #else 795 void 796 set_stackptrs(int cpu) 797 { 798 799 set_stackptr(PSR_IRQ32_MODE, 800 irqstack.pv_va + ((IRQ_STACK_SIZE * PAGE_SIZE) * (cpu + 1))); 801 set_stackptr(PSR_ABT32_MODE, 802 abtstack.pv_va + ((ABT_STACK_SIZE * PAGE_SIZE) * (cpu + 1))); 803 set_stackptr(PSR_UND32_MODE, 804 undstack.pv_va + ((UND_STACK_SIZE * PAGE_SIZE) * (cpu + 1))); 805 } 806 #endif 807 808 static void 809 arm_kdb_init(void) 810 { 811 812 kdb_init(); 813 #ifdef KDB 814 if (boothowto & RB_KDB) 815 kdb_enter(KDB_WHY_BOOTFLAGS, "Boot flags requested debugger"); 816 #endif 817 } 818 819 #ifdef FDT 820 #if __ARM_ARCH < 6 821 void * 822 initarm(struct arm_boot_params *abp) 823 { 824 struct mem_region mem_regions[FDT_MEM_REGIONS]; 825 struct pv_addr kernel_l1pt; 826 struct pv_addr dpcpu; 827 vm_offset_t dtbp, freemempos, l2_start, lastaddr; 828 uint64_t memsize; 829 uint32_t l2size; 830 char *env; 831 void *kmdp; 832 u_int l1pagetable; 833 int i, j, err_devmap, mem_regions_sz; 834 835 lastaddr = parse_boot_param(abp); 836 arm_physmem_kernaddr = abp->abp_physaddr; 837 838 memsize = 0; 839 840 cpuinfo_init(); 841 set_cpufuncs(); 842 843 /* 844 * Find the dtb passed in by the boot loader. 845 */ 846 kmdp = preload_search_by_type("elf kernel"); 847 if (kmdp != NULL) 848 dtbp = MD_FETCH(kmdp, MODINFOMD_DTBP, vm_offset_t); 849 else 850 dtbp = (vm_offset_t)NULL; 851 852 #if defined(FDT_DTB_STATIC) 853 /* 854 * In case the device tree blob was not retrieved (from metadata) try 855 * to use the statically embedded one. 856 */ 857 if (dtbp == (vm_offset_t)NULL) 858 dtbp = (vm_offset_t)&fdt_static_dtb; 859 #endif 860 861 if (OF_install(OFW_FDT, 0) == FALSE) 862 panic("Cannot install FDT"); 863 864 if (OF_init((void *)dtbp) != 0) 865 panic("OF_init failed with the found device tree"); 866 867 /* Grab physical memory regions information from device tree. */ 868 if (fdt_get_mem_regions(mem_regions, &mem_regions_sz, &memsize) != 0) 869 panic("Cannot get physical memory regions"); 870 arm_physmem_hardware_regions(mem_regions, mem_regions_sz); 871 872 /* Grab reserved memory regions information from device tree. */ 873 if (fdt_get_reserved_regions(mem_regions, &mem_regions_sz) == 0) 874 arm_physmem_exclude_regions(mem_regions, mem_regions_sz, 875 EXFLAG_NODUMP | EXFLAG_NOALLOC); 876 877 /* Platform-specific initialisation */ 878 platform_probe_and_attach(); 879 880 pcpu0_init(); 881 882 /* Do basic tuning, hz etc */ 883 init_param1(); 884 885 /* Calculate number of L2 tables needed for mapping vm_page_array */ 886 l2size = (memsize / PAGE_SIZE) * sizeof(struct vm_page); 887 l2size = (l2size >> L1_S_SHIFT) + 1; 888 889 /* 890 * Add one table for end of kernel map, one for stacks, msgbuf and 891 * L1 and L2 tables map, one for vectors map and two for 892 * l2 structures from pmap_bootstrap. 893 */ 894 l2size += 5; 895 896 /* Make it divisible by 4 */ 897 l2size = (l2size + 3) & ~3; 898 899 freemempos = (lastaddr + PAGE_MASK) & ~PAGE_MASK; 900 901 /* Define a macro to simplify memory allocation */ 902 #define valloc_pages(var, np) \ 903 alloc_pages((var).pv_va, (np)); \ 904 (var).pv_pa = (var).pv_va + (abp->abp_physaddr - KERNVIRTADDR); 905 906 #define alloc_pages(var, np) \ 907 (var) = freemempos; \ 908 freemempos += (np * PAGE_SIZE); \ 909 memset((char *)(var), 0, ((np) * PAGE_SIZE)); 910 911 while (((freemempos - L1_TABLE_SIZE) & (L1_TABLE_SIZE - 1)) != 0) 912 freemempos += PAGE_SIZE; 913 valloc_pages(kernel_l1pt, L1_TABLE_SIZE / PAGE_SIZE); 914 915 for (i = 0, j = 0; i < l2size; ++i) { 916 if (!(i % (PAGE_SIZE / L2_TABLE_SIZE_REAL))) { 917 valloc_pages(kernel_pt_table[i], 918 L2_TABLE_SIZE / PAGE_SIZE); 919 j = i; 920 } else { 921 kernel_pt_table[i].pv_va = kernel_pt_table[j].pv_va + 922 L2_TABLE_SIZE_REAL * (i - j); 923 kernel_pt_table[i].pv_pa = 924 kernel_pt_table[i].pv_va - KERNVIRTADDR + 925 abp->abp_physaddr; 926 927 } 928 } 929 /* 930 * Allocate a page for the system page mapped to 0x00000000 931 * or 0xffff0000. This page will just contain the system vectors 932 * and can be shared by all processes. 933 */ 934 valloc_pages(systempage, 1); 935 936 /* Allocate dynamic per-cpu area. */ 937 valloc_pages(dpcpu, DPCPU_SIZE / PAGE_SIZE); 938 dpcpu_init((void *)dpcpu.pv_va, 0); 939 940 /* Allocate stacks for all modes */ 941 valloc_pages(irqstack, IRQ_STACK_SIZE * MAXCPU); 942 valloc_pages(abtstack, ABT_STACK_SIZE * MAXCPU); 943 valloc_pages(undstack, UND_STACK_SIZE * MAXCPU); 944 valloc_pages(kernelstack, kstack_pages * MAXCPU); 945 valloc_pages(msgbufpv, round_page(msgbufsize) / PAGE_SIZE); 946 947 /* 948 * Now we start construction of the L1 page table 949 * We start by mapping the L2 page tables into the L1. 950 * This means that we can replace L1 mappings later on if necessary 951 */ 952 l1pagetable = kernel_l1pt.pv_va; 953 954 /* 955 * Try to map as much as possible of kernel text and data using 956 * 1MB section mapping and for the rest of initial kernel address 957 * space use L2 coarse tables. 958 * 959 * Link L2 tables for mapping remainder of kernel (modulo 1MB) 960 * and kernel structures 961 */ 962 l2_start = lastaddr & ~(L1_S_OFFSET); 963 for (i = 0 ; i < l2size - 1; i++) 964 pmap_link_l2pt(l1pagetable, l2_start + i * L1_S_SIZE, 965 &kernel_pt_table[i]); 966 967 pmap_curmaxkvaddr = l2_start + (l2size - 1) * L1_S_SIZE; 968 969 /* Map kernel code and data */ 970 pmap_map_chunk(l1pagetable, KERNVIRTADDR, abp->abp_physaddr, 971 (((uint32_t)(lastaddr) - KERNVIRTADDR) + PAGE_MASK) & ~PAGE_MASK, 972 VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE); 973 974 /* Map L1 directory and allocated L2 page tables */ 975 pmap_map_chunk(l1pagetable, kernel_l1pt.pv_va, kernel_l1pt.pv_pa, 976 L1_TABLE_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_PAGETABLE); 977 978 pmap_map_chunk(l1pagetable, kernel_pt_table[0].pv_va, 979 kernel_pt_table[0].pv_pa, 980 L2_TABLE_SIZE_REAL * l2size, 981 VM_PROT_READ|VM_PROT_WRITE, PTE_PAGETABLE); 982 983 /* Map allocated DPCPU, stacks and msgbuf */ 984 pmap_map_chunk(l1pagetable, dpcpu.pv_va, dpcpu.pv_pa, 985 freemempos - dpcpu.pv_va, 986 VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE); 987 988 /* Link and map the vector page */ 989 pmap_link_l2pt(l1pagetable, ARM_VECTORS_HIGH, 990 &kernel_pt_table[l2size - 1]); 991 pmap_map_entry(l1pagetable, ARM_VECTORS_HIGH, systempage.pv_pa, 992 VM_PROT_READ|VM_PROT_WRITE|VM_PROT_EXECUTE, PTE_CACHE); 993 994 /* Establish static device mappings. */ 995 err_devmap = platform_devmap_init(); 996 devmap_bootstrap(l1pagetable, NULL); 997 vm_max_kernel_address = platform_lastaddr(); 998 999 cpu_domains((DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2)) | DOMAIN_CLIENT); 1000 pmap_pa = kernel_l1pt.pv_pa; 1001 cpu_setttb(kernel_l1pt.pv_pa); 1002 cpu_tlb_flushID(); 1003 cpu_domains(DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2)); 1004 1005 /* 1006 * Now that proper page tables are installed, call cpu_setup() to enable 1007 * instruction and data caches and other chip-specific features. 1008 */ 1009 cpu_setup(); 1010 1011 /* 1012 * Only after the SOC registers block is mapped we can perform device 1013 * tree fixups, as they may attempt to read parameters from hardware. 1014 */ 1015 OF_interpret("perform-fixup", 0); 1016 1017 platform_gpio_init(); 1018 1019 cninit(); 1020 1021 debugf("initarm: console initialized\n"); 1022 debugf(" arg1 kmdp = 0x%08x\n", (uint32_t)kmdp); 1023 debugf(" boothowto = 0x%08x\n", boothowto); 1024 debugf(" dtbp = 0x%08x\n", (uint32_t)dtbp); 1025 arm_print_kenv(); 1026 1027 env = kern_getenv("kernelname"); 1028 if (env != NULL) { 1029 strlcpy(kernelname, env, sizeof(kernelname)); 1030 freeenv(env); 1031 } 1032 1033 if (err_devmap != 0) 1034 printf("WARNING: could not fully configure devmap, error=%d\n", 1035 err_devmap); 1036 1037 platform_late_init(); 1038 1039 /* 1040 * Pages were allocated during the secondary bootstrap for the 1041 * stacks for different CPU modes. 1042 * We must now set the r13 registers in the different CPU modes to 1043 * point to these stacks. 1044 * Since the ARM stacks use STMFD etc. we must set r13 to the top end 1045 * of the stack memory. 1046 */ 1047 cpu_control(CPU_CONTROL_MMU_ENABLE, CPU_CONTROL_MMU_ENABLE); 1048 1049 set_stackptrs(0); 1050 1051 /* 1052 * We must now clean the cache again.... 1053 * Cleaning may be done by reading new data to displace any 1054 * dirty data in the cache. This will have happened in cpu_setttb() 1055 * but since we are boot strapping the addresses used for the read 1056 * may have just been remapped and thus the cache could be out 1057 * of sync. A re-clean after the switch will cure this. 1058 * After booting there are no gross relocations of the kernel thus 1059 * this problem will not occur after initarm(). 1060 */ 1061 cpu_idcache_wbinv_all(); 1062 1063 undefined_init(); 1064 1065 init_proc0(kernelstack.pv_va); 1066 1067 arm_vector_init(ARM_VECTORS_HIGH, ARM_VEC_ALL); 1068 pmap_bootstrap(freemempos, &kernel_l1pt); 1069 msgbufp = (void *)msgbufpv.pv_va; 1070 msgbufinit(msgbufp, msgbufsize); 1071 mutex_init(); 1072 1073 /* 1074 * Exclude the kernel (and all the things we allocated which immediately 1075 * follow the kernel) from the VM allocation pool but not from crash 1076 * dumps. virtual_avail is a global variable which tracks the kva we've 1077 * "allocated" while setting up pmaps. 1078 * 1079 * Prepare the list of physical memory available to the vm subsystem. 1080 */ 1081 arm_physmem_exclude_region(abp->abp_physaddr, 1082 (virtual_avail - KERNVIRTADDR), EXFLAG_NOALLOC); 1083 arm_physmem_init_kernel_globals(); 1084 1085 init_param2(physmem); 1086 dbg_monitor_init(); 1087 arm_kdb_init(); 1088 1089 return ((void *)(kernelstack.pv_va + USPACE_SVC_STACK_TOP - 1090 sizeof(struct pcb))); 1091 } 1092 #else /* __ARM_ARCH < 6 */ 1093 void * 1094 initarm(struct arm_boot_params *abp) 1095 { 1096 struct mem_region mem_regions[FDT_MEM_REGIONS]; 1097 vm_paddr_t lastaddr; 1098 vm_offset_t dtbp, kernelstack, dpcpu; 1099 char *env; 1100 void *kmdp; 1101 int err_devmap, mem_regions_sz; 1102 #ifdef EFI 1103 struct efi_map_header *efihdr; 1104 #endif 1105 1106 /* get last allocated physical address */ 1107 arm_physmem_kernaddr = abp->abp_physaddr; 1108 lastaddr = parse_boot_param(abp) - KERNVIRTADDR + arm_physmem_kernaddr; 1109 1110 set_cpufuncs(); 1111 cpuinfo_init(); 1112 1113 /* 1114 * Find the dtb passed in by the boot loader. 1115 */ 1116 kmdp = preload_search_by_type("elf kernel"); 1117 dtbp = MD_FETCH(kmdp, MODINFOMD_DTBP, vm_offset_t); 1118 #if defined(FDT_DTB_STATIC) 1119 /* 1120 * In case the device tree blob was not retrieved (from metadata) try 1121 * to use the statically embedded one. 1122 */ 1123 if (dtbp == (vm_offset_t)NULL) 1124 dtbp = (vm_offset_t)&fdt_static_dtb; 1125 #endif 1126 1127 if (OF_install(OFW_FDT, 0) == FALSE) 1128 panic("Cannot install FDT"); 1129 1130 if (OF_init((void *)dtbp) != 0) 1131 panic("OF_init failed with the found device tree"); 1132 1133 #if defined(LINUX_BOOT_ABI) 1134 arm_parse_fdt_bootargs(); 1135 #endif 1136 1137 #ifdef EFI 1138 efihdr = (struct efi_map_header *)preload_search_info(kmdp, 1139 MODINFO_METADATA | MODINFOMD_EFI_MAP); 1140 if (efihdr != NULL) { 1141 arm_add_efi_map_entries(efihdr, mem_regions, &mem_regions_sz); 1142 } else 1143 #endif 1144 { 1145 /* Grab physical memory regions information from device tree. */ 1146 if (fdt_get_mem_regions(mem_regions, &mem_regions_sz,NULL) != 0) 1147 panic("Cannot get physical memory regions"); 1148 } 1149 arm_physmem_hardware_regions(mem_regions, mem_regions_sz); 1150 1151 /* Grab reserved memory regions information from device tree. */ 1152 if (fdt_get_reserved_regions(mem_regions, &mem_regions_sz) == 0) 1153 arm_physmem_exclude_regions(mem_regions, mem_regions_sz, 1154 EXFLAG_NODUMP | EXFLAG_NOALLOC); 1155 1156 /* 1157 * Set TEX remapping registers. 1158 * Setup kernel page tables and switch to kernel L1 page table. 1159 */ 1160 pmap_set_tex(); 1161 pmap_bootstrap_prepare(lastaddr); 1162 1163 /* 1164 * If EARLY_PRINTF support is enabled, we need to re-establish the 1165 * mapping after pmap_bootstrap_prepare() switches to new page tables. 1166 * Note that we can only do the remapping if the VA is outside the 1167 * kernel, now that we have real virtual (not VA=PA) mappings in effect. 1168 * Early printf does not work between the time pmap_set_tex() does 1169 * cp15_prrr_set() and this code remaps the VA. 1170 */ 1171 #if defined(EARLY_PRINTF) && defined(SOCDEV_PA) && defined(SOCDEV_VA) && SOCDEV_VA < KERNBASE 1172 pmap_preboot_map_attr(SOCDEV_PA, SOCDEV_VA, 1024 * 1024, 1173 VM_PROT_READ | VM_PROT_WRITE, VM_MEMATTR_DEVICE); 1174 #endif 1175 1176 /* 1177 * Now that proper page tables are installed, call cpu_setup() to enable 1178 * instruction and data caches and other chip-specific features. 1179 */ 1180 cpu_setup(); 1181 1182 /* Platform-specific initialisation */ 1183 platform_probe_and_attach(); 1184 pcpu0_init(); 1185 1186 /* Do basic tuning, hz etc */ 1187 init_param1(); 1188 1189 /* 1190 * Allocate a page for the system page mapped to 0xffff0000 1191 * This page will just contain the system vectors and can be 1192 * shared by all processes. 1193 */ 1194 systempage = pmap_preboot_get_pages(1); 1195 1196 /* Map the vector page. */ 1197 pmap_preboot_map_pages(systempage, ARM_VECTORS_HIGH, 1); 1198 if (virtual_end >= ARM_VECTORS_HIGH) 1199 virtual_end = ARM_VECTORS_HIGH - 1; 1200 1201 /* Allocate dynamic per-cpu area. */ 1202 dpcpu = pmap_preboot_get_vpages(DPCPU_SIZE / PAGE_SIZE); 1203 dpcpu_init((void *)dpcpu, 0); 1204 1205 /* Allocate stacks for all modes */ 1206 irqstack = pmap_preboot_get_vpages(IRQ_STACK_SIZE * MAXCPU); 1207 abtstack = pmap_preboot_get_vpages(ABT_STACK_SIZE * MAXCPU); 1208 undstack = pmap_preboot_get_vpages(UND_STACK_SIZE * MAXCPU ); 1209 kernelstack = pmap_preboot_get_vpages(kstack_pages * MAXCPU); 1210 1211 /* Allocate message buffer. */ 1212 msgbufp = (void *)pmap_preboot_get_vpages( 1213 round_page(msgbufsize) / PAGE_SIZE); 1214 1215 /* 1216 * Pages were allocated during the secondary bootstrap for the 1217 * stacks for different CPU modes. 1218 * We must now set the r13 registers in the different CPU modes to 1219 * point to these stacks. 1220 * Since the ARM stacks use STMFD etc. we must set r13 to the top end 1221 * of the stack memory. 1222 */ 1223 set_stackptrs(0); 1224 mutex_init(); 1225 1226 /* Establish static device mappings. */ 1227 err_devmap = platform_devmap_init(); 1228 devmap_bootstrap(0, NULL); 1229 vm_max_kernel_address = platform_lastaddr(); 1230 1231 /* 1232 * Only after the SOC registers block is mapped we can perform device 1233 * tree fixups, as they may attempt to read parameters from hardware. 1234 */ 1235 OF_interpret("perform-fixup", 0); 1236 platform_gpio_init(); 1237 cninit(); 1238 1239 /* 1240 * If we made a mapping for EARLY_PRINTF after pmap_bootstrap_prepare(), 1241 * undo it now that the normal console printf works. 1242 */ 1243 #if defined(EARLY_PRINTF) && defined(SOCDEV_PA) && defined(SOCDEV_VA) && SOCDEV_VA < KERNBASE 1244 pmap_kremove(SOCDEV_VA); 1245 #endif 1246 1247 debugf("initarm: console initialized\n"); 1248 debugf(" arg1 kmdp = 0x%08x\n", (uint32_t)kmdp); 1249 debugf(" boothowto = 0x%08x\n", boothowto); 1250 debugf(" dtbp = 0x%08x\n", (uint32_t)dtbp); 1251 debugf(" lastaddr1: 0x%08x\n", lastaddr); 1252 arm_print_kenv(); 1253 1254 env = kern_getenv("kernelname"); 1255 if (env != NULL) 1256 strlcpy(kernelname, env, sizeof(kernelname)); 1257 1258 if (err_devmap != 0) 1259 printf("WARNING: could not fully configure devmap, error=%d\n", 1260 err_devmap); 1261 1262 platform_late_init(); 1263 1264 /* 1265 * We must now clean the cache again.... 1266 * Cleaning may be done by reading new data to displace any 1267 * dirty data in the cache. This will have happened in cpu_setttb() 1268 * but since we are boot strapping the addresses used for the read 1269 * may have just been remapped and thus the cache could be out 1270 * of sync. A re-clean after the switch will cure this. 1271 * After booting there are no gross relocations of the kernel thus 1272 * this problem will not occur after initarm(). 1273 */ 1274 /* Set stack for exception handlers */ 1275 undefined_init(); 1276 init_proc0(kernelstack); 1277 arm_vector_init(ARM_VECTORS_HIGH, ARM_VEC_ALL); 1278 enable_interrupts(PSR_A); 1279 pmap_bootstrap(0); 1280 1281 /* Exclude the kernel (and all the things we allocated which immediately 1282 * follow the kernel) from the VM allocation pool but not from crash 1283 * dumps. virtual_avail is a global variable which tracks the kva we've 1284 * "allocated" while setting up pmaps. 1285 * 1286 * Prepare the list of physical memory available to the vm subsystem. 1287 */ 1288 arm_physmem_exclude_region(abp->abp_physaddr, 1289 pmap_preboot_get_pages(0) - abp->abp_physaddr, EXFLAG_NOALLOC); 1290 arm_physmem_init_kernel_globals(); 1291 1292 init_param2(physmem); 1293 /* Init message buffer. */ 1294 msgbufinit(msgbufp, msgbufsize); 1295 dbg_monitor_init(); 1296 arm_kdb_init(); 1297 /* Apply possible BP hardening. */ 1298 cpuinfo_init_bp_hardening(); 1299 return ((void *)STACKALIGN(thread0.td_pcb)); 1300 1301 } 1302 1303 #endif /* __ARM_ARCH < 6 */ 1304 #endif /* FDT */ 1305