1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2011 Semihalf. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 #include "opt_ddb.h" 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/bus.h> 35 #include <sys/kernel.h> 36 #include <sys/lock.h> 37 #include <sys/mutex.h> 38 #include <sys/proc.h> 39 #include <sys/pcpu.h> 40 #include <sys/sched.h> 41 #include <sys/smp.h> 42 #include <sys/ktr.h> 43 #include <sys/malloc.h> 44 45 #include <vm/vm.h> 46 #include <vm/vm_extern.h> 47 #include <vm/vm_kern.h> 48 #include <vm/pmap.h> 49 50 #include <machine/armreg.h> 51 #include <machine/cpu.h> 52 #include <machine/cpufunc.h> 53 #include <machine/debug_monitor.h> 54 #include <machine/smp.h> 55 #include <machine/pcb.h> 56 #include <machine/physmem.h> 57 #include <machine/intr.h> 58 #include <machine/vmparam.h> 59 #ifdef VFP 60 #include <machine/vfp.h> 61 #endif 62 #ifdef CPU_MV_PJ4B 63 #include <arm/mv/mvwin.h> 64 #endif 65 66 /* used to hold the AP's until we are ready to release them */ 67 struct mtx ap_boot_mtx; 68 struct pcb stoppcbs[MAXCPU]; 69 70 /* # of Applications processors */ 71 volatile int mp_naps; 72 73 /* Set to 1 once we're ready to let the APs out of the pen. */ 74 volatile int aps_ready = 0; 75 76 void set_stackptrs(int cpu); 77 78 /* Temporary variables for init_secondary() */ 79 void *dpcpu[MAXCPU - 1]; 80 81 /* Determine if we running MP machine */ 82 int 83 cpu_mp_probe(void) 84 { 85 86 KASSERT(mp_ncpus != 0, ("cpu_mp_probe: mp_ncpus is unset")); 87 88 CPU_SETOF(0, &all_cpus); 89 90 return (mp_ncpus > 1); 91 } 92 93 /* Start Application Processor via platform specific function */ 94 static int 95 check_ap(void) 96 { 97 uint32_t ms; 98 99 for (ms = 0; ms < 2000; ++ms) { 100 if ((mp_naps + 1) == mp_ncpus) 101 return (0); /* success */ 102 else 103 DELAY(1000); 104 } 105 106 return (-2); 107 } 108 109 /* Initialize and fire up non-boot processors */ 110 void 111 cpu_mp_start(void) 112 { 113 int error, i; 114 115 mtx_init(&ap_boot_mtx, "ap boot", NULL, MTX_SPIN); 116 117 /* Reserve memory for application processors */ 118 for(i = 0; i < (mp_ncpus - 1); i++) 119 dpcpu[i] = (void *)kmem_malloc(DPCPU_SIZE, M_WAITOK | M_ZERO); 120 121 dcache_wbinv_poc_all(); 122 123 /* Initialize boot code and start up processors */ 124 platform_mp_start_ap(); 125 126 /* Check if ap's started properly */ 127 error = check_ap(); 128 if (error) 129 printf("WARNING: Some AP's failed to start\n"); 130 else 131 for (i = 1; i < mp_ncpus; i++) 132 CPU_SET(i, &all_cpus); 133 } 134 135 /* Introduce rest of cores to the world */ 136 void 137 cpu_mp_announce(void) 138 { 139 140 } 141 142 extern vm_paddr_t pmap_pa; 143 void 144 init_secondary(int cpu) 145 { 146 struct pcpu *pc; 147 uint32_t loop_counter; 148 149 pmap_set_tex(); 150 cpuinfo_reinit_mmu(pmap_kern_ttb); 151 cpu_setup(); 152 153 /* Provide stack pointers for other processor modes. */ 154 set_stackptrs(cpu); 155 156 enable_interrupts(PSR_A); 157 pc = &__pcpu[cpu]; 158 159 /* 160 * pcpu_init() updates queue, so it should not be executed in parallel 161 * on several cores 162 */ 163 while(mp_naps < (cpu - 1)) 164 ; 165 166 pcpu_init(pc, cpu, sizeof(struct pcpu)); 167 dpcpu_init(dpcpu[cpu - 1], cpu); 168 #if __ARM_ARCH >= 6 && defined(DDB) 169 dbg_monitor_init_secondary(); 170 #endif 171 /* Signal our startup to BSP */ 172 atomic_add_rel_32(&mp_naps, 1); 173 174 /* Spin until the BSP releases the APs */ 175 while (!atomic_load_acq_int(&aps_ready)) { 176 #if __ARM_ARCH >= 7 177 __asm __volatile("wfe"); 178 #endif 179 } 180 181 /* Initialize curthread */ 182 KASSERT(PCPU_GET(idlethread) != NULL, ("no idle thread")); 183 pc->pc_curthread = pc->pc_idlethread; 184 pc->pc_curpcb = pc->pc_idlethread->td_pcb; 185 set_curthread(pc->pc_idlethread); 186 #ifdef VFP 187 vfp_init(); 188 #endif 189 190 /* Configure the interrupt controller */ 191 intr_pic_init_secondary(); 192 193 /* Apply possible BP hardening */ 194 cpuinfo_init_bp_hardening(); 195 196 mtx_lock_spin(&ap_boot_mtx); 197 198 atomic_add_rel_32(&smp_cpus, 1); 199 200 if (smp_cpus == mp_ncpus) { 201 /* enable IPI's, tlb shootdown, freezes etc */ 202 atomic_store_rel_int(&smp_started, 1); 203 } 204 205 mtx_unlock_spin(&ap_boot_mtx); 206 207 enable_interrupts(PSR_I); 208 209 loop_counter = 0; 210 while (smp_started == 0) { 211 DELAY(100); 212 loop_counter++; 213 if (loop_counter == 1000) 214 CTR0(KTR_SMP, "AP still wait for smp_started"); 215 } 216 /* Start per-CPU event timers. */ 217 cpu_initclocks_ap(); 218 219 CTR0(KTR_SMP, "go into scheduler"); 220 221 /* Enter the scheduler */ 222 sched_throw(NULL); 223 224 panic("scheduler returned us to %s", __func__); 225 /* NOTREACHED */ 226 } 227 228 static void 229 ipi_rendezvous(void *dummy __unused) 230 { 231 232 CTR0(KTR_SMP, "IPI_RENDEZVOUS"); 233 smp_rendezvous_action(); 234 } 235 236 static void 237 ipi_ast(void *dummy __unused) 238 { 239 240 CTR0(KTR_SMP, "IPI_AST"); 241 } 242 243 static void 244 ipi_stop(void *dummy __unused) 245 { 246 u_int cpu; 247 248 /* 249 * IPI_STOP_HARD is mapped to IPI_STOP. 250 */ 251 CTR0(KTR_SMP, "IPI_STOP or IPI_STOP_HARD"); 252 253 cpu = PCPU_GET(cpuid); 254 savectx(&stoppcbs[cpu]); 255 256 /* 257 * CPUs are stopped when entering the debugger and at 258 * system shutdown, both events which can precede a 259 * panic dump. For the dump to be correct, all caches 260 * must be flushed and invalidated, but on ARM there's 261 * no way to broadcast a wbinv_all to other cores. 262 * Instead, we have each core do the local wbinv_all as 263 * part of stopping the core. The core requesting the 264 * stop will do the l2 cache flush after all other cores 265 * have done their l1 flushes and stopped. 266 */ 267 dcache_wbinv_poc_all(); 268 269 /* Indicate we are stopped */ 270 CPU_SET_ATOMIC(cpu, &stopped_cpus); 271 272 /* Wait for restart */ 273 while (!CPU_ISSET(cpu, &started_cpus)) 274 cpu_spinwait(); 275 276 CPU_CLR_ATOMIC(cpu, &started_cpus); 277 CPU_CLR_ATOMIC(cpu, &stopped_cpus); 278 #ifdef DDB 279 dbg_resume_dbreg(); 280 #endif 281 CTR0(KTR_SMP, "IPI_STOP (restart)"); 282 } 283 284 static void 285 ipi_preempt(void *arg) 286 { 287 struct trapframe *oldframe; 288 struct thread *td; 289 290 critical_enter(); 291 td = curthread; 292 td->td_intr_nesting_level++; 293 oldframe = td->td_intr_frame; 294 td->td_intr_frame = (struct trapframe *)arg; 295 296 CTR1(KTR_SMP, "%s: IPI_PREEMPT", __func__); 297 sched_preempt(td); 298 299 td->td_intr_frame = oldframe; 300 td->td_intr_nesting_level--; 301 critical_exit(); 302 } 303 304 static void 305 ipi_hardclock(void *arg) 306 { 307 struct trapframe *oldframe; 308 struct thread *td; 309 310 critical_enter(); 311 td = curthread; 312 td->td_intr_nesting_level++; 313 oldframe = td->td_intr_frame; 314 td->td_intr_frame = (struct trapframe *)arg; 315 316 CTR1(KTR_SMP, "%s: IPI_HARDCLOCK", __func__); 317 hardclockintr(); 318 319 td->td_intr_frame = oldframe; 320 td->td_intr_nesting_level--; 321 critical_exit(); 322 } 323 324 static void 325 release_aps(void *dummy __unused) 326 { 327 uint32_t loop_counter; 328 329 if (mp_ncpus == 1) 330 return; 331 332 intr_pic_ipi_setup(IPI_RENDEZVOUS, "rendezvous", ipi_rendezvous, NULL); 333 intr_pic_ipi_setup(IPI_AST, "ast", ipi_ast, NULL); 334 intr_pic_ipi_setup(IPI_STOP, "stop", ipi_stop, NULL); 335 intr_pic_ipi_setup(IPI_PREEMPT, "preempt", ipi_preempt, NULL); 336 intr_pic_ipi_setup(IPI_HARDCLOCK, "hardclock", ipi_hardclock, NULL); 337 338 atomic_store_rel_int(&aps_ready, 1); 339 /* Wake the other threads up */ 340 dsb(); 341 sev(); 342 343 printf("Release APs\n"); 344 345 for (loop_counter = 0; loop_counter < 2000; loop_counter++) { 346 if (smp_started) 347 return; 348 DELAY(1000); 349 } 350 printf("AP's not started\n"); 351 } 352 353 SYSINIT(start_aps, SI_SUB_SMP, SI_ORDER_FIRST, release_aps, NULL); 354 355 struct cpu_group * 356 cpu_topo(void) 357 { 358 359 return (smp_topo_1level(CG_SHARE_L2, mp_ncpus, 0)); 360 } 361 362 void 363 cpu_mp_setmaxid(void) 364 { 365 366 platform_mp_setmaxid(); 367 } 368 369 /* Sending IPI */ 370 void 371 ipi_all_but_self(u_int ipi) 372 { 373 cpuset_t other_cpus; 374 375 other_cpus = all_cpus; 376 CPU_CLR(PCPU_GET(cpuid), &other_cpus); 377 CTR2(KTR_SMP, "%s: ipi: %x", __func__, ipi); 378 intr_ipi_send(other_cpus, ipi); 379 } 380 381 void 382 ipi_cpu(int cpu, u_int ipi) 383 { 384 cpuset_t cpus; 385 386 CPU_ZERO(&cpus); 387 CPU_SET(cpu, &cpus); 388 389 CTR3(KTR_SMP, "%s: cpu: %d, ipi: %x", __func__, cpu, ipi); 390 intr_ipi_send(cpus, ipi); 391 } 392 393 void 394 ipi_selected(cpuset_t cpus, u_int ipi) 395 { 396 397 CTR2(KTR_SMP, "%s: ipi: %x", __func__, ipi); 398 intr_ipi_send(cpus, ipi); 399 } 400