1 /*- 2 * Copyright (c) 2011 The FreeBSD Foundation 3 * All rights reserved. 4 * 5 * Developed by Ben Gray <ben.r.gray@gmail.com> 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the company nor the name of the author may be used to 16 * endorse or promote products derived from this software without specific 17 * prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 */ 31 32 /** 33 * The ARM Cortex-A9 core can support a global timer plus a private and 34 * watchdog timer per core. This driver reserves memory and interrupt 35 * resources for accessing both timer register sets, these resources are 36 * stored globally and used to setup the timecount and eventtimer. 37 * 38 * The timecount timer uses the global 64-bit counter, whereas the 39 * per-CPU eventtimer uses the private 32-bit counters. 40 * 41 * 42 * REF: ARM Cortex-A9 MPCore, Technical Reference Manual (rev. r2p2) 43 */ 44 45 #include <sys/cdefs.h> 46 __FBSDID("$FreeBSD$"); 47 48 #include <sys/param.h> 49 #include <sys/systm.h> 50 #include <sys/bus.h> 51 #include <sys/kernel.h> 52 #include <sys/module.h> 53 #include <sys/malloc.h> 54 #include <sys/rman.h> 55 #include <sys/timeet.h> 56 #include <sys/timetc.h> 57 #include <sys/watchdog.h> 58 #include <machine/bus.h> 59 #include <machine/cpu.h> 60 #include <machine/intr.h> 61 62 #include <dev/fdt/fdt_common.h> 63 #include <dev/ofw/openfirm.h> 64 #include <dev/ofw/ofw_bus.h> 65 #include <dev/ofw/ofw_bus_subr.h> 66 67 #include <machine/bus.h> 68 #include <machine/fdt.h> 69 70 #include <arm/arm/mpcore_timervar.h> 71 72 /* Private (per-CPU) timer register map */ 73 #define PRV_TIMER_LOAD 0x0000 74 #define PRV_TIMER_COUNT 0x0004 75 #define PRV_TIMER_CTRL 0x0008 76 #define PRV_TIMER_INTR 0x000C 77 78 #define PRV_TIMER_CTR_PRESCALER_SHIFT 8 79 #define PRV_TIMER_CTRL_IRQ_ENABLE (1UL << 2) 80 #define PRV_TIMER_CTRL_AUTO_RELOAD (1UL << 1) 81 #define PRV_TIMER_CTRL_TIMER_ENABLE (1UL << 0) 82 83 #define PRV_TIMER_INTR_EVENT (1UL << 0) 84 85 /* Global timer register map */ 86 #define GBL_TIMER_COUNT_LOW 0x0000 87 #define GBL_TIMER_COUNT_HIGH 0x0004 88 #define GBL_TIMER_CTRL 0x0008 89 #define GBL_TIMER_INTR 0x000C 90 91 #define GBL_TIMER_CTR_PRESCALER_SHIFT 8 92 #define GBL_TIMER_CTRL_AUTO_INC (1UL << 3) 93 #define GBL_TIMER_CTRL_IRQ_ENABLE (1UL << 2) 94 #define GBL_TIMER_CTRL_COMP_ENABLE (1UL << 1) 95 #define GBL_TIMER_CTRL_TIMER_ENABLE (1UL << 0) 96 97 #define GBL_TIMER_INTR_EVENT (1UL << 0) 98 99 struct arm_tmr_softc { 100 struct resource * tmr_res[4]; 101 bus_space_tag_t prv_bst; 102 bus_space_tag_t gbl_bst; 103 bus_space_handle_t prv_bsh; 104 bus_space_handle_t gbl_bsh; 105 uint64_t clkfreq; 106 struct eventtimer et; 107 }; 108 109 static struct resource_spec arm_tmr_spec[] = { 110 { SYS_RES_MEMORY, 0, RF_ACTIVE }, /* Global registers */ 111 { SYS_RES_IRQ, 0, RF_ACTIVE }, /* Global timer interrupt (unused) */ 112 { SYS_RES_MEMORY, 1, RF_ACTIVE }, /* Private (per-CPU) registers */ 113 { SYS_RES_IRQ, 1, RF_ACTIVE }, /* Private timer interrupt */ 114 { -1, 0 } 115 }; 116 117 static struct arm_tmr_softc *arm_tmr_sc = NULL; 118 119 static uint64_t platform_arm_tmr_freq = 0; 120 121 #define tmr_prv_read_4(reg) \ 122 bus_space_read_4(arm_tmr_sc->prv_bst, arm_tmr_sc->prv_bsh, reg) 123 #define tmr_prv_write_4(reg, val) \ 124 bus_space_write_4(arm_tmr_sc->prv_bst, arm_tmr_sc->prv_bsh, reg, val) 125 #define tmr_gbl_read_4(reg) \ 126 bus_space_read_4(arm_tmr_sc->gbl_bst, arm_tmr_sc->gbl_bsh, reg) 127 #define tmr_gbl_write_4(reg, val) \ 128 bus_space_write_4(arm_tmr_sc->gbl_bst, arm_tmr_sc->gbl_bsh, reg, val) 129 130 131 static timecounter_get_t arm_tmr_get_timecount; 132 133 static struct timecounter arm_tmr_timecount = { 134 .tc_name = "MPCore", 135 .tc_get_timecount = arm_tmr_get_timecount, 136 .tc_poll_pps = NULL, 137 .tc_counter_mask = ~0u, 138 .tc_frequency = 0, 139 .tc_quality = 800, 140 }; 141 142 /** 143 * arm_tmr_get_timecount - reads the timecount (global) timer 144 * @tc: pointer to arm_tmr_timecount struct 145 * 146 * We only read the lower 32-bits, the timecount stuff only uses 32-bits 147 * so (for now?) ignore the upper 32-bits. 148 * 149 * RETURNS 150 * The lower 32-bits of the counter. 151 */ 152 static unsigned 153 arm_tmr_get_timecount(struct timecounter *tc) 154 { 155 return (tmr_gbl_read_4(GBL_TIMER_COUNT_LOW)); 156 } 157 158 /** 159 * arm_tmr_start - starts the eventtimer (private) timer 160 * @et: pointer to eventtimer struct 161 * @first: the number of seconds and fractional sections to trigger in 162 * @period: the period (in seconds and fractional sections) to set 163 * 164 * If the eventtimer is required to be in oneshot mode, period will be 165 * NULL and first will point to the time to trigger. If in periodic mode 166 * period will contain the time period and first may optionally contain 167 * the time for the first period. 168 * 169 * RETURNS 170 * Always returns 0 171 */ 172 static int 173 arm_tmr_start(struct eventtimer *et, sbintime_t first, sbintime_t period) 174 { 175 uint32_t load, count; 176 uint32_t ctrl; 177 178 tmr_prv_write_4(PRV_TIMER_CTRL, 0); 179 tmr_prv_write_4(PRV_TIMER_INTR, PRV_TIMER_INTR_EVENT); 180 181 ctrl = PRV_TIMER_CTRL_IRQ_ENABLE | PRV_TIMER_CTRL_TIMER_ENABLE; 182 183 if (period != 0) { 184 load = ((uint32_t)et->et_frequency * period) >> 32; 185 ctrl |= PRV_TIMER_CTRL_AUTO_RELOAD; 186 } else 187 load = 0; 188 189 if (first != 0) 190 count = (uint32_t)((et->et_frequency * first) >> 32); 191 else 192 count = load; 193 194 tmr_prv_write_4(PRV_TIMER_LOAD, load); 195 tmr_prv_write_4(PRV_TIMER_COUNT, count); 196 tmr_prv_write_4(PRV_TIMER_CTRL, ctrl); 197 198 return (0); 199 } 200 201 /** 202 * arm_tmr_stop - stops the eventtimer (private) timer 203 * @et: pointer to eventtimer struct 204 * 205 * Simply stops the private timer by clearing all bits in the ctrl register. 206 * 207 * RETURNS 208 * Always returns 0 209 */ 210 static int 211 arm_tmr_stop(struct eventtimer *et) 212 { 213 tmr_prv_write_4(PRV_TIMER_CTRL, 0); 214 tmr_prv_write_4(PRV_TIMER_INTR, PRV_TIMER_INTR_EVENT); 215 return (0); 216 } 217 218 /** 219 * arm_tmr_intr - ISR for the eventtimer (private) timer 220 * @arg: pointer to arm_tmr_softc struct 221 * 222 * Clears the event register and then calls the eventtimer callback. 223 * 224 * RETURNS 225 * Always returns FILTER_HANDLED 226 */ 227 static int 228 arm_tmr_intr(void *arg) 229 { 230 struct arm_tmr_softc *sc = (struct arm_tmr_softc *)arg; 231 232 tmr_prv_write_4(PRV_TIMER_INTR, PRV_TIMER_INTR_EVENT); 233 234 if (sc->et.et_active) 235 sc->et.et_event_cb(&sc->et, sc->et.et_arg); 236 237 return (FILTER_HANDLED); 238 } 239 240 241 242 243 /** 244 * arm_tmr_probe - timer probe routine 245 * @dev: new device 246 * 247 * The probe function returns success when probed with the fdt compatible 248 * string set to "arm,mpcore-timers". 249 * 250 * RETURNS 251 * BUS_PROBE_DEFAULT if the fdt device is compatible, otherwise ENXIO. 252 */ 253 static int 254 arm_tmr_probe(device_t dev) 255 { 256 257 if (!ofw_bus_status_okay(dev)) 258 return (ENXIO); 259 260 if (!ofw_bus_is_compatible(dev, "arm,mpcore-timers")) 261 return (ENXIO); 262 263 device_set_desc(dev, "ARM MPCore Timers"); 264 return (BUS_PROBE_DEFAULT); 265 } 266 267 /** 268 * arm_tmr_attach - attaches the timer to the simplebus 269 * @dev: new device 270 * 271 * Reserves memory and interrupt resources, stores the softc structure 272 * globally and registers both the timecount and eventtimer objects. 273 * 274 * RETURNS 275 * Zero on sucess or ENXIO if an error occuried. 276 */ 277 static int 278 arm_tmr_attach(device_t dev) 279 { 280 struct arm_tmr_softc *sc = device_get_softc(dev); 281 phandle_t node; 282 pcell_t clock; 283 void *ihl; 284 boolean_t fixed_freq; 285 286 if (arm_tmr_sc) 287 return (ENXIO); 288 289 if (platform_arm_tmr_freq == ARM_TMR_FREQUENCY_VARIES) { 290 fixed_freq = false; 291 } else { 292 fixed_freq = true; 293 if (platform_arm_tmr_freq != 0) { 294 sc->clkfreq = platform_arm_tmr_freq; 295 } else { 296 /* Get the base clock frequency */ 297 node = ofw_bus_get_node(dev); 298 if ((OF_getencprop(node, "clock-frequency", &clock, 299 sizeof(clock))) <= 0) { 300 device_printf(dev, "missing clock-frequency " 301 "attribute in FDT\n"); 302 return (ENXIO); 303 } 304 } 305 } 306 307 if (bus_alloc_resources(dev, arm_tmr_spec, sc->tmr_res)) { 308 device_printf(dev, "could not allocate resources\n"); 309 return (ENXIO); 310 } 311 312 /* Global timer interface */ 313 sc->gbl_bst = rman_get_bustag(sc->tmr_res[0]); 314 sc->gbl_bsh = rman_get_bushandle(sc->tmr_res[0]); 315 316 /* Private per-CPU timer interface */ 317 sc->prv_bst = rman_get_bustag(sc->tmr_res[2]); 318 sc->prv_bsh = rman_get_bushandle(sc->tmr_res[2]); 319 320 arm_tmr_sc = sc; 321 322 /* Disable both timers to start off */ 323 tmr_prv_write_4(PRV_TIMER_CTRL, 0x00000000); 324 tmr_gbl_write_4(GBL_TIMER_CTRL, 0x00000000); 325 326 if (bus_setup_intr(dev, sc->tmr_res[3], INTR_TYPE_CLK, arm_tmr_intr, 327 NULL, sc, &ihl) != 0) { 328 bus_release_resources(dev, arm_tmr_spec, sc->tmr_res); 329 device_printf(dev, "Unable to setup the clock irq handler.\n"); 330 return (ENXIO); 331 } 332 333 /* 334 * If the clock is fixed-frequency, setup and enable the global timer to 335 * use as the timecounter. If it's variable frequency it won't work as 336 * a timecounter. We also can't use it for DELAY(), so hopefully the 337 * platform provides its own implementation. If it doesn't, ours will 338 * get used, but since the frequency isn't set, it will only use the 339 * bogus loop counter. 340 */ 341 if (fixed_freq) { 342 tmr_gbl_write_4(GBL_TIMER_CTRL, GBL_TIMER_CTRL_TIMER_ENABLE); 343 arm_tmr_timecount.tc_frequency = sc->clkfreq; 344 tc_init(&arm_tmr_timecount); 345 } 346 347 /* 348 * Setup and register the eventtimer. Most event timers set their min 349 * and max period values to some value calculated from the clock 350 * frequency. We might not know yet what our runtime clock frequency 351 * will be, so we just use some safe values. A max of 2 seconds ensures 352 * that even if our base clock frequency is 2GHz (meaning a 4GHz CPU), 353 * we won't overflow our 32-bit timer count register. A min of 20 354 * nanoseconds is pretty much completely arbitrary. 355 */ 356 sc->et.et_name = "MPCore"; 357 sc->et.et_flags = ET_FLAGS_PERIODIC | ET_FLAGS_ONESHOT | ET_FLAGS_PERCPU; 358 sc->et.et_quality = 1000; 359 sc->et.et_frequency = sc->clkfreq; 360 sc->et.et_min_period = 20 * SBT_1NS; 361 sc->et.et_max_period = 2 * SBT_1S; 362 sc->et.et_start = arm_tmr_start; 363 sc->et.et_stop = arm_tmr_stop; 364 sc->et.et_priv = sc; 365 et_register(&sc->et); 366 367 return (0); 368 } 369 370 static device_method_t arm_tmr_methods[] = { 371 DEVMETHOD(device_probe, arm_tmr_probe), 372 DEVMETHOD(device_attach, arm_tmr_attach), 373 { 0, 0 } 374 }; 375 376 static driver_t arm_tmr_driver = { 377 "mp_tmr", 378 arm_tmr_methods, 379 sizeof(struct arm_tmr_softc), 380 }; 381 382 static devclass_t arm_tmr_devclass; 383 384 DRIVER_MODULE(mp_tmr, simplebus, arm_tmr_driver, arm_tmr_devclass, 0, 0); 385 386 /* 387 * Handle a change in clock frequency. The mpcore timer runs at half the CPU 388 * frequency. When the CPU frequency changes due to power-saving or thermal 389 * managment, the platform-specific code that causes the frequency change calls 390 * this routine to inform the clock driver, and we in turn inform the event 391 * timer system, which actually updates the value in et->frequency for us and 392 * reschedules the current event(s) in a way that's atomic with respect to 393 * start/stop/intr code that may be running on various CPUs at the time of the 394 * call. 395 * 396 * This routine can also be called by a platform's early init code. If the 397 * value passed is ARM_TMR_FREQUENCY_VARIES, that will cause the attach() code 398 * to register as an eventtimer, but not a timecounter. If the value passed in 399 * is any other non-zero value it is used as the fixed frequency for the timer. 400 */ 401 void 402 arm_tmr_change_frequency(uint64_t newfreq) 403 { 404 405 if (arm_tmr_sc == NULL) 406 platform_arm_tmr_freq = newfreq; 407 else 408 et_change_frequency(&arm_tmr_sc->et, newfreq); 409 } 410 411 /** 412 * DELAY - Delay for at least usec microseconds. 413 * @usec: number of microseconds to delay by 414 * 415 * This function is called all over the kernel and is suppose to provide a 416 * consistent delay. This function may also be called before the console 417 * is setup so no printf's can be called here. 418 * 419 * RETURNS: 420 * nothing 421 */ 422 static void __used /* Must emit function code for the weak ref below. */ 423 arm_tmr_DELAY(int usec) 424 { 425 int32_t counts_per_usec; 426 int32_t counts; 427 uint32_t first, last; 428 429 /* Check the timers are setup, if not just use a for loop for the meantime */ 430 if (arm_tmr_sc == NULL || arm_tmr_timecount.tc_frequency == 0) { 431 for (; usec > 0; usec--) 432 for (counts = 200; counts > 0; counts--) 433 cpufunc_nullop(); /* Prevent gcc from optimizing 434 * out the loop 435 */ 436 return; 437 } 438 439 /* Get the number of times to count */ 440 counts_per_usec = ((arm_tmr_timecount.tc_frequency / 1000000) + 1); 441 442 /* 443 * Clamp the timeout at a maximum value (about 32 seconds with 444 * a 66MHz clock). *Nobody* should be delay()ing for anywhere 445 * near that length of time and if they are, they should be hung 446 * out to dry. 447 */ 448 if (usec >= (0x80000000U / counts_per_usec)) 449 counts = (0x80000000U / counts_per_usec) - 1; 450 else 451 counts = usec * counts_per_usec; 452 453 first = tmr_gbl_read_4(GBL_TIMER_COUNT_LOW); 454 455 while (counts > 0) { 456 last = tmr_gbl_read_4(GBL_TIMER_COUNT_LOW); 457 counts -= (int32_t)(last - first); 458 first = last; 459 } 460 } 461 462 /* 463 * Supply a DELAY() implementation via weak linkage. A platform may want to use 464 * the mpcore per-cpu eventtimers but provide its own DELAY() routine, 465 * especially when the core frequency can change on the fly. 466 */ 467 __weak_reference(arm_tmr_DELAY, DELAY); 468 469