1 /*- 2 * Copyright (c) 2011 The FreeBSD Foundation 3 * All rights reserved. 4 * 5 * Developed by Ben Gray <ben.r.gray@gmail.com> 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the company nor the name of the author may be used to 16 * endorse or promote products derived from this software without specific 17 * prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 */ 31 32 /** 33 * The ARM Cortex-A9 core can support a global timer plus a private and 34 * watchdog timer per core. This driver reserves memory and interrupt 35 * resources for accessing both timer register sets, these resources are 36 * stored globally and used to setup the timecount and eventtimer. 37 * 38 * The timecount timer uses the global 64-bit counter, whereas the 39 * per-CPU eventtimer uses the private 32-bit counters. 40 * 41 * 42 * REF: ARM Cortex-A9 MPCore, Technical Reference Manual (rev. r2p2) 43 */ 44 45 #include <sys/cdefs.h> 46 __FBSDID("$FreeBSD$"); 47 48 #include <sys/param.h> 49 #include <sys/systm.h> 50 #include <sys/bus.h> 51 #include <sys/kernel.h> 52 #include <sys/module.h> 53 #include <sys/malloc.h> 54 #include <sys/rman.h> 55 #include <sys/timeet.h> 56 #include <sys/timetc.h> 57 #include <sys/watchdog.h> 58 #include <machine/bus.h> 59 #include <machine/cpu.h> 60 #include <machine/intr.h> 61 62 #include <dev/fdt/fdt_common.h> 63 #include <dev/ofw/openfirm.h> 64 #include <dev/ofw/ofw_bus.h> 65 #include <dev/ofw/ofw_bus_subr.h> 66 67 #include <machine/bus.h> 68 #include <machine/fdt.h> 69 70 #include <arm/arm/mpcore_timervar.h> 71 72 /* Private (per-CPU) timer register map */ 73 #define PRV_TIMER_LOAD 0x0000 74 #define PRV_TIMER_COUNT 0x0004 75 #define PRV_TIMER_CTRL 0x0008 76 #define PRV_TIMER_INTR 0x000C 77 78 #define PRV_TIMER_CTR_PRESCALER_SHIFT 8 79 #define PRV_TIMER_CTRL_IRQ_ENABLE (1UL << 2) 80 #define PRV_TIMER_CTRL_AUTO_RELOAD (1UL << 1) 81 #define PRV_TIMER_CTRL_TIMER_ENABLE (1UL << 0) 82 83 #define PRV_TIMER_INTR_EVENT (1UL << 0) 84 85 /* Global timer register map */ 86 #define GBL_TIMER_COUNT_LOW 0x0000 87 #define GBL_TIMER_COUNT_HIGH 0x0004 88 #define GBL_TIMER_CTRL 0x0008 89 #define GBL_TIMER_INTR 0x000C 90 91 #define GBL_TIMER_CTR_PRESCALER_SHIFT 8 92 #define GBL_TIMER_CTRL_AUTO_INC (1UL << 3) 93 #define GBL_TIMER_CTRL_IRQ_ENABLE (1UL << 2) 94 #define GBL_TIMER_CTRL_COMP_ENABLE (1UL << 1) 95 #define GBL_TIMER_CTRL_TIMER_ENABLE (1UL << 0) 96 97 #define GBL_TIMER_INTR_EVENT (1UL << 0) 98 99 struct arm_tmr_softc { 100 device_t dev; 101 int irqrid; 102 int memrid; 103 struct resource * gbl_mem; 104 struct resource * prv_mem; 105 struct resource * prv_irq; 106 uint64_t clkfreq; 107 struct eventtimer et; 108 }; 109 110 static struct eventtimer *arm_tmr_et; 111 static struct timecounter *arm_tmr_tc; 112 static uint64_t arm_tmr_freq; 113 static boolean_t arm_tmr_freq_varies; 114 115 #define tmr_prv_read_4(sc, reg) bus_read_4((sc)->prv_mem, reg) 116 #define tmr_prv_write_4(sc, reg, val) bus_write_4((sc)->prv_mem, reg, val) 117 #define tmr_gbl_read_4(sc, reg) bus_read_4((sc)->gbl_mem, reg) 118 #define tmr_gbl_write_4(sc, reg, val) bus_write_4((sc)->gbl_mem, reg, val) 119 120 static timecounter_get_t arm_tmr_get_timecount; 121 122 static struct timecounter arm_tmr_timecount = { 123 .tc_name = "MPCore", 124 .tc_get_timecount = arm_tmr_get_timecount, 125 .tc_poll_pps = NULL, 126 .tc_counter_mask = ~0u, 127 .tc_frequency = 0, 128 .tc_quality = 800, 129 }; 130 131 #define TMR_GBL 0x01 132 #define TMR_PRV 0x02 133 #define TMR_BOTH (TMR_GBL | TMR_PRV) 134 #define TMR_NONE 0 135 136 static struct ofw_compat_data compat_data[] = { 137 {"arm,mpcore-timers", TMR_BOTH}, /* Non-standard, FreeBSD. */ 138 {"arm,cortex-a9-global-timer", TMR_GBL}, 139 {"arm,cortex-a5-global-timer", TMR_GBL}, 140 {"arm,cortex-a9-twd-timer", TMR_PRV}, 141 {"arm,cortex-a5-twd-timer", TMR_PRV}, 142 {"arm,arm11mp-twd-timer", TMR_PRV}, 143 {NULL, TMR_NONE} 144 }; 145 146 /** 147 * arm_tmr_get_timecount - reads the timecount (global) timer 148 * @tc: pointer to arm_tmr_timecount struct 149 * 150 * We only read the lower 32-bits, the timecount stuff only uses 32-bits 151 * so (for now?) ignore the upper 32-bits. 152 * 153 * RETURNS 154 * The lower 32-bits of the counter. 155 */ 156 static unsigned 157 arm_tmr_get_timecount(struct timecounter *tc) 158 { 159 struct arm_tmr_softc *sc; 160 161 sc = tc->tc_priv; 162 return (tmr_gbl_read_4(sc, GBL_TIMER_COUNT_LOW)); 163 } 164 165 /** 166 * arm_tmr_start - starts the eventtimer (private) timer 167 * @et: pointer to eventtimer struct 168 * @first: the number of seconds and fractional sections to trigger in 169 * @period: the period (in seconds and fractional sections) to set 170 * 171 * If the eventtimer is required to be in oneshot mode, period will be 172 * NULL and first will point to the time to trigger. If in periodic mode 173 * period will contain the time period and first may optionally contain 174 * the time for the first period. 175 * 176 * RETURNS 177 * Always returns 0 178 */ 179 static int 180 arm_tmr_start(struct eventtimer *et, sbintime_t first, sbintime_t period) 181 { 182 struct arm_tmr_softc *sc; 183 uint32_t load, count; 184 uint32_t ctrl; 185 186 sc = et->et_priv; 187 tmr_prv_write_4(sc, PRV_TIMER_CTRL, 0); 188 tmr_prv_write_4(sc, PRV_TIMER_INTR, PRV_TIMER_INTR_EVENT); 189 190 ctrl = PRV_TIMER_CTRL_IRQ_ENABLE | PRV_TIMER_CTRL_TIMER_ENABLE; 191 192 if (period != 0) { 193 load = ((uint32_t)et->et_frequency * period) >> 32; 194 ctrl |= PRV_TIMER_CTRL_AUTO_RELOAD; 195 } else 196 load = 0; 197 198 if (first != 0) 199 count = (uint32_t)((et->et_frequency * first) >> 32); 200 else 201 count = load; 202 203 tmr_prv_write_4(sc, PRV_TIMER_LOAD, load); 204 tmr_prv_write_4(sc, PRV_TIMER_COUNT, count); 205 tmr_prv_write_4(sc, PRV_TIMER_CTRL, ctrl); 206 207 return (0); 208 } 209 210 /** 211 * arm_tmr_stop - stops the eventtimer (private) timer 212 * @et: pointer to eventtimer struct 213 * 214 * Simply stops the private timer by clearing all bits in the ctrl register. 215 * 216 * RETURNS 217 * Always returns 0 218 */ 219 static int 220 arm_tmr_stop(struct eventtimer *et) 221 { 222 struct arm_tmr_softc *sc; 223 224 sc = et->et_priv; 225 tmr_prv_write_4(sc, PRV_TIMER_CTRL, 0); 226 tmr_prv_write_4(sc, PRV_TIMER_INTR, PRV_TIMER_INTR_EVENT); 227 return (0); 228 } 229 230 /** 231 * arm_tmr_intr - ISR for the eventtimer (private) timer 232 * @arg: pointer to arm_tmr_softc struct 233 * 234 * Clears the event register and then calls the eventtimer callback. 235 * 236 * RETURNS 237 * Always returns FILTER_HANDLED 238 */ 239 static int 240 arm_tmr_intr(void *arg) 241 { 242 struct arm_tmr_softc *sc; 243 244 sc = arg; 245 tmr_prv_write_4(sc, PRV_TIMER_INTR, PRV_TIMER_INTR_EVENT); 246 if (sc->et.et_active) 247 sc->et.et_event_cb(&sc->et, sc->et.et_arg); 248 return (FILTER_HANDLED); 249 } 250 251 252 253 254 /** 255 * arm_tmr_probe - timer probe routine 256 * @dev: new device 257 * 258 * The probe function returns success when probed with the fdt compatible 259 * string set to "arm,mpcore-timers". 260 * 261 * RETURNS 262 * BUS_PROBE_DEFAULT if the fdt device is compatible, otherwise ENXIO. 263 */ 264 static int 265 arm_tmr_probe(device_t dev) 266 { 267 268 if (!ofw_bus_status_okay(dev)) 269 return (ENXIO); 270 271 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == TMR_NONE) 272 return (ENXIO); 273 274 device_set_desc(dev, "ARM MPCore Timers"); 275 return (BUS_PROBE_DEFAULT); 276 } 277 278 static int 279 attach_tc(struct arm_tmr_softc *sc) 280 { 281 int rid; 282 283 if (arm_tmr_tc != NULL) 284 return (EBUSY); 285 286 rid = sc->memrid; 287 sc->gbl_mem = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, &rid, 288 RF_ACTIVE); 289 if (sc->gbl_mem == NULL) { 290 device_printf(sc->dev, "could not allocate gbl mem resources\n"); 291 return (ENXIO); 292 } 293 tmr_gbl_write_4(sc, GBL_TIMER_CTRL, 0x00000000); 294 295 arm_tmr_timecount.tc_frequency = sc->clkfreq; 296 arm_tmr_timecount.tc_priv = sc; 297 tc_init(&arm_tmr_timecount); 298 arm_tmr_tc = &arm_tmr_timecount; 299 300 tmr_gbl_write_4(sc, GBL_TIMER_CTRL, GBL_TIMER_CTRL_TIMER_ENABLE); 301 302 return (0); 303 } 304 305 static int 306 attach_et(struct arm_tmr_softc *sc) 307 { 308 void *ihl; 309 int irid, mrid; 310 311 if (arm_tmr_et != NULL) 312 return (EBUSY); 313 314 mrid = sc->memrid; 315 sc->prv_mem = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, &mrid, 316 RF_ACTIVE); 317 if (sc->prv_mem == NULL) { 318 device_printf(sc->dev, "could not allocate prv mem resources\n"); 319 return (ENXIO); 320 } 321 tmr_prv_write_4(sc, PRV_TIMER_CTRL, 0x00000000); 322 323 irid = sc->irqrid; 324 sc->prv_irq = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, &irid, RF_ACTIVE); 325 if (sc->prv_irq == NULL) { 326 bus_release_resource(sc->dev, SYS_RES_MEMORY, mrid, sc->prv_mem); 327 device_printf(sc->dev, "could not allocate prv irq resources\n"); 328 return (ENXIO); 329 } 330 331 if (bus_setup_intr(sc->dev, sc->prv_irq, INTR_TYPE_CLK, arm_tmr_intr, 332 NULL, sc, &ihl) != 0) { 333 bus_release_resource(sc->dev, SYS_RES_MEMORY, mrid, sc->prv_mem); 334 bus_release_resource(sc->dev, SYS_RES_IRQ, irid, sc->prv_irq); 335 device_printf(sc->dev, "unable to setup the et irq handler.\n"); 336 return (ENXIO); 337 } 338 339 /* 340 * Setup and register the eventtimer. Most event timers set their min 341 * and max period values to some value calculated from the clock 342 * frequency. We might not know yet what our runtime clock frequency 343 * will be, so we just use some safe values. A max of 2 seconds ensures 344 * that even if our base clock frequency is 2GHz (meaning a 4GHz CPU), 345 * we won't overflow our 32-bit timer count register. A min of 20 346 * nanoseconds is pretty much completely arbitrary. 347 */ 348 sc->et.et_name = "MPCore"; 349 sc->et.et_flags = ET_FLAGS_PERIODIC | ET_FLAGS_ONESHOT | ET_FLAGS_PERCPU; 350 sc->et.et_quality = 1000; 351 sc->et.et_frequency = sc->clkfreq; 352 sc->et.et_min_period = 20 * SBT_1NS; 353 sc->et.et_max_period = 2 * SBT_1S; 354 sc->et.et_start = arm_tmr_start; 355 sc->et.et_stop = arm_tmr_stop; 356 sc->et.et_priv = sc; 357 et_register(&sc->et); 358 arm_tmr_et = &sc->et; 359 360 return (0); 361 } 362 363 /** 364 * arm_tmr_attach - attaches the timer to the simplebus 365 * @dev: new device 366 * 367 * Reserves memory and interrupt resources, stores the softc structure 368 * globally and registers both the timecount and eventtimer objects. 369 * 370 * RETURNS 371 * Zero on sucess or ENXIO if an error occuried. 372 */ 373 static int 374 arm_tmr_attach(device_t dev) 375 { 376 struct arm_tmr_softc *sc; 377 phandle_t node; 378 pcell_t clock; 379 int et_err, tc_err, tmrtype; 380 381 sc = device_get_softc(dev); 382 sc->dev = dev; 383 384 if (arm_tmr_freq_varies) { 385 sc->clkfreq = arm_tmr_freq; 386 } else { 387 if (arm_tmr_freq != 0) { 388 sc->clkfreq = arm_tmr_freq; 389 } else { 390 /* Get the base clock frequency */ 391 node = ofw_bus_get_node(dev); 392 if ((OF_getencprop(node, "clock-frequency", &clock, 393 sizeof(clock))) <= 0) { 394 device_printf(dev, "missing clock-frequency " 395 "attribute in FDT\n"); 396 return (ENXIO); 397 } 398 sc->clkfreq = clock; 399 } 400 } 401 402 tmrtype = ofw_bus_search_compatible(dev, compat_data)->ocd_data; 403 tc_err = ENXIO; 404 et_err = ENXIO; 405 406 /* 407 * If we're handling the global timer and it is fixed-frequency, set it 408 * up to use as a timecounter. If it's variable frequency it won't work 409 * as a timecounter. We also can't use it for DELAY(), so hopefully the 410 * platform provides its own implementation. If it doesn't, ours will 411 * get used, but since the frequency isn't set, it will only use the 412 * bogus loop counter. 413 */ 414 if (tmrtype & TMR_GBL) { 415 if (!arm_tmr_freq_varies) 416 tc_err = attach_tc(sc); 417 else if (bootverbose) 418 device_printf(sc->dev, 419 "not using variable-frequency device as timecounter"); 420 sc->memrid++; 421 sc->irqrid++; 422 } 423 424 /* If we are handling the private timer, set it up as an eventtimer. */ 425 if (tmrtype & TMR_PRV) { 426 et_err = attach_et(sc); 427 } 428 429 /* 430 * If we didn't successfully set up a timecounter or eventtimer then we 431 * didn't actually attach at all, return error. 432 */ 433 if (tc_err != 0 && et_err != 0) { 434 return (ENXIO); 435 } 436 return (0); 437 } 438 439 static device_method_t arm_tmr_methods[] = { 440 DEVMETHOD(device_probe, arm_tmr_probe), 441 DEVMETHOD(device_attach, arm_tmr_attach), 442 { 0, 0 } 443 }; 444 445 static driver_t arm_tmr_driver = { 446 "mp_tmr", 447 arm_tmr_methods, 448 sizeof(struct arm_tmr_softc), 449 }; 450 451 static devclass_t arm_tmr_devclass; 452 453 EARLY_DRIVER_MODULE(mp_tmr, simplebus, arm_tmr_driver, arm_tmr_devclass, 0, 0, 454 BUS_PASS_TIMER + BUS_PASS_ORDER_MIDDLE); 455 EARLY_DRIVER_MODULE(mp_tmr, ofwbus, arm_tmr_driver, arm_tmr_devclass, 0, 0, 456 BUS_PASS_TIMER + BUS_PASS_ORDER_MIDDLE); 457 458 /* 459 * Handle a change in clock frequency. The mpcore timer runs at half the CPU 460 * frequency. When the CPU frequency changes due to power-saving or thermal 461 * managment, the platform-specific code that causes the frequency change calls 462 * this routine to inform the clock driver, and we in turn inform the event 463 * timer system, which actually updates the value in et->frequency for us and 464 * reschedules the current event(s) in a way that's atomic with respect to 465 * start/stop/intr code that may be running on various CPUs at the time of the 466 * call. 467 * 468 * This routine can also be called by a platform's early init code. If the 469 * value passed is ARM_TMR_FREQUENCY_VARIES, that will cause the attach() code 470 * to register as an eventtimer, but not a timecounter. If the value passed in 471 * is any other non-zero value it is used as the fixed frequency for the timer. 472 */ 473 void 474 arm_tmr_change_frequency(uint64_t newfreq) 475 { 476 477 if (newfreq == ARM_TMR_FREQUENCY_VARIES) { 478 arm_tmr_freq_varies = true; 479 return; 480 } 481 482 arm_tmr_freq = newfreq; 483 if (arm_tmr_et != NULL) 484 et_change_frequency(arm_tmr_et, newfreq); 485 } 486 487 /** 488 * DELAY - Delay for at least usec microseconds. 489 * @usec: number of microseconds to delay by 490 * 491 * This function is called all over the kernel and is suppose to provide a 492 * consistent delay. This function may also be called before the console 493 * is setup so no printf's can be called here. 494 * 495 * RETURNS: 496 * nothing 497 */ 498 static void __used /* Must emit function code for the weak ref below. */ 499 arm_tmr_DELAY(int usec) 500 { 501 struct arm_tmr_softc *sc; 502 int32_t counts_per_usec; 503 int32_t counts; 504 uint32_t first, last; 505 506 /* Check the timers are setup, if not just use a for loop for the meantime */ 507 if (arm_tmr_tc == NULL || arm_tmr_timecount.tc_frequency == 0) { 508 for (; usec > 0; usec--) 509 for (counts = 200; counts > 0; counts--) 510 cpufunc_nullop(); /* Prevent gcc from optimizing 511 * out the loop 512 */ 513 return; 514 } 515 516 sc = arm_tmr_tc->tc_priv; 517 518 /* Get the number of times to count */ 519 counts_per_usec = ((arm_tmr_timecount.tc_frequency / 1000000) + 1); 520 521 /* 522 * Clamp the timeout at a maximum value (about 32 seconds with 523 * a 66MHz clock). *Nobody* should be delay()ing for anywhere 524 * near that length of time and if they are, they should be hung 525 * out to dry. 526 */ 527 if (usec >= (0x80000000U / counts_per_usec)) 528 counts = (0x80000000U / counts_per_usec) - 1; 529 else 530 counts = usec * counts_per_usec; 531 532 first = tmr_gbl_read_4(sc, GBL_TIMER_COUNT_LOW); 533 534 while (counts > 0) { 535 last = tmr_gbl_read_4(sc, GBL_TIMER_COUNT_LOW); 536 counts -= (int32_t)(last - first); 537 first = last; 538 } 539 } 540 541 /* 542 * Supply a DELAY() implementation via weak linkage. A platform may want to use 543 * the mpcore per-cpu eventtimers but provide its own DELAY() routine, 544 * especially when the core frequency can change on the fly. 545 */ 546 __weak_reference(arm_tmr_DELAY, DELAY); 547 548