1 /*- 2 * Copyright (c) 2011 The FreeBSD Foundation 3 * All rights reserved. 4 * 5 * Developed by Ben Gray <ben.r.gray@gmail.com> 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the company nor the name of the author may be used to 16 * endorse or promote products derived from this software without specific 17 * prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 */ 31 32 /** 33 * The ARM Cortex-A9 core can support a global timer plus a private and 34 * watchdog timer per core. This driver reserves memory and interrupt 35 * resources for accessing both timer register sets, these resources are 36 * stored globally and used to setup the timecount and eventtimer. 37 * 38 * The timecount timer uses the global 64-bit counter, whereas the 39 * per-CPU eventtimer uses the private 32-bit counters. 40 * 41 * 42 * REF: ARM Cortex-A9 MPCore, Technical Reference Manual (rev. r2p2) 43 */ 44 45 #include <sys/cdefs.h> 46 __FBSDID("$FreeBSD$"); 47 48 #include <sys/param.h> 49 #include <sys/systm.h> 50 #include <sys/bus.h> 51 #include <sys/kernel.h> 52 #include <sys/module.h> 53 #include <sys/malloc.h> 54 #include <sys/rman.h> 55 #include <sys/timeet.h> 56 #include <sys/timetc.h> 57 #include <sys/watchdog.h> 58 #include <machine/bus.h> 59 #include <machine/cpu.h> 60 #include <machine/intr.h> 61 62 #ifdef MULTIDELAY 63 #include <machine/machdep.h> /* For arm_set_delay */ 64 #endif 65 66 #include <dev/ofw/openfirm.h> 67 #include <dev/ofw/ofw_bus.h> 68 #include <dev/ofw/ofw_bus_subr.h> 69 70 #include <machine/bus.h> 71 72 #include <arm/arm/mpcore_timervar.h> 73 74 #if defined(PLATFORM) && !defined(MULTIDELAY) 75 #error The MPCore Timer driver requires MULTIDELAY when building with PLATFORM 76 #endif 77 78 /* Private (per-CPU) timer register map */ 79 #define PRV_TIMER_LOAD 0x0000 80 #define PRV_TIMER_COUNT 0x0004 81 #define PRV_TIMER_CTRL 0x0008 82 #define PRV_TIMER_INTR 0x000C 83 84 #define PRV_TIMER_CTR_PRESCALER_SHIFT 8 85 #define PRV_TIMER_CTRL_IRQ_ENABLE (1UL << 2) 86 #define PRV_TIMER_CTRL_AUTO_RELOAD (1UL << 1) 87 #define PRV_TIMER_CTRL_TIMER_ENABLE (1UL << 0) 88 89 #define PRV_TIMER_INTR_EVENT (1UL << 0) 90 91 /* Global timer register map */ 92 #define GBL_TIMER_COUNT_LOW 0x0000 93 #define GBL_TIMER_COUNT_HIGH 0x0004 94 #define GBL_TIMER_CTRL 0x0008 95 #define GBL_TIMER_INTR 0x000C 96 97 #define GBL_TIMER_CTR_PRESCALER_SHIFT 8 98 #define GBL_TIMER_CTRL_AUTO_INC (1UL << 3) 99 #define GBL_TIMER_CTRL_IRQ_ENABLE (1UL << 2) 100 #define GBL_TIMER_CTRL_COMP_ENABLE (1UL << 1) 101 #define GBL_TIMER_CTRL_TIMER_ENABLE (1UL << 0) 102 103 #define GBL_TIMER_INTR_EVENT (1UL << 0) 104 105 struct arm_tmr_softc { 106 device_t dev; 107 int irqrid; 108 int memrid; 109 struct resource * gbl_mem; 110 struct resource * prv_mem; 111 struct resource * prv_irq; 112 uint64_t clkfreq; 113 struct eventtimer et; 114 }; 115 116 static struct eventtimer *arm_tmr_et; 117 static struct timecounter *arm_tmr_tc; 118 static uint64_t arm_tmr_freq; 119 static boolean_t arm_tmr_freq_varies; 120 121 #define tmr_prv_read_4(sc, reg) bus_read_4((sc)->prv_mem, reg) 122 #define tmr_prv_write_4(sc, reg, val) bus_write_4((sc)->prv_mem, reg, val) 123 #define tmr_gbl_read_4(sc, reg) bus_read_4((sc)->gbl_mem, reg) 124 #define tmr_gbl_write_4(sc, reg, val) bus_write_4((sc)->gbl_mem, reg, val) 125 126 static void arm_tmr_delay(int, void *); 127 128 static timecounter_get_t arm_tmr_get_timecount; 129 130 static struct timecounter arm_tmr_timecount = { 131 .tc_name = "MPCore", 132 .tc_get_timecount = arm_tmr_get_timecount, 133 .tc_poll_pps = NULL, 134 .tc_counter_mask = ~0u, 135 .tc_frequency = 0, 136 .tc_quality = 800, 137 }; 138 139 #define TMR_GBL 0x01 140 #define TMR_PRV 0x02 141 #define TMR_BOTH (TMR_GBL | TMR_PRV) 142 #define TMR_NONE 0 143 144 static struct ofw_compat_data compat_data[] = { 145 {"arm,mpcore-timers", TMR_BOTH}, /* Non-standard, FreeBSD. */ 146 {"arm,cortex-a9-global-timer", TMR_GBL}, 147 {"arm,cortex-a5-global-timer", TMR_GBL}, 148 {"arm,cortex-a9-twd-timer", TMR_PRV}, 149 {"arm,cortex-a5-twd-timer", TMR_PRV}, 150 {"arm,arm11mp-twd-timer", TMR_PRV}, 151 {NULL, TMR_NONE} 152 }; 153 154 /** 155 * arm_tmr_get_timecount - reads the timecount (global) timer 156 * @tc: pointer to arm_tmr_timecount struct 157 * 158 * We only read the lower 32-bits, the timecount stuff only uses 32-bits 159 * so (for now?) ignore the upper 32-bits. 160 * 161 * RETURNS 162 * The lower 32-bits of the counter. 163 */ 164 static unsigned 165 arm_tmr_get_timecount(struct timecounter *tc) 166 { 167 struct arm_tmr_softc *sc; 168 169 sc = tc->tc_priv; 170 return (tmr_gbl_read_4(sc, GBL_TIMER_COUNT_LOW)); 171 } 172 173 /** 174 * arm_tmr_start - starts the eventtimer (private) timer 175 * @et: pointer to eventtimer struct 176 * @first: the number of seconds and fractional sections to trigger in 177 * @period: the period (in seconds and fractional sections) to set 178 * 179 * If the eventtimer is required to be in oneshot mode, period will be 180 * NULL and first will point to the time to trigger. If in periodic mode 181 * period will contain the time period and first may optionally contain 182 * the time for the first period. 183 * 184 * RETURNS 185 * Always returns 0 186 */ 187 static int 188 arm_tmr_start(struct eventtimer *et, sbintime_t first, sbintime_t period) 189 { 190 struct arm_tmr_softc *sc; 191 uint32_t load, count; 192 uint32_t ctrl; 193 194 sc = et->et_priv; 195 tmr_prv_write_4(sc, PRV_TIMER_CTRL, 0); 196 tmr_prv_write_4(sc, PRV_TIMER_INTR, PRV_TIMER_INTR_EVENT); 197 198 ctrl = PRV_TIMER_CTRL_IRQ_ENABLE | PRV_TIMER_CTRL_TIMER_ENABLE; 199 200 if (period != 0) { 201 load = ((uint32_t)et->et_frequency * period) >> 32; 202 ctrl |= PRV_TIMER_CTRL_AUTO_RELOAD; 203 } else 204 load = 0; 205 206 if (first != 0) 207 count = (uint32_t)((et->et_frequency * first) >> 32); 208 else 209 count = load; 210 211 tmr_prv_write_4(sc, PRV_TIMER_LOAD, load); 212 tmr_prv_write_4(sc, PRV_TIMER_COUNT, count); 213 tmr_prv_write_4(sc, PRV_TIMER_CTRL, ctrl); 214 215 return (0); 216 } 217 218 /** 219 * arm_tmr_stop - stops the eventtimer (private) timer 220 * @et: pointer to eventtimer struct 221 * 222 * Simply stops the private timer by clearing all bits in the ctrl register. 223 * 224 * RETURNS 225 * Always returns 0 226 */ 227 static int 228 arm_tmr_stop(struct eventtimer *et) 229 { 230 struct arm_tmr_softc *sc; 231 232 sc = et->et_priv; 233 tmr_prv_write_4(sc, PRV_TIMER_CTRL, 0); 234 tmr_prv_write_4(sc, PRV_TIMER_INTR, PRV_TIMER_INTR_EVENT); 235 return (0); 236 } 237 238 /** 239 * arm_tmr_intr - ISR for the eventtimer (private) timer 240 * @arg: pointer to arm_tmr_softc struct 241 * 242 * Clears the event register and then calls the eventtimer callback. 243 * 244 * RETURNS 245 * Always returns FILTER_HANDLED 246 */ 247 static int 248 arm_tmr_intr(void *arg) 249 { 250 struct arm_tmr_softc *sc; 251 252 sc = arg; 253 tmr_prv_write_4(sc, PRV_TIMER_INTR, PRV_TIMER_INTR_EVENT); 254 if (sc->et.et_active) 255 sc->et.et_event_cb(&sc->et, sc->et.et_arg); 256 return (FILTER_HANDLED); 257 } 258 259 260 261 262 /** 263 * arm_tmr_probe - timer probe routine 264 * @dev: new device 265 * 266 * The probe function returns success when probed with the fdt compatible 267 * string set to "arm,mpcore-timers". 268 * 269 * RETURNS 270 * BUS_PROBE_DEFAULT if the fdt device is compatible, otherwise ENXIO. 271 */ 272 static int 273 arm_tmr_probe(device_t dev) 274 { 275 276 if (!ofw_bus_status_okay(dev)) 277 return (ENXIO); 278 279 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == TMR_NONE) 280 return (ENXIO); 281 282 device_set_desc(dev, "ARM MPCore Timers"); 283 return (BUS_PROBE_DEFAULT); 284 } 285 286 static int 287 attach_tc(struct arm_tmr_softc *sc) 288 { 289 int rid; 290 291 if (arm_tmr_tc != NULL) 292 return (EBUSY); 293 294 rid = sc->memrid; 295 sc->gbl_mem = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, &rid, 296 RF_ACTIVE); 297 if (sc->gbl_mem == NULL) { 298 device_printf(sc->dev, "could not allocate gbl mem resources\n"); 299 return (ENXIO); 300 } 301 tmr_gbl_write_4(sc, GBL_TIMER_CTRL, 0x00000000); 302 303 arm_tmr_timecount.tc_frequency = sc->clkfreq; 304 arm_tmr_timecount.tc_priv = sc; 305 tc_init(&arm_tmr_timecount); 306 arm_tmr_tc = &arm_tmr_timecount; 307 308 tmr_gbl_write_4(sc, GBL_TIMER_CTRL, GBL_TIMER_CTRL_TIMER_ENABLE); 309 310 return (0); 311 } 312 313 static int 314 attach_et(struct arm_tmr_softc *sc) 315 { 316 void *ihl; 317 int irid, mrid; 318 319 if (arm_tmr_et != NULL) 320 return (EBUSY); 321 322 mrid = sc->memrid; 323 sc->prv_mem = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, &mrid, 324 RF_ACTIVE); 325 if (sc->prv_mem == NULL) { 326 device_printf(sc->dev, "could not allocate prv mem resources\n"); 327 return (ENXIO); 328 } 329 tmr_prv_write_4(sc, PRV_TIMER_CTRL, 0x00000000); 330 331 irid = sc->irqrid; 332 sc->prv_irq = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, &irid, RF_ACTIVE); 333 if (sc->prv_irq == NULL) { 334 bus_release_resource(sc->dev, SYS_RES_MEMORY, mrid, sc->prv_mem); 335 device_printf(sc->dev, "could not allocate prv irq resources\n"); 336 return (ENXIO); 337 } 338 339 if (bus_setup_intr(sc->dev, sc->prv_irq, INTR_TYPE_CLK, arm_tmr_intr, 340 NULL, sc, &ihl) != 0) { 341 bus_release_resource(sc->dev, SYS_RES_MEMORY, mrid, sc->prv_mem); 342 bus_release_resource(sc->dev, SYS_RES_IRQ, irid, sc->prv_irq); 343 device_printf(sc->dev, "unable to setup the et irq handler.\n"); 344 return (ENXIO); 345 } 346 347 /* 348 * Setup and register the eventtimer. Most event timers set their min 349 * and max period values to some value calculated from the clock 350 * frequency. We might not know yet what our runtime clock frequency 351 * will be, so we just use some safe values. A max of 2 seconds ensures 352 * that even if our base clock frequency is 2GHz (meaning a 4GHz CPU), 353 * we won't overflow our 32-bit timer count register. A min of 20 354 * nanoseconds is pretty much completely arbitrary. 355 */ 356 sc->et.et_name = "MPCore"; 357 sc->et.et_flags = ET_FLAGS_PERIODIC | ET_FLAGS_ONESHOT | ET_FLAGS_PERCPU; 358 sc->et.et_quality = 1000; 359 sc->et.et_frequency = sc->clkfreq; 360 sc->et.et_min_period = 20 * SBT_1NS; 361 sc->et.et_max_period = 2 * SBT_1S; 362 sc->et.et_start = arm_tmr_start; 363 sc->et.et_stop = arm_tmr_stop; 364 sc->et.et_priv = sc; 365 et_register(&sc->et); 366 arm_tmr_et = &sc->et; 367 368 return (0); 369 } 370 371 /** 372 * arm_tmr_attach - attaches the timer to the simplebus 373 * @dev: new device 374 * 375 * Reserves memory and interrupt resources, stores the softc structure 376 * globally and registers both the timecount and eventtimer objects. 377 * 378 * RETURNS 379 * Zero on success or ENXIO if an error occuried. 380 */ 381 static int 382 arm_tmr_attach(device_t dev) 383 { 384 struct arm_tmr_softc *sc; 385 phandle_t node; 386 pcell_t clock; 387 int et_err, tc_err, tmrtype; 388 389 sc = device_get_softc(dev); 390 sc->dev = dev; 391 392 if (arm_tmr_freq_varies) { 393 sc->clkfreq = arm_tmr_freq; 394 } else { 395 if (arm_tmr_freq != 0) { 396 sc->clkfreq = arm_tmr_freq; 397 } else { 398 /* Get the base clock frequency */ 399 node = ofw_bus_get_node(dev); 400 if ((OF_getencprop(node, "clock-frequency", &clock, 401 sizeof(clock))) <= 0) { 402 device_printf(dev, "missing clock-frequency " 403 "attribute in FDT\n"); 404 return (ENXIO); 405 } 406 sc->clkfreq = clock; 407 } 408 } 409 410 tmrtype = ofw_bus_search_compatible(dev, compat_data)->ocd_data; 411 tc_err = ENXIO; 412 et_err = ENXIO; 413 414 /* 415 * If we're handling the global timer and it is fixed-frequency, set it 416 * up to use as a timecounter. If it's variable frequency it won't work 417 * as a timecounter. We also can't use it for DELAY(), so hopefully the 418 * platform provides its own implementation. If it doesn't, ours will 419 * get used, but since the frequency isn't set, it will only use the 420 * bogus loop counter. 421 */ 422 if (tmrtype & TMR_GBL) { 423 if (!arm_tmr_freq_varies) 424 tc_err = attach_tc(sc); 425 else if (bootverbose) 426 device_printf(sc->dev, 427 "not using variable-frequency device as timecounter"); 428 sc->memrid++; 429 sc->irqrid++; 430 } 431 432 /* If we are handling the private timer, set it up as an eventtimer. */ 433 if (tmrtype & TMR_PRV) { 434 et_err = attach_et(sc); 435 } 436 437 /* 438 * If we didn't successfully set up a timecounter or eventtimer then we 439 * didn't actually attach at all, return error. 440 */ 441 if (tc_err != 0 && et_err != 0) { 442 return (ENXIO); 443 } 444 445 #ifdef MULTIDELAY 446 /* 447 * We can register as the DELAY() implementation only if we successfully 448 * set up the global timer. 449 */ 450 if (tc_err == 0) 451 arm_set_delay(arm_tmr_delay, sc); 452 #endif 453 454 return (0); 455 } 456 457 static device_method_t arm_tmr_methods[] = { 458 DEVMETHOD(device_probe, arm_tmr_probe), 459 DEVMETHOD(device_attach, arm_tmr_attach), 460 { 0, 0 } 461 }; 462 463 static driver_t arm_tmr_driver = { 464 "mp_tmr", 465 arm_tmr_methods, 466 sizeof(struct arm_tmr_softc), 467 }; 468 469 static devclass_t arm_tmr_devclass; 470 471 EARLY_DRIVER_MODULE(mp_tmr, simplebus, arm_tmr_driver, arm_tmr_devclass, 0, 0, 472 BUS_PASS_TIMER + BUS_PASS_ORDER_MIDDLE); 473 EARLY_DRIVER_MODULE(mp_tmr, ofwbus, arm_tmr_driver, arm_tmr_devclass, 0, 0, 474 BUS_PASS_TIMER + BUS_PASS_ORDER_MIDDLE); 475 476 /* 477 * Handle a change in clock frequency. The mpcore timer runs at half the CPU 478 * frequency. When the CPU frequency changes due to power-saving or thermal 479 * management, the platform-specific code that causes the frequency change calls 480 * this routine to inform the clock driver, and we in turn inform the event 481 * timer system, which actually updates the value in et->frequency for us and 482 * reschedules the current event(s) in a way that's atomic with respect to 483 * start/stop/intr code that may be running on various CPUs at the time of the 484 * call. 485 * 486 * This routine can also be called by a platform's early init code. If the 487 * value passed is ARM_TMR_FREQUENCY_VARIES, that will cause the attach() code 488 * to register as an eventtimer, but not a timecounter. If the value passed in 489 * is any other non-zero value it is used as the fixed frequency for the timer. 490 */ 491 void 492 arm_tmr_change_frequency(uint64_t newfreq) 493 { 494 495 if (newfreq == ARM_TMR_FREQUENCY_VARIES) { 496 arm_tmr_freq_varies = true; 497 return; 498 } 499 500 arm_tmr_freq = newfreq; 501 if (arm_tmr_et != NULL) 502 et_change_frequency(arm_tmr_et, newfreq); 503 } 504 505 static void 506 arm_tmr_delay(int usec, void *arg) 507 { 508 struct arm_tmr_softc *sc = arg; 509 int32_t counts_per_usec; 510 int32_t counts; 511 uint32_t first, last; 512 513 /* Get the number of times to count */ 514 counts_per_usec = ((arm_tmr_timecount.tc_frequency / 1000000) + 1); 515 516 /* 517 * Clamp the timeout at a maximum value (about 32 seconds with 518 * a 66MHz clock). *Nobody* should be delay()ing for anywhere 519 * near that length of time and if they are, they should be hung 520 * out to dry. 521 */ 522 if (usec >= (0x80000000U / counts_per_usec)) 523 counts = (0x80000000U / counts_per_usec) - 1; 524 else 525 counts = usec * counts_per_usec; 526 527 first = tmr_gbl_read_4(sc, GBL_TIMER_COUNT_LOW); 528 529 while (counts > 0) { 530 last = tmr_gbl_read_4(sc, GBL_TIMER_COUNT_LOW); 531 counts -= (int32_t)(last - first); 532 first = last; 533 } 534 } 535 536 #ifndef MULTIDELAY 537 /** 538 * DELAY - Delay for at least usec microseconds. 539 * @usec: number of microseconds to delay by 540 * 541 * This function is called all over the kernel and is suppose to provide a 542 * consistent delay. This function may also be called before the console 543 * is setup so no printf's can be called here. 544 * 545 * RETURNS: 546 * nothing 547 */ 548 void 549 DELAY(int usec) 550 { 551 struct arm_tmr_softc *sc; 552 int32_t counts; 553 554 /* Check the timers are setup, if not just use a for loop for the meantime */ 555 if (arm_tmr_tc == NULL || arm_tmr_timecount.tc_frequency == 0) { 556 for (; usec > 0; usec--) 557 for (counts = 200; counts > 0; counts--) 558 cpufunc_nullop(); /* Prevent gcc from optimizing 559 * out the loop 560 */ 561 } else { 562 sc = arm_tmr_tc->tc_priv; 563 arm_tmr_delay(usec, sc); 564 } 565 } 566 #endif 567