1 /*- 2 * Copyright (c) 2011 The FreeBSD Foundation 3 * All rights reserved. 4 * 5 * Developed by Ben Gray <ben.r.gray@gmail.com> 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the company nor the name of the author may be used to 16 * endorse or promote products derived from this software without specific 17 * prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 */ 31 32 /** 33 * The ARM Cortex-A9 core can support a global timer plus a private and 34 * watchdog timer per core. This driver reserves memory and interrupt 35 * resources for accessing both timer register sets, these resources are 36 * stored globally and used to setup the timecount and eventtimer. 37 * 38 * The timecount timer uses the global 64-bit counter, whereas the 39 * per-CPU eventtimer uses the private 32-bit counters. 40 * 41 * 42 * REF: ARM Cortex-A9 MPCore, Technical Reference Manual (rev. r2p2) 43 */ 44 45 #include <sys/cdefs.h> 46 __FBSDID("$FreeBSD$"); 47 48 #include <sys/param.h> 49 #include <sys/systm.h> 50 #include <sys/bus.h> 51 #include <sys/kernel.h> 52 #include <sys/module.h> 53 #include <sys/malloc.h> 54 #include <sys/rman.h> 55 #include <sys/timeet.h> 56 #include <sys/timetc.h> 57 #include <sys/watchdog.h> 58 #include <machine/bus.h> 59 #include <machine/cpu.h> 60 #include <machine/intr.h> 61 62 #include <dev/ofw/openfirm.h> 63 #include <dev/ofw/ofw_bus.h> 64 #include <dev/ofw/ofw_bus_subr.h> 65 66 #include <machine/bus.h> 67 68 #include <arm/arm/mpcore_timervar.h> 69 70 /* Private (per-CPU) timer register map */ 71 #define PRV_TIMER_LOAD 0x0000 72 #define PRV_TIMER_COUNT 0x0004 73 #define PRV_TIMER_CTRL 0x0008 74 #define PRV_TIMER_INTR 0x000C 75 76 #define PRV_TIMER_CTR_PRESCALER_SHIFT 8 77 #define PRV_TIMER_CTRL_IRQ_ENABLE (1UL << 2) 78 #define PRV_TIMER_CTRL_AUTO_RELOAD (1UL << 1) 79 #define PRV_TIMER_CTRL_TIMER_ENABLE (1UL << 0) 80 81 #define PRV_TIMER_INTR_EVENT (1UL << 0) 82 83 /* Global timer register map */ 84 #define GBL_TIMER_COUNT_LOW 0x0000 85 #define GBL_TIMER_COUNT_HIGH 0x0004 86 #define GBL_TIMER_CTRL 0x0008 87 #define GBL_TIMER_INTR 0x000C 88 89 #define GBL_TIMER_CTR_PRESCALER_SHIFT 8 90 #define GBL_TIMER_CTRL_AUTO_INC (1UL << 3) 91 #define GBL_TIMER_CTRL_IRQ_ENABLE (1UL << 2) 92 #define GBL_TIMER_CTRL_COMP_ENABLE (1UL << 1) 93 #define GBL_TIMER_CTRL_TIMER_ENABLE (1UL << 0) 94 95 #define GBL_TIMER_INTR_EVENT (1UL << 0) 96 97 struct arm_tmr_softc { 98 device_t dev; 99 int irqrid; 100 int memrid; 101 struct resource * gbl_mem; 102 struct resource * prv_mem; 103 struct resource * prv_irq; 104 uint64_t clkfreq; 105 struct eventtimer et; 106 }; 107 108 static struct eventtimer *arm_tmr_et; 109 static struct timecounter *arm_tmr_tc; 110 static uint64_t arm_tmr_freq; 111 static boolean_t arm_tmr_freq_varies; 112 113 #define tmr_prv_read_4(sc, reg) bus_read_4((sc)->prv_mem, reg) 114 #define tmr_prv_write_4(sc, reg, val) bus_write_4((sc)->prv_mem, reg, val) 115 #define tmr_gbl_read_4(sc, reg) bus_read_4((sc)->gbl_mem, reg) 116 #define tmr_gbl_write_4(sc, reg, val) bus_write_4((sc)->gbl_mem, reg, val) 117 118 static timecounter_get_t arm_tmr_get_timecount; 119 120 static struct timecounter arm_tmr_timecount = { 121 .tc_name = "MPCore", 122 .tc_get_timecount = arm_tmr_get_timecount, 123 .tc_poll_pps = NULL, 124 .tc_counter_mask = ~0u, 125 .tc_frequency = 0, 126 .tc_quality = 800, 127 }; 128 129 #define TMR_GBL 0x01 130 #define TMR_PRV 0x02 131 #define TMR_BOTH (TMR_GBL | TMR_PRV) 132 #define TMR_NONE 0 133 134 static struct ofw_compat_data compat_data[] = { 135 {"arm,mpcore-timers", TMR_BOTH}, /* Non-standard, FreeBSD. */ 136 {"arm,cortex-a9-global-timer", TMR_GBL}, 137 {"arm,cortex-a5-global-timer", TMR_GBL}, 138 {"arm,cortex-a9-twd-timer", TMR_PRV}, 139 {"arm,cortex-a5-twd-timer", TMR_PRV}, 140 {"arm,arm11mp-twd-timer", TMR_PRV}, 141 {NULL, TMR_NONE} 142 }; 143 144 /** 145 * arm_tmr_get_timecount - reads the timecount (global) timer 146 * @tc: pointer to arm_tmr_timecount struct 147 * 148 * We only read the lower 32-bits, the timecount stuff only uses 32-bits 149 * so (for now?) ignore the upper 32-bits. 150 * 151 * RETURNS 152 * The lower 32-bits of the counter. 153 */ 154 static unsigned 155 arm_tmr_get_timecount(struct timecounter *tc) 156 { 157 struct arm_tmr_softc *sc; 158 159 sc = tc->tc_priv; 160 return (tmr_gbl_read_4(sc, GBL_TIMER_COUNT_LOW)); 161 } 162 163 /** 164 * arm_tmr_start - starts the eventtimer (private) timer 165 * @et: pointer to eventtimer struct 166 * @first: the number of seconds and fractional sections to trigger in 167 * @period: the period (in seconds and fractional sections) to set 168 * 169 * If the eventtimer is required to be in oneshot mode, period will be 170 * NULL and first will point to the time to trigger. If in periodic mode 171 * period will contain the time period and first may optionally contain 172 * the time for the first period. 173 * 174 * RETURNS 175 * Always returns 0 176 */ 177 static int 178 arm_tmr_start(struct eventtimer *et, sbintime_t first, sbintime_t period) 179 { 180 struct arm_tmr_softc *sc; 181 uint32_t load, count; 182 uint32_t ctrl; 183 184 sc = et->et_priv; 185 tmr_prv_write_4(sc, PRV_TIMER_CTRL, 0); 186 tmr_prv_write_4(sc, PRV_TIMER_INTR, PRV_TIMER_INTR_EVENT); 187 188 ctrl = PRV_TIMER_CTRL_IRQ_ENABLE | PRV_TIMER_CTRL_TIMER_ENABLE; 189 190 if (period != 0) { 191 load = ((uint32_t)et->et_frequency * period) >> 32; 192 ctrl |= PRV_TIMER_CTRL_AUTO_RELOAD; 193 } else 194 load = 0; 195 196 if (first != 0) 197 count = (uint32_t)((et->et_frequency * first) >> 32); 198 else 199 count = load; 200 201 tmr_prv_write_4(sc, PRV_TIMER_LOAD, load); 202 tmr_prv_write_4(sc, PRV_TIMER_COUNT, count); 203 tmr_prv_write_4(sc, PRV_TIMER_CTRL, ctrl); 204 205 return (0); 206 } 207 208 /** 209 * arm_tmr_stop - stops the eventtimer (private) timer 210 * @et: pointer to eventtimer struct 211 * 212 * Simply stops the private timer by clearing all bits in the ctrl register. 213 * 214 * RETURNS 215 * Always returns 0 216 */ 217 static int 218 arm_tmr_stop(struct eventtimer *et) 219 { 220 struct arm_tmr_softc *sc; 221 222 sc = et->et_priv; 223 tmr_prv_write_4(sc, PRV_TIMER_CTRL, 0); 224 tmr_prv_write_4(sc, PRV_TIMER_INTR, PRV_TIMER_INTR_EVENT); 225 return (0); 226 } 227 228 /** 229 * arm_tmr_intr - ISR for the eventtimer (private) timer 230 * @arg: pointer to arm_tmr_softc struct 231 * 232 * Clears the event register and then calls the eventtimer callback. 233 * 234 * RETURNS 235 * Always returns FILTER_HANDLED 236 */ 237 static int 238 arm_tmr_intr(void *arg) 239 { 240 struct arm_tmr_softc *sc; 241 242 sc = arg; 243 tmr_prv_write_4(sc, PRV_TIMER_INTR, PRV_TIMER_INTR_EVENT); 244 if (sc->et.et_active) 245 sc->et.et_event_cb(&sc->et, sc->et.et_arg); 246 return (FILTER_HANDLED); 247 } 248 249 250 251 252 /** 253 * arm_tmr_probe - timer probe routine 254 * @dev: new device 255 * 256 * The probe function returns success when probed with the fdt compatible 257 * string set to "arm,mpcore-timers". 258 * 259 * RETURNS 260 * BUS_PROBE_DEFAULT if the fdt device is compatible, otherwise ENXIO. 261 */ 262 static int 263 arm_tmr_probe(device_t dev) 264 { 265 266 if (!ofw_bus_status_okay(dev)) 267 return (ENXIO); 268 269 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == TMR_NONE) 270 return (ENXIO); 271 272 device_set_desc(dev, "ARM MPCore Timers"); 273 return (BUS_PROBE_DEFAULT); 274 } 275 276 static int 277 attach_tc(struct arm_tmr_softc *sc) 278 { 279 int rid; 280 281 if (arm_tmr_tc != NULL) 282 return (EBUSY); 283 284 rid = sc->memrid; 285 sc->gbl_mem = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, &rid, 286 RF_ACTIVE); 287 if (sc->gbl_mem == NULL) { 288 device_printf(sc->dev, "could not allocate gbl mem resources\n"); 289 return (ENXIO); 290 } 291 tmr_gbl_write_4(sc, GBL_TIMER_CTRL, 0x00000000); 292 293 arm_tmr_timecount.tc_frequency = sc->clkfreq; 294 arm_tmr_timecount.tc_priv = sc; 295 tc_init(&arm_tmr_timecount); 296 arm_tmr_tc = &arm_tmr_timecount; 297 298 tmr_gbl_write_4(sc, GBL_TIMER_CTRL, GBL_TIMER_CTRL_TIMER_ENABLE); 299 300 return (0); 301 } 302 303 static int 304 attach_et(struct arm_tmr_softc *sc) 305 { 306 void *ihl; 307 int irid, mrid; 308 309 if (arm_tmr_et != NULL) 310 return (EBUSY); 311 312 mrid = sc->memrid; 313 sc->prv_mem = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, &mrid, 314 RF_ACTIVE); 315 if (sc->prv_mem == NULL) { 316 device_printf(sc->dev, "could not allocate prv mem resources\n"); 317 return (ENXIO); 318 } 319 tmr_prv_write_4(sc, PRV_TIMER_CTRL, 0x00000000); 320 321 irid = sc->irqrid; 322 sc->prv_irq = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, &irid, RF_ACTIVE); 323 if (sc->prv_irq == NULL) { 324 bus_release_resource(sc->dev, SYS_RES_MEMORY, mrid, sc->prv_mem); 325 device_printf(sc->dev, "could not allocate prv irq resources\n"); 326 return (ENXIO); 327 } 328 329 if (bus_setup_intr(sc->dev, sc->prv_irq, INTR_TYPE_CLK, arm_tmr_intr, 330 NULL, sc, &ihl) != 0) { 331 bus_release_resource(sc->dev, SYS_RES_MEMORY, mrid, sc->prv_mem); 332 bus_release_resource(sc->dev, SYS_RES_IRQ, irid, sc->prv_irq); 333 device_printf(sc->dev, "unable to setup the et irq handler.\n"); 334 return (ENXIO); 335 } 336 337 /* 338 * Setup and register the eventtimer. Most event timers set their min 339 * and max period values to some value calculated from the clock 340 * frequency. We might not know yet what our runtime clock frequency 341 * will be, so we just use some safe values. A max of 2 seconds ensures 342 * that even if our base clock frequency is 2GHz (meaning a 4GHz CPU), 343 * we won't overflow our 32-bit timer count register. A min of 20 344 * nanoseconds is pretty much completely arbitrary. 345 */ 346 sc->et.et_name = "MPCore"; 347 sc->et.et_flags = ET_FLAGS_PERIODIC | ET_FLAGS_ONESHOT | ET_FLAGS_PERCPU; 348 sc->et.et_quality = 1000; 349 sc->et.et_frequency = sc->clkfreq; 350 sc->et.et_min_period = 20 * SBT_1NS; 351 sc->et.et_max_period = 2 * SBT_1S; 352 sc->et.et_start = arm_tmr_start; 353 sc->et.et_stop = arm_tmr_stop; 354 sc->et.et_priv = sc; 355 et_register(&sc->et); 356 arm_tmr_et = &sc->et; 357 358 return (0); 359 } 360 361 /** 362 * arm_tmr_attach - attaches the timer to the simplebus 363 * @dev: new device 364 * 365 * Reserves memory and interrupt resources, stores the softc structure 366 * globally and registers both the timecount and eventtimer objects. 367 * 368 * RETURNS 369 * Zero on success or ENXIO if an error occuried. 370 */ 371 static int 372 arm_tmr_attach(device_t dev) 373 { 374 struct arm_tmr_softc *sc; 375 phandle_t node; 376 pcell_t clock; 377 int et_err, tc_err, tmrtype; 378 379 sc = device_get_softc(dev); 380 sc->dev = dev; 381 382 if (arm_tmr_freq_varies) { 383 sc->clkfreq = arm_tmr_freq; 384 } else { 385 if (arm_tmr_freq != 0) { 386 sc->clkfreq = arm_tmr_freq; 387 } else { 388 /* Get the base clock frequency */ 389 node = ofw_bus_get_node(dev); 390 if ((OF_getencprop(node, "clock-frequency", &clock, 391 sizeof(clock))) <= 0) { 392 device_printf(dev, "missing clock-frequency " 393 "attribute in FDT\n"); 394 return (ENXIO); 395 } 396 sc->clkfreq = clock; 397 } 398 } 399 400 tmrtype = ofw_bus_search_compatible(dev, compat_data)->ocd_data; 401 tc_err = ENXIO; 402 et_err = ENXIO; 403 404 /* 405 * If we're handling the global timer and it is fixed-frequency, set it 406 * up to use as a timecounter. If it's variable frequency it won't work 407 * as a timecounter. We also can't use it for DELAY(), so hopefully the 408 * platform provides its own implementation. If it doesn't, ours will 409 * get used, but since the frequency isn't set, it will only use the 410 * bogus loop counter. 411 */ 412 if (tmrtype & TMR_GBL) { 413 if (!arm_tmr_freq_varies) 414 tc_err = attach_tc(sc); 415 else if (bootverbose) 416 device_printf(sc->dev, 417 "not using variable-frequency device as timecounter"); 418 sc->memrid++; 419 sc->irqrid++; 420 } 421 422 /* If we are handling the private timer, set it up as an eventtimer. */ 423 if (tmrtype & TMR_PRV) { 424 et_err = attach_et(sc); 425 } 426 427 /* 428 * If we didn't successfully set up a timecounter or eventtimer then we 429 * didn't actually attach at all, return error. 430 */ 431 if (tc_err != 0 && et_err != 0) { 432 return (ENXIO); 433 } 434 return (0); 435 } 436 437 static device_method_t arm_tmr_methods[] = { 438 DEVMETHOD(device_probe, arm_tmr_probe), 439 DEVMETHOD(device_attach, arm_tmr_attach), 440 { 0, 0 } 441 }; 442 443 static driver_t arm_tmr_driver = { 444 "mp_tmr", 445 arm_tmr_methods, 446 sizeof(struct arm_tmr_softc), 447 }; 448 449 static devclass_t arm_tmr_devclass; 450 451 EARLY_DRIVER_MODULE(mp_tmr, simplebus, arm_tmr_driver, arm_tmr_devclass, 0, 0, 452 BUS_PASS_TIMER + BUS_PASS_ORDER_MIDDLE); 453 EARLY_DRIVER_MODULE(mp_tmr, ofwbus, arm_tmr_driver, arm_tmr_devclass, 0, 0, 454 BUS_PASS_TIMER + BUS_PASS_ORDER_MIDDLE); 455 456 /* 457 * Handle a change in clock frequency. The mpcore timer runs at half the CPU 458 * frequency. When the CPU frequency changes due to power-saving or thermal 459 * management, the platform-specific code that causes the frequency change calls 460 * this routine to inform the clock driver, and we in turn inform the event 461 * timer system, which actually updates the value in et->frequency for us and 462 * reschedules the current event(s) in a way that's atomic with respect to 463 * start/stop/intr code that may be running on various CPUs at the time of the 464 * call. 465 * 466 * This routine can also be called by a platform's early init code. If the 467 * value passed is ARM_TMR_FREQUENCY_VARIES, that will cause the attach() code 468 * to register as an eventtimer, but not a timecounter. If the value passed in 469 * is any other non-zero value it is used as the fixed frequency for the timer. 470 */ 471 void 472 arm_tmr_change_frequency(uint64_t newfreq) 473 { 474 475 if (newfreq == ARM_TMR_FREQUENCY_VARIES) { 476 arm_tmr_freq_varies = true; 477 return; 478 } 479 480 arm_tmr_freq = newfreq; 481 if (arm_tmr_et != NULL) 482 et_change_frequency(arm_tmr_et, newfreq); 483 } 484 485 /** 486 * DELAY - Delay for at least usec microseconds. 487 * @usec: number of microseconds to delay by 488 * 489 * This function is called all over the kernel and is suppose to provide a 490 * consistent delay. This function may also be called before the console 491 * is setup so no printf's can be called here. 492 * 493 * RETURNS: 494 * nothing 495 */ 496 static void __used /* Must emit function code for the weak ref below. */ 497 arm_tmr_DELAY(int usec) 498 { 499 struct arm_tmr_softc *sc; 500 int32_t counts_per_usec; 501 int32_t counts; 502 uint32_t first, last; 503 504 /* Check the timers are setup, if not just use a for loop for the meantime */ 505 if (arm_tmr_tc == NULL || arm_tmr_timecount.tc_frequency == 0) { 506 for (; usec > 0; usec--) 507 for (counts = 200; counts > 0; counts--) 508 cpufunc_nullop(); /* Prevent gcc from optimizing 509 * out the loop 510 */ 511 return; 512 } 513 514 sc = arm_tmr_tc->tc_priv; 515 516 /* Get the number of times to count */ 517 counts_per_usec = ((arm_tmr_timecount.tc_frequency / 1000000) + 1); 518 519 /* 520 * Clamp the timeout at a maximum value (about 32 seconds with 521 * a 66MHz clock). *Nobody* should be delay()ing for anywhere 522 * near that length of time and if they are, they should be hung 523 * out to dry. 524 */ 525 if (usec >= (0x80000000U / counts_per_usec)) 526 counts = (0x80000000U / counts_per_usec) - 1; 527 else 528 counts = usec * counts_per_usec; 529 530 first = tmr_gbl_read_4(sc, GBL_TIMER_COUNT_LOW); 531 532 while (counts > 0) { 533 last = tmr_gbl_read_4(sc, GBL_TIMER_COUNT_LOW); 534 counts -= (int32_t)(last - first); 535 first = last; 536 } 537 } 538 539 /* 540 * Supply a DELAY() implementation via weak linkage. A platform may want to use 541 * the mpcore per-cpu eventtimers but provide its own DELAY() routine, 542 * especially when the core frequency can change on the fly. 543 */ 544 __weak_reference(arm_tmr_DELAY, DELAY); 545 546