1 /*- 2 * Copyright (c) 2011 The FreeBSD Foundation 3 * All rights reserved. 4 * 5 * Developed by Ben Gray <ben.r.gray@gmail.com> 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the company nor the name of the author may be used to 16 * endorse or promote products derived from this software without specific 17 * prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 */ 31 32 /** 33 * The ARM Cortex-A9 core can support a global timer plus a private and 34 * watchdog timer per core. This driver reserves memory and interrupt 35 * resources for accessing both timer register sets, these resources are 36 * stored globally and used to setup the timecount and eventtimer. 37 * 38 * The timecount timer uses the global 64-bit counter, whereas the 39 * per-CPU eventtimer uses the private 32-bit counters. 40 * 41 * 42 * REF: ARM Cortex-A9 MPCore, Technical Reference Manual (rev. r2p2) 43 */ 44 45 #include <sys/cdefs.h> 46 __FBSDID("$FreeBSD$"); 47 48 #include <sys/param.h> 49 #include <sys/systm.h> 50 #include <sys/bus.h> 51 #include <sys/kernel.h> 52 #include <sys/module.h> 53 #include <sys/malloc.h> 54 #include <sys/rman.h> 55 #include <sys/timeet.h> 56 #include <sys/timetc.h> 57 #include <sys/watchdog.h> 58 #include <machine/bus.h> 59 #include <machine/cpu.h> 60 #include <machine/intr.h> 61 62 #include <dev/fdt/fdt_common.h> 63 #include <dev/ofw/openfirm.h> 64 #include <dev/ofw/ofw_bus.h> 65 #include <dev/ofw/ofw_bus_subr.h> 66 67 #include <machine/bus.h> 68 #include <machine/fdt.h> 69 70 /* Private (per-CPU) timer register map */ 71 #define PRV_TIMER_LOAD 0x0000 72 #define PRV_TIMER_COUNT 0x0004 73 #define PRV_TIMER_CTRL 0x0008 74 #define PRV_TIMER_INTR 0x000C 75 76 #define PRV_TIMER_CTR_PRESCALER_SHIFT 8 77 #define PRV_TIMER_CTRL_IRQ_ENABLE (1UL << 2) 78 #define PRV_TIMER_CTRL_AUTO_RELOAD (1UL << 1) 79 #define PRV_TIMER_CTRL_TIMER_ENABLE (1UL << 0) 80 81 #define PRV_TIMER_INTR_EVENT (1UL << 0) 82 83 /* Global timer register map */ 84 #define GBL_TIMER_COUNT_LOW 0x0000 85 #define GBL_TIMER_COUNT_HIGH 0x0004 86 #define GBL_TIMER_CTRL 0x0008 87 #define GBL_TIMER_INTR 0x000C 88 89 #define GBL_TIMER_CTR_PRESCALER_SHIFT 8 90 #define GBL_TIMER_CTRL_AUTO_INC (1UL << 3) 91 #define GBL_TIMER_CTRL_IRQ_ENABLE (1UL << 2) 92 #define GBL_TIMER_CTRL_COMP_ENABLE (1UL << 1) 93 #define GBL_TIMER_CTRL_TIMER_ENABLE (1UL << 0) 94 95 #define GBL_TIMER_INTR_EVENT (1UL << 0) 96 97 struct arm_tmr_softc { 98 struct resource * tmr_res[4]; 99 bus_space_tag_t prv_bst; 100 bus_space_tag_t gbl_bst; 101 bus_space_handle_t prv_bsh; 102 bus_space_handle_t gbl_bsh; 103 uint32_t clkfreq; 104 struct eventtimer et; 105 }; 106 107 static struct resource_spec arm_tmr_spec[] = { 108 { SYS_RES_MEMORY, 0, RF_ACTIVE }, /* Global registers */ 109 { SYS_RES_IRQ, 0, RF_ACTIVE }, /* Global timer interrupt (unused) */ 110 { SYS_RES_MEMORY, 1, RF_ACTIVE }, /* Private (per-CPU) registers */ 111 { SYS_RES_IRQ, 1, RF_ACTIVE }, /* Private timer interrupt */ 112 { -1, 0 } 113 }; 114 115 static struct arm_tmr_softc *arm_tmr_sc = NULL; 116 117 uint32_t platform_arm_tmr_freq = 0; 118 119 #define tmr_prv_read_4(reg) \ 120 bus_space_read_4(arm_tmr_sc->prv_bst, arm_tmr_sc->prv_bsh, reg) 121 #define tmr_prv_write_4(reg, val) \ 122 bus_space_write_4(arm_tmr_sc->prv_bst, arm_tmr_sc->prv_bsh, reg, val) 123 #define tmr_gbl_read_4(reg) \ 124 bus_space_read_4(arm_tmr_sc->gbl_bst, arm_tmr_sc->gbl_bsh, reg) 125 #define tmr_gbl_write_4(reg, val) \ 126 bus_space_write_4(arm_tmr_sc->gbl_bst, arm_tmr_sc->gbl_bsh, reg, val) 127 128 129 static timecounter_get_t arm_tmr_get_timecount; 130 131 static struct timecounter arm_tmr_timecount = { 132 .tc_name = "MPCore", 133 .tc_get_timecount = arm_tmr_get_timecount, 134 .tc_poll_pps = NULL, 135 .tc_counter_mask = ~0u, 136 .tc_frequency = 0, 137 .tc_quality = 800, 138 }; 139 140 /** 141 * arm_tmr_get_timecount - reads the timecount (global) timer 142 * @tc: pointer to arm_tmr_timecount struct 143 * 144 * We only read the lower 32-bits, the timecount stuff only uses 32-bits 145 * so (for now?) ignore the upper 32-bits. 146 * 147 * RETURNS 148 * The lower 32-bits of the counter. 149 */ 150 static unsigned 151 arm_tmr_get_timecount(struct timecounter *tc) 152 { 153 return (tmr_gbl_read_4(GBL_TIMER_COUNT_LOW)); 154 } 155 156 /** 157 * arm_tmr_start - starts the eventtimer (private) timer 158 * @et: pointer to eventtimer struct 159 * @first: the number of seconds and fractional sections to trigger in 160 * @period: the period (in seconds and fractional sections) to set 161 * 162 * If the eventtimer is required to be in oneshot mode, period will be 163 * NULL and first will point to the time to trigger. If in periodic mode 164 * period will contain the time period and first may optionally contain 165 * the time for the first period. 166 * 167 * RETURNS 168 * Always returns 0 169 */ 170 static int 171 arm_tmr_start(struct eventtimer *et, sbintime_t first, sbintime_t period) 172 { 173 uint32_t load, count; 174 uint32_t ctrl; 175 176 tmr_prv_write_4(PRV_TIMER_CTRL, 0); 177 tmr_prv_write_4(PRV_TIMER_INTR, PRV_TIMER_INTR_EVENT); 178 179 ctrl = PRV_TIMER_CTRL_IRQ_ENABLE | PRV_TIMER_CTRL_TIMER_ENABLE; 180 181 if (period != 0) { 182 load = ((uint32_t)et->et_frequency * period) >> 32; 183 ctrl |= PRV_TIMER_CTRL_AUTO_RELOAD; 184 } else 185 load = 0; 186 187 if (first != 0) 188 count = (uint32_t)((et->et_frequency * first) >> 32); 189 else 190 count = load; 191 192 tmr_prv_write_4(PRV_TIMER_LOAD, load); 193 tmr_prv_write_4(PRV_TIMER_COUNT, count); 194 tmr_prv_write_4(PRV_TIMER_CTRL, ctrl); 195 196 return (0); 197 } 198 199 /** 200 * arm_tmr_stop - stops the eventtimer (private) timer 201 * @et: pointer to eventtimer struct 202 * 203 * Simply stops the private timer by clearing all bits in the ctrl register. 204 * 205 * RETURNS 206 * Always returns 0 207 */ 208 static int 209 arm_tmr_stop(struct eventtimer *et) 210 { 211 tmr_prv_write_4(PRV_TIMER_CTRL, 0); 212 return (0); 213 } 214 215 /** 216 * arm_tmr_intr - ISR for the eventtimer (private) timer 217 * @arg: pointer to arm_tmr_softc struct 218 * 219 * Clears the event register and then calls the eventtimer callback. 220 * 221 * RETURNS 222 * Always returns FILTER_HANDLED 223 */ 224 static int 225 arm_tmr_intr(void *arg) 226 { 227 struct arm_tmr_softc *sc = (struct arm_tmr_softc *)arg; 228 229 tmr_prv_write_4(PRV_TIMER_INTR, PRV_TIMER_INTR_EVENT); 230 231 if (sc->et.et_active) 232 sc->et.et_event_cb(&sc->et, sc->et.et_arg); 233 234 return (FILTER_HANDLED); 235 } 236 237 238 239 240 /** 241 * arm_tmr_probe - timer probe routine 242 * @dev: new device 243 * 244 * The probe function returns success when probed with the fdt compatible 245 * string set to "arm,mpcore-timers". 246 * 247 * RETURNS 248 * BUS_PROBE_DEFAULT if the fdt device is compatible, otherwise ENXIO. 249 */ 250 static int 251 arm_tmr_probe(device_t dev) 252 { 253 254 if (!ofw_bus_status_okay(dev)) 255 return (ENXIO); 256 257 if (!ofw_bus_is_compatible(dev, "arm,mpcore-timers")) 258 return (ENXIO); 259 260 device_set_desc(dev, "ARM MPCore Timers"); 261 return (BUS_PROBE_DEFAULT); 262 } 263 264 /** 265 * arm_tmr_attach - attaches the timer to the simplebus 266 * @dev: new device 267 * 268 * Reserves memory and interrupt resources, stores the softc structure 269 * globally and registers both the timecount and eventtimer objects. 270 * 271 * RETURNS 272 * Zero on sucess or ENXIO if an error occuried. 273 */ 274 static int 275 arm_tmr_attach(device_t dev) 276 { 277 struct arm_tmr_softc *sc = device_get_softc(dev); 278 phandle_t node; 279 pcell_t clock; 280 void *ihl; 281 282 if (arm_tmr_sc) 283 return (ENXIO); 284 285 if (platform_arm_tmr_freq != 0) 286 sc->clkfreq = platform_arm_tmr_freq; 287 else { 288 /* Get the base clock frequency */ 289 node = ofw_bus_get_node(dev); 290 if ((OF_getprop(node, "clock-frequency", &clock, 291 sizeof(clock))) <= 0) { 292 device_printf(dev, "missing clock-frequency attribute in FDT\n"); 293 return (ENXIO); 294 } 295 sc->clkfreq = fdt32_to_cpu(clock); 296 } 297 298 299 if (bus_alloc_resources(dev, arm_tmr_spec, sc->tmr_res)) { 300 device_printf(dev, "could not allocate resources\n"); 301 return (ENXIO); 302 } 303 304 /* Global timer interface */ 305 sc->gbl_bst = rman_get_bustag(sc->tmr_res[0]); 306 sc->gbl_bsh = rman_get_bushandle(sc->tmr_res[0]); 307 308 /* Private per-CPU timer interface */ 309 sc->prv_bst = rman_get_bustag(sc->tmr_res[2]); 310 sc->prv_bsh = rman_get_bushandle(sc->tmr_res[2]); 311 312 arm_tmr_sc = sc; 313 314 /* Disable both timers to start off */ 315 tmr_prv_write_4(PRV_TIMER_CTRL, 0x00000000); 316 tmr_gbl_write_4(GBL_TIMER_CTRL, 0x00000000); 317 318 /* Setup and enable the global timer to use as the timecounter */ 319 tmr_gbl_write_4(GBL_TIMER_CTRL, (0x00 << GBL_TIMER_CTR_PRESCALER_SHIFT) | 320 GBL_TIMER_CTRL_TIMER_ENABLE); 321 322 arm_tmr_timecount.tc_frequency = sc->clkfreq; 323 tc_init(&arm_tmr_timecount); 324 325 /* Setup and enable the timer */ 326 if (bus_setup_intr(dev, sc->tmr_res[3], INTR_TYPE_CLK, arm_tmr_intr, 327 NULL, sc, &ihl) != 0) { 328 bus_release_resources(dev, arm_tmr_spec, sc->tmr_res); 329 device_printf(dev, "Unable to setup the clock irq handler.\n"); 330 return (ENXIO); 331 } 332 333 sc->et.et_name = "MPCore"; 334 sc->et.et_flags = ET_FLAGS_PERIODIC | ET_FLAGS_ONESHOT | ET_FLAGS_PERCPU; 335 sc->et.et_quality = 1000; 336 337 sc->et.et_frequency = sc->clkfreq; 338 sc->et.et_min_period = (0x00000002LLU << 32) / sc->et.et_frequency; 339 sc->et.et_max_period = (0xfffffffeLLU << 32) / sc->et.et_frequency; 340 sc->et.et_start = arm_tmr_start; 341 sc->et.et_stop = arm_tmr_stop; 342 sc->et.et_priv = sc; 343 et_register(&sc->et); 344 345 return (0); 346 } 347 348 static device_method_t arm_tmr_methods[] = { 349 DEVMETHOD(device_probe, arm_tmr_probe), 350 DEVMETHOD(device_attach, arm_tmr_attach), 351 { 0, 0 } 352 }; 353 354 static driver_t arm_tmr_driver = { 355 "mp_tmr", 356 arm_tmr_methods, 357 sizeof(struct arm_tmr_softc), 358 }; 359 360 static devclass_t arm_tmr_devclass; 361 362 DRIVER_MODULE(mp_tmr, simplebus, arm_tmr_driver, arm_tmr_devclass, 0, 0); 363 364 /** 365 * DELAY - Delay for at least usec microseconds. 366 * @usec: number of microseconds to delay by 367 * 368 * This function is called all over the kernel and is suppose to provide a 369 * consistent delay. This function may also be called before the console 370 * is setup so no printf's can be called here. 371 * 372 * RETURNS: 373 * nothing 374 */ 375 static void __used /* Must emit function code for the weak ref below. */ 376 arm_tmr_DELAY(int usec) 377 { 378 int32_t counts_per_usec; 379 int32_t counts; 380 uint32_t first, last; 381 382 /* Check the timers are setup, if not just use a for loop for the meantime */ 383 if (arm_tmr_sc == NULL) { 384 for (; usec > 0; usec--) 385 for (counts = 200; counts > 0; counts--) 386 cpufunc_nullop(); /* Prevent gcc from optimizing 387 * out the loop 388 */ 389 return; 390 } 391 392 /* Get the number of times to count */ 393 counts_per_usec = ((arm_tmr_timecount.tc_frequency / 1000000) + 1); 394 395 /* 396 * Clamp the timeout at a maximum value (about 32 seconds with 397 * a 66MHz clock). *Nobody* should be delay()ing for anywhere 398 * near that length of time and if they are, they should be hung 399 * out to dry. 400 */ 401 if (usec >= (0x80000000U / counts_per_usec)) 402 counts = (0x80000000U / counts_per_usec) - 1; 403 else 404 counts = usec * counts_per_usec; 405 406 first = tmr_gbl_read_4(GBL_TIMER_COUNT_LOW); 407 408 while (counts > 0) { 409 last = tmr_gbl_read_4(GBL_TIMER_COUNT_LOW); 410 counts -= (int32_t)(last - first); 411 first = last; 412 } 413 } 414 415 /* 416 * Supply a DELAY() implementation via weak linkage. A platform may want to use 417 * the mpcore per-cpu eventtimers but provide its own DELAY() routine, 418 * especially when the core frequency can change on the fly. 419 */ 420 __weak_reference(arm_tmr_DELAY, DELAY); 421 422