1 /*- 2 * Copyright (c) 2011 The FreeBSD Foundation 3 * All rights reserved. 4 * 5 * Developed by Ben Gray <ben.r.gray@gmail.com> 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the company nor the name of the author may be used to 16 * endorse or promote products derived from this software without specific 17 * prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 */ 31 32 /** 33 * The ARM Cortex-A9 core can support a global timer plus a private and 34 * watchdog timer per core. This driver reserves memory and interrupt 35 * resources for accessing both timer register sets, these resources are 36 * stored globally and used to setup the timecount and eventtimer. 37 * 38 * The timecount timer uses the global 64-bit counter, whereas the 39 * per-CPU eventtimer uses the private 32-bit counters. 40 * 41 * 42 * REF: ARM Cortex-A9 MPCore, Technical Reference Manual (rev. r2p2) 43 */ 44 45 #include <sys/cdefs.h> 46 __FBSDID("$FreeBSD$"); 47 48 #include <sys/param.h> 49 #include <sys/systm.h> 50 #include <sys/bus.h> 51 #include <sys/kernel.h> 52 #include <sys/module.h> 53 #include <sys/malloc.h> 54 #include <sys/rman.h> 55 #include <sys/timeet.h> 56 #include <sys/timetc.h> 57 #include <sys/watchdog.h> 58 #include <machine/bus.h> 59 #include <machine/cpu.h> 60 #include <machine/frame.h> 61 #include <machine/intr.h> 62 63 #include <dev/fdt/fdt_common.h> 64 #include <dev/ofw/openfirm.h> 65 #include <dev/ofw/ofw_bus.h> 66 #include <dev/ofw/ofw_bus_subr.h> 67 68 #include <machine/bus.h> 69 #include <machine/fdt.h> 70 71 /* Private (per-CPU) timer register map */ 72 #define PRV_TIMER_LOAD 0x0000 73 #define PRV_TIMER_COUNT 0x0004 74 #define PRV_TIMER_CTRL 0x0008 75 #define PRV_TIMER_INTR 0x000C 76 77 #define PRV_TIMER_CTR_PRESCALER_SHIFT 8 78 #define PRV_TIMER_CTRL_IRQ_ENABLE (1UL << 2) 79 #define PRV_TIMER_CTRL_AUTO_RELOAD (1UL << 1) 80 #define PRV_TIMER_CTRL_TIMER_ENABLE (1UL << 0) 81 82 #define PRV_TIMER_INTR_EVENT (1UL << 0) 83 84 /* Global timer register map */ 85 #define GBL_TIMER_COUNT_LOW 0x0000 86 #define GBL_TIMER_COUNT_HIGH 0x0004 87 #define GBL_TIMER_CTRL 0x0008 88 #define GBL_TIMER_INTR 0x000C 89 90 #define GBL_TIMER_CTR_PRESCALER_SHIFT 8 91 #define GBL_TIMER_CTRL_AUTO_INC (1UL << 3) 92 #define GBL_TIMER_CTRL_IRQ_ENABLE (1UL << 2) 93 #define GBL_TIMER_CTRL_COMP_ENABLE (1UL << 1) 94 #define GBL_TIMER_CTRL_TIMER_ENABLE (1UL << 0) 95 96 #define GBL_TIMER_INTR_EVENT (1UL << 0) 97 98 struct arm_tmr_softc { 99 struct resource * tmr_res[4]; 100 bus_space_tag_t prv_bst; 101 bus_space_tag_t gbl_bst; 102 bus_space_handle_t prv_bsh; 103 bus_space_handle_t gbl_bsh; 104 uint32_t clkfreq; 105 struct eventtimer et; 106 }; 107 108 static struct resource_spec arm_tmr_spec[] = { 109 { SYS_RES_MEMORY, 0, RF_ACTIVE }, /* Global registers */ 110 { SYS_RES_IRQ, 0, RF_ACTIVE }, /* Global timer interrupt (unused) */ 111 { SYS_RES_MEMORY, 1, RF_ACTIVE }, /* Private (per-CPU) registers */ 112 { SYS_RES_IRQ, 1, RF_ACTIVE }, /* Private timer interrupt */ 113 { -1, 0 } 114 }; 115 116 static struct arm_tmr_softc *arm_tmr_sc = NULL; 117 118 #define tmr_prv_read_4(reg) \ 119 bus_space_read_4(arm_tmr_sc->prv_bst, arm_tmr_sc->prv_bsh, reg) 120 #define tmr_prv_write_4(reg, val) \ 121 bus_space_write_4(arm_tmr_sc->prv_bst, arm_tmr_sc->prv_bsh, reg, val) 122 #define tmr_gbl_read_4(reg) \ 123 bus_space_read_4(arm_tmr_sc->gbl_bst, arm_tmr_sc->gbl_bsh, reg) 124 #define tmr_gbl_write_4(reg, val) \ 125 bus_space_write_4(arm_tmr_sc->gbl_bst, arm_tmr_sc->gbl_bsh, reg, val) 126 127 128 static timecounter_get_t arm_tmr_get_timecount; 129 130 static struct timecounter arm_tmr_timecount = { 131 .tc_name = "ARM MPCore Timecounter", 132 .tc_get_timecount = arm_tmr_get_timecount, 133 .tc_poll_pps = NULL, 134 .tc_counter_mask = ~0u, 135 .tc_frequency = 0, 136 .tc_quality = 1000, 137 }; 138 139 /** 140 * arm_tmr_get_timecount - reads the timecount (global) timer 141 * @tc: pointer to arm_tmr_timecount struct 142 * 143 * We only read the lower 32-bits, the timecount stuff only uses 32-bits 144 * so (for now?) ignore the upper 32-bits. 145 * 146 * RETURNS 147 * The lower 32-bits of the counter. 148 */ 149 static unsigned 150 arm_tmr_get_timecount(struct timecounter *tc) 151 { 152 return (tmr_gbl_read_4(GBL_TIMER_COUNT_LOW)); 153 } 154 155 /** 156 * arm_tmr_start - starts the eventtimer (private) timer 157 * @et: pointer to eventtimer struct 158 * @first: the number of seconds and fractional sections to trigger in 159 * @period: the period (in seconds and fractional sections) to set 160 * 161 * If the eventtimer is required to be in oneshot mode, period will be 162 * NULL and first will point to the time to trigger. If in periodic mode 163 * period will contain the time period and first may optionally contain 164 * the time for the first period. 165 * 166 * RETURNS 167 * Always returns 0 168 */ 169 static int 170 arm_tmr_start(struct eventtimer *et, sbintime_t first, sbintime_t period) 171 { 172 uint32_t load, count; 173 uint32_t ctrl; 174 175 ctrl = PRV_TIMER_CTRL_IRQ_ENABLE | PRV_TIMER_CTRL_TIMER_ENABLE; 176 177 if (period != 0) { 178 load = ((uint32_t)et->et_frequency * period) >> 32; 179 ctrl |= PRV_TIMER_CTRL_AUTO_RELOAD; 180 } else 181 load = 0; 182 183 if (first != 0) 184 count = ((uint32_t)et->et_frequency * first) >> 32; 185 else 186 count = load; 187 188 tmr_prv_write_4(PRV_TIMER_LOAD, load); 189 tmr_prv_write_4(PRV_TIMER_COUNT, count); 190 191 tmr_prv_write_4(PRV_TIMER_CTRL, ctrl); 192 return (0); 193 } 194 195 /** 196 * arm_tmr_stop - stops the eventtimer (private) timer 197 * @et: pointer to eventtimer struct 198 * 199 * Simply stops the private timer by clearing all bits in the ctrl register. 200 * 201 * RETURNS 202 * Always returns 0 203 */ 204 static int 205 arm_tmr_stop(struct eventtimer *et) 206 { 207 tmr_prv_write_4(PRV_TIMER_CTRL, 0); 208 return (0); 209 } 210 211 /** 212 * arm_tmr_intr - ISR for the eventtimer (private) timer 213 * @arg: pointer to arm_tmr_softc struct 214 * 215 * Clears the event register and then calls the eventtimer callback. 216 * 217 * RETURNS 218 * Always returns FILTER_HANDLED 219 */ 220 static int 221 arm_tmr_intr(void *arg) 222 { 223 struct arm_tmr_softc *sc = (struct arm_tmr_softc *)arg; 224 225 tmr_prv_write_4(PRV_TIMER_INTR, PRV_TIMER_INTR_EVENT); 226 227 if (sc->et.et_active) 228 sc->et.et_event_cb(&sc->et, sc->et.et_arg); 229 230 return (FILTER_HANDLED); 231 } 232 233 234 235 236 /** 237 * arm_tmr_probe - timer probe routine 238 * @dev: new device 239 * 240 * The probe function returns success when probed with the fdt compatible 241 * string set to "arm,mpcore-timers". 242 * 243 * RETURNS 244 * BUS_PROBE_DEFAULT if the fdt device is compatible, otherwise ENXIO. 245 */ 246 static int 247 arm_tmr_probe(device_t dev) 248 { 249 if (!ofw_bus_is_compatible(dev, "arm,mpcore-timers")) 250 return (ENXIO); 251 252 device_set_desc(dev, "ARM Generic MPCore Timers"); 253 return (BUS_PROBE_DEFAULT); 254 } 255 256 /** 257 * arm_tmr_attach - attaches the timer to the simplebus 258 * @dev: new device 259 * 260 * Reserves memory and interrupt resources, stores the softc structure 261 * globally and registers both the timecount and eventtimer objects. 262 * 263 * RETURNS 264 * Zero on sucess or ENXIO if an error occuried. 265 */ 266 static int 267 arm_tmr_attach(device_t dev) 268 { 269 struct arm_tmr_softc *sc = device_get_softc(dev); 270 phandle_t node; 271 pcell_t clock; 272 void *ihl; 273 274 if (arm_tmr_sc) 275 return (ENXIO); 276 277 /* Get the base clock frequency */ 278 node = ofw_bus_get_node(dev); 279 if ((OF_getprop(node, "clock-frequency", &clock, sizeof(clock))) <= 0) { 280 device_printf(dev, "missing clock-frequency attribute in FDT\n"); 281 return (ENXIO); 282 } 283 sc->clkfreq = fdt32_to_cpu(clock); 284 285 286 if (bus_alloc_resources(dev, arm_tmr_spec, sc->tmr_res)) { 287 device_printf(dev, "could not allocate resources\n"); 288 return (ENXIO); 289 } 290 291 /* Global timer interface */ 292 sc->gbl_bst = rman_get_bustag(sc->tmr_res[0]); 293 sc->gbl_bsh = rman_get_bushandle(sc->tmr_res[0]); 294 295 /* Private per-CPU timer interface */ 296 sc->prv_bst = rman_get_bustag(sc->tmr_res[2]); 297 sc->prv_bsh = rman_get_bushandle(sc->tmr_res[2]); 298 299 arm_tmr_sc = sc; 300 301 /* Disable both timers to start off */ 302 tmr_prv_write_4(PRV_TIMER_CTRL, 0x00000000); 303 tmr_gbl_write_4(GBL_TIMER_CTRL, 0x00000000); 304 305 /* Setup and enable the global timer to use as the timecounter */ 306 tmr_gbl_write_4(GBL_TIMER_CTRL, (0x00 << GBL_TIMER_CTR_PRESCALER_SHIFT) | 307 GBL_TIMER_CTRL_TIMER_ENABLE); 308 309 arm_tmr_timecount.tc_frequency = sc->clkfreq; 310 tc_init(&arm_tmr_timecount); 311 312 /* Setup and enable the timer */ 313 if (bus_setup_intr(dev, sc->tmr_res[3], INTR_TYPE_CLK, arm_tmr_intr, 314 NULL, sc, &ihl) != 0) { 315 bus_release_resources(dev, arm_tmr_spec, sc->tmr_res); 316 device_printf(dev, "Unable to setup the clock irq handler.\n"); 317 return (ENXIO); 318 } 319 320 sc->et.et_name = "ARM MPCore Eventtimer"; 321 sc->et.et_flags = ET_FLAGS_PERIODIC | ET_FLAGS_ONESHOT | ET_FLAGS_PERCPU; 322 sc->et.et_quality = 1000; 323 324 sc->et.et_frequency = sc->clkfreq; 325 sc->et.et_min_period = (0x00000002LLU << 32) / sc->et.et_frequency; 326 sc->et.et_max_period = (0xfffffffeLLU << 32) / sc->et.et_frequency; 327 sc->et.et_start = arm_tmr_start; 328 sc->et.et_stop = arm_tmr_stop; 329 sc->et.et_priv = sc; 330 et_register(&sc->et); 331 332 return (0); 333 } 334 335 static device_method_t arm_tmr_methods[] = { 336 DEVMETHOD(device_probe, arm_tmr_probe), 337 DEVMETHOD(device_attach, arm_tmr_attach), 338 { 0, 0 } 339 }; 340 341 static driver_t arm_tmr_driver = { 342 "mp_tmr", 343 arm_tmr_methods, 344 sizeof(struct arm_tmr_softc), 345 }; 346 347 static devclass_t arm_tmr_devclass; 348 349 DRIVER_MODULE(mp_tmr, simplebus, arm_tmr_driver, arm_tmr_devclass, 0, 0); 350 351 /** 352 * cpu_initclocks - called by system to initialise the cpu clocks 353 * 354 * This is a boilerplat function, most of the setup has already been done 355 * when the driver was attached. Therefore this function must only be called 356 * after the driver is attached. 357 * 358 * RETURNS 359 * nothing 360 */ 361 void 362 cpu_initclocks(void) 363 { 364 if (PCPU_GET(cpuid) == 0) 365 cpu_initclocks_bsp(); 366 else 367 cpu_initclocks_ap(); 368 } 369 370 /** 371 * DELAY - Delay for at least usec microseconds. 372 * @usec: number of microseconds to delay by 373 * 374 * This function is called all over the kernel and is suppose to provide a 375 * consistent delay. This function may also be called before the console 376 * is setup so no printf's can be called here. 377 * 378 * RETURNS: 379 * nothing 380 */ 381 void 382 DELAY(int usec) 383 { 384 int32_t counts_per_usec; 385 int32_t counts; 386 uint32_t first, last; 387 388 /* Check the timers are setup, if not just use a for loop for the meantime */ 389 if (arm_tmr_sc == NULL) { 390 for (; usec > 0; usec--) 391 for (counts = 200; counts > 0; counts--) 392 cpufunc_nullop(); /* Prevent gcc from optimizing 393 * out the loop 394 */ 395 return; 396 } 397 398 /* Get the number of times to count */ 399 counts_per_usec = ((arm_tmr_timecount.tc_frequency / 1000000) + 1); 400 401 /* 402 * Clamp the timeout at a maximum value (about 32 seconds with 403 * a 66MHz clock). *Nobody* should be delay()ing for anywhere 404 * near that length of time and if they are, they should be hung 405 * out to dry. 406 */ 407 if (usec >= (0x80000000U / counts_per_usec)) 408 counts = (0x80000000U / counts_per_usec) - 1; 409 else 410 counts = usec * counts_per_usec; 411 412 first = tmr_gbl_read_4(GBL_TIMER_COUNT_LOW); 413 414 while (counts > 0) { 415 last = tmr_gbl_read_4(GBL_TIMER_COUNT_LOW); 416 counts -= (int32_t)(last - first); 417 first = last; 418 } 419 } 420