xref: /freebsd/sys/arm/arm/sys_machdep.c (revision 18282c47)
16fc729afSOlivier Houchard /*-
251369649SPedro F. Giffuni  * SPDX-License-Identifier: BSD-3-Clause
351369649SPedro F. Giffuni  *
46fc729afSOlivier Houchard  * Copyright (c) 1990 The Regents of the University of California.
56fc729afSOlivier Houchard  * All rights reserved.
66fc729afSOlivier Houchard  *
76fc729afSOlivier Houchard  * Redistribution and use in source and binary forms, with or without
86fc729afSOlivier Houchard  * modification, are permitted provided that the following conditions
96fc729afSOlivier Houchard  * are met:
106fc729afSOlivier Houchard  * 1. Redistributions of source code must retain the above copyright
116fc729afSOlivier Houchard  *    notice, this list of conditions and the following disclaimer.
126fc729afSOlivier Houchard  * 2. Redistributions in binary form must reproduce the above copyright
136fc729afSOlivier Houchard  *    notice, this list of conditions and the following disclaimer in the
146fc729afSOlivier Houchard  *    documentation and/or other materials provided with the distribution.
15f04f6877SWarner Losh  * 3. Neither the name of the University nor the names of its contributors
166fc729afSOlivier Houchard  *    may be used to endorse or promote products derived from this software
176fc729afSOlivier Houchard  *    without specific prior written permission.
186fc729afSOlivier Houchard  *
196fc729afSOlivier Houchard  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
206fc729afSOlivier Houchard  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
216fc729afSOlivier Houchard  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
226fc729afSOlivier Houchard  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
236fc729afSOlivier Houchard  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
246fc729afSOlivier Houchard  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
256fc729afSOlivier Houchard  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
266fc729afSOlivier Houchard  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
276fc729afSOlivier Houchard  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
286fc729afSOlivier Houchard  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
296fc729afSOlivier Houchard  * SUCH DAMAGE.
306fc729afSOlivier Houchard  *
316fc729afSOlivier Houchard  *	from: @(#)sys_machdep.c	5.5 (Berkeley) 1/19/91
326fc729afSOlivier Houchard  */
336fc729afSOlivier Houchard 
346fc729afSOlivier Houchard #include <sys/cdefs.h>
356fc729afSOlivier Houchard __FBSDID("$FreeBSD$");
366fc729afSOlivier Houchard 
3724c1c3bfSJonathan Anderson #include "opt_capsicum.h"
3818282c47SMark Johnston #include "opt_ktrace.h"
3974b5505eSRobert Watson 
406fc729afSOlivier Houchard #include <sys/param.h>
416fc729afSOlivier Houchard #include <sys/systm.h>
424a144410SRobert Watson #include <sys/capsicum.h>
4318282c47SMark Johnston #include <sys/ktrace.h>
446fc729afSOlivier Houchard #include <sys/proc.h>
456fc729afSOlivier Houchard #include <sys/sysproto.h>
466fc729afSOlivier Houchard #include <sys/syscall.h>
476fc729afSOlivier Houchard #include <sys/sysent.h>
488826d904SIan Lepore #include <vm/vm.h>
498826d904SIan Lepore #include <vm/vm_extern.h>
506fc729afSOlivier Houchard 
513025d19dSMichal Meloun #include <machine/cpu.h>
52371853e5SOlivier Houchard #include <machine/sysarch.h>
53a86d7982SMichal Meloun #include <machine/machdep.h>
548826d904SIan Lepore #include <machine/vmparam.h>
55371853e5SOlivier Houchard 
566fc729afSOlivier Houchard #ifndef _SYS_SYSPROTO_H_
576fc729afSOlivier Houchard struct sysarch_args {
586fc729afSOlivier Houchard 	int op;
596fc729afSOlivier Houchard 	char *parms;
606fc729afSOlivier Houchard };
616fc729afSOlivier Houchard #endif
626fc729afSOlivier Houchard 
63371853e5SOlivier Houchard /* Prototypes */
64371853e5SOlivier Houchard static int arm32_sync_icache (struct thread *, void *);
65371853e5SOlivier Houchard static int arm32_drain_writebuf(struct thread *, void *);
66371853e5SOlivier Houchard 
678826d904SIan Lepore static int
688826d904SIan Lepore sync_icache(uintptr_t addr, size_t len)
698826d904SIan Lepore {
708826d904SIan Lepore 	size_t size;
718826d904SIan Lepore 	vm_offset_t rv;
728826d904SIan Lepore 
73ec090f4aSMichal Meloun 	 /* Align starting address to cacheline size */
74ec090f4aSMichal Meloun 	len += addr & cpuinfo.dcache_line_mask;
75ec090f4aSMichal Meloun 	addr &= ~cpuinfo.dcache_line_mask;
768826d904SIan Lepore 
778826d904SIan Lepore 	/* Break whole range to pages. */
788826d904SIan Lepore 	do {
798826d904SIan Lepore 		size = PAGE_SIZE - (addr & PAGE_MASK);
808826d904SIan Lepore 		size = min(size, len);
818826d904SIan Lepore 		rv = dcache_wb_pou_checked(addr, size);
828826d904SIan Lepore 		if (rv == 1) /* see dcache_wb_pou_checked() */
838826d904SIan Lepore 			rv = icache_inv_pou_checked(addr, size);
848826d904SIan Lepore 		if (rv != 1) {
858826d904SIan Lepore 			if (!useracc((void *)addr, size, VM_PROT_READ)) {
868826d904SIan Lepore 				/* Invalid access */
878826d904SIan Lepore 				return (rv);
888826d904SIan Lepore 			}
898826d904SIan Lepore 			/* Valid but unmapped page - skip it. */
908826d904SIan Lepore 		}
918826d904SIan Lepore 		len -= size;
928826d904SIan Lepore 		addr += size;
938826d904SIan Lepore 	} while (len > 0);
948826d904SIan Lepore 
958826d904SIan Lepore 	/* Invalidate branch predictor buffer. */
968826d904SIan Lepore 	bpb_inv_all();
978826d904SIan Lepore 	return (1);
988826d904SIan Lepore }
998826d904SIan Lepore 
100371853e5SOlivier Houchard static int
101371853e5SOlivier Houchard arm32_sync_icache(struct thread *td, void *args)
102371853e5SOlivier Houchard {
103371853e5SOlivier Houchard 	struct arm_sync_icache_args ua;
104371853e5SOlivier Houchard 	int error;
1058826d904SIan Lepore 	ksiginfo_t ksi;
1068826d904SIan Lepore 	vm_offset_t rv;
107371853e5SOlivier Houchard 
108371853e5SOlivier Houchard 	if ((error = copyin(args, &ua, sizeof(ua))) != 0)
109371853e5SOlivier Houchard 		return (error);
110371853e5SOlivier Houchard 
1118826d904SIan Lepore 	if  (ua.len == 0) {
1128826d904SIan Lepore 		td->td_retval[0] = 0;
1138826d904SIan Lepore 		return (0);
1148826d904SIan Lepore 	}
1158826d904SIan Lepore 
1168826d904SIan Lepore 	/*
1178826d904SIan Lepore 	 * Validate arguments. Address and length are unsigned,
1188826d904SIan Lepore 	 * so we can use wrapped overflow check.
1198826d904SIan Lepore 	 */
1208826d904SIan Lepore 	if (((ua.addr + ua.len) < ua.addr) ||
1218826d904SIan Lepore 	    ((ua.addr + ua.len) > VM_MAXUSER_ADDRESS)) {
1228826d904SIan Lepore 		ksiginfo_init_trap(&ksi);
1238826d904SIan Lepore 		ksi.ksi_signo = SIGSEGV;
1248826d904SIan Lepore 		ksi.ksi_code = SEGV_ACCERR;
1258826d904SIan Lepore 		ksi.ksi_addr = (void *)max(ua.addr, VM_MAXUSER_ADDRESS);
1268826d904SIan Lepore 		trapsignal(td, &ksi);
1278826d904SIan Lepore 		return (EINVAL);
1288826d904SIan Lepore 	}
1298826d904SIan Lepore 
1308826d904SIan Lepore 	rv = sync_icache(ua.addr, ua.len);
1318826d904SIan Lepore 	if (rv != 1) {
1328826d904SIan Lepore 		ksiginfo_init_trap(&ksi);
1338826d904SIan Lepore 		ksi.ksi_signo = SIGSEGV;
1348826d904SIan Lepore 		ksi.ksi_code = SEGV_MAPERR;
1358826d904SIan Lepore 		ksi.ksi_addr = (void *)rv;
1368826d904SIan Lepore 		trapsignal(td, &ksi);
1378826d904SIan Lepore 		return (EINVAL);
1388826d904SIan Lepore 	}
139371853e5SOlivier Houchard 
140371853e5SOlivier Houchard 	td->td_retval[0] = 0;
141371853e5SOlivier Houchard 	return (0);
142371853e5SOlivier Houchard }
143371853e5SOlivier Houchard 
144371853e5SOlivier Houchard static int
145371853e5SOlivier Houchard arm32_drain_writebuf(struct thread *td, void *args)
146371853e5SOlivier Houchard {
147371853e5SOlivier Houchard 	/* No args. */
148371853e5SOlivier Houchard 
149a89156f5SMichal Meloun 	dsb();
150a89156f5SMichal Meloun 	cpu_l2cache_drain_writebuf();
151a89156f5SMichal Meloun 	td->td_retval[0] = 0;
152371853e5SOlivier Houchard 	return (0);
153371853e5SOlivier Houchard }
154371853e5SOlivier Houchard 
155a74985cdSOlivier Houchard static int
156a74985cdSOlivier Houchard arm32_set_tp(struct thread *td, void *args)
157a74985cdSOlivier Houchard {
158a74985cdSOlivier Houchard 
159cf1a573fSOleksandr Tymoshenko 	set_tls(args);
160a74985cdSOlivier Houchard 	return (0);
161a74985cdSOlivier Houchard }
162a74985cdSOlivier Houchard 
163a74985cdSOlivier Houchard static int
164a74985cdSOlivier Houchard arm32_get_tp(struct thread *td, void *args)
165a74985cdSOlivier Houchard {
166a74985cdSOlivier Houchard 
167fa878ec3SEd Schouten 	td->td_retval[0] = (register_t)get_tls();
168a74985cdSOlivier Houchard 	return (0);
169a74985cdSOlivier Houchard }
170a74985cdSOlivier Houchard 
1716fc729afSOlivier Houchard int
1723e85b721SEd Maste sysarch(struct thread *td, struct sysarch_args *uap)
1736fc729afSOlivier Houchard {
174371853e5SOlivier Houchard 	int error;
175371853e5SOlivier Houchard 
17624c1c3bfSJonathan Anderson #ifdef CAPABILITY_MODE
17774b5505eSRobert Watson 	/*
17812bc222eSJonathan Anderson 	 * When adding new operations, add a new case statement here to
17912bc222eSJonathan Anderson 	 * explicitly indicate whether or not the operation is safe to
18012bc222eSJonathan Anderson 	 * perform in capability mode.
18174b5505eSRobert Watson 	 */
18274b5505eSRobert Watson 	if (IN_CAPABILITY_MODE(td)) {
18374b5505eSRobert Watson 		switch (uap->op) {
18474b5505eSRobert Watson 		case ARM_SYNC_ICACHE:
18574b5505eSRobert Watson 		case ARM_DRAIN_WRITEBUF:
18674b5505eSRobert Watson 		case ARM_SET_TP:
18774b5505eSRobert Watson 		case ARM_GET_TP:
188a86d7982SMichal Meloun 		case ARM_GET_VFPSTATE:
18974b5505eSRobert Watson 			break;
19074b5505eSRobert Watson 
19174b5505eSRobert Watson 		default:
192a417d4a4SDag-Erling Smørgrav #ifdef KTRACE
193a417d4a4SDag-Erling Smørgrav 			if (KTRPOINT(td, KTR_CAPFAIL))
1943fded357SPawel Jakub Dawidek 				ktrcapfail(CAPFAIL_SYSCALL, NULL, NULL);
195a417d4a4SDag-Erling Smørgrav #endif
19674b5505eSRobert Watson 			return (ECAPMODE);
19774b5505eSRobert Watson 		}
19874b5505eSRobert Watson 	}
19974b5505eSRobert Watson #endif
20074b5505eSRobert Watson 
201371853e5SOlivier Houchard 	switch (uap->op) {
202371853e5SOlivier Houchard 	case ARM_SYNC_ICACHE:
203371853e5SOlivier Houchard 		error = arm32_sync_icache(td, uap->parms);
204371853e5SOlivier Houchard 		break;
205371853e5SOlivier Houchard 	case ARM_DRAIN_WRITEBUF:
206371853e5SOlivier Houchard 		error = arm32_drain_writebuf(td, uap->parms);
207371853e5SOlivier Houchard 		break;
208a74985cdSOlivier Houchard 	case ARM_SET_TP:
209a74985cdSOlivier Houchard 		error = arm32_set_tp(td, uap->parms);
210a74985cdSOlivier Houchard 		break;
211a74985cdSOlivier Houchard 	case ARM_GET_TP:
212a74985cdSOlivier Houchard 		error = arm32_get_tp(td, uap->parms);
213a74985cdSOlivier Houchard 		break;
214a86d7982SMichal Meloun 	case ARM_GET_VFPSTATE:
215a86d7982SMichal Meloun 		error = arm_get_vfpstate(td, uap->parms);
216a86d7982SMichal Meloun 		break;
217371853e5SOlivier Houchard 	default:
218371853e5SOlivier Houchard 		error = EINVAL;
219371853e5SOlivier Houchard 		break;
220371853e5SOlivier Houchard 	}
221371853e5SOlivier Houchard 	return (error);
2226fc729afSOlivier Houchard }
223