1 /*-
2  * Copyright (c) 2012 Oleksandr Tymoshenko <gonzo@freebsd.org>
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions
7  * are met:
8  * 1. Redistributions of source code must retain the above copyright
9  *    notice, this list of conditions and the following disclaimer.
10  * 2. Redistributions in binary form must reproduce the above copyright
11  *    notice, this list of conditions and the following disclaimer in the
12  *    documentation and/or other materials provided with the distribution.
13  *
14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24  * SUCH DAMAGE.
25  *
26  */
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
29 
30 #include <sys/param.h>
31 #include <sys/systm.h>
32 #include <sys/bus.h>
33 #include <sys/kernel.h>
34 #include <sys/lock.h>
35 #include <sys/malloc.h>
36 #include <sys/module.h>
37 #include <sys/mutex.h>
38 #include <sys/rman.h>
39 #include <sys/sysctl.h>
40 #include <sys/taskqueue.h>
41 
42 #include <machine/bus.h>
43 
44 #include <dev/fdt/fdt_common.h>
45 #include <dev/ofw/ofw_bus.h>
46 #include <dev/ofw/ofw_bus_subr.h>
47 
48 #include <dev/mmc/bridge.h>
49 #include <dev/mmc/mmcreg.h>
50 #include <dev/mmc/mmcbrvar.h>
51 
52 #include <dev/sdhci/sdhci.h>
53 #include "sdhci_if.h"
54 
55 #include "bcm2835_dma.h"
56 #include <arm/broadcom/bcm2835/bcm2835_mbox_prop.h>
57 #include "bcm2835_vcbus.h"
58 
59 #define	BCM2835_DEFAULT_SDHCI_FREQ	50
60 
61 #define	BCM_SDHCI_BUFFER_SIZE		512
62 #define	NUM_DMA_SEGS			2
63 
64 #ifdef DEBUG
65 #define dprintf(fmt, args...) do { printf("%s(): ", __func__);   \
66     printf(fmt,##args); } while (0)
67 #else
68 #define dprintf(fmt, args...)
69 #endif
70 
71 /* DMA doesn't yet work with the bcm3826 */
72 #ifdef SOC_BCM2836
73 #define	PIO_MODE	1
74 #else
75 #define	PIO_MODE	0
76 #endif
77 
78 static int bcm2835_sdhci_hs = 1;
79 static int bcm2835_sdhci_pio_mode = PIO_MODE;
80 
81 TUNABLE_INT("hw.bcm2835.sdhci.hs", &bcm2835_sdhci_hs);
82 TUNABLE_INT("hw.bcm2835.sdhci.pio_mode", &bcm2835_sdhci_pio_mode);
83 
84 struct bcm_sdhci_softc {
85 	device_t		sc_dev;
86 	struct mtx		sc_mtx;
87 	struct resource *	sc_mem_res;
88 	struct resource *	sc_irq_res;
89 	bus_space_tag_t		sc_bst;
90 	bus_space_handle_t	sc_bsh;
91 	void *			sc_intrhand;
92 	struct mmc_request *	sc_req;
93 	struct mmc_data *	sc_data;
94 	uint32_t		sc_flags;
95 #define	LPC_SD_FLAGS_IGNORECRC		(1 << 0)
96 	int			sc_xfer_direction;
97 #define	DIRECTION_READ		0
98 #define	DIRECTION_WRITE		1
99 	int			sc_xfer_done;
100 	int			sc_bus_busy;
101 	struct sdhci_slot	sc_slot;
102 	int			sc_dma_inuse;
103 	int			sc_dma_ch;
104 	bus_dma_tag_t		sc_dma_tag;
105 	bus_dmamap_t		sc_dma_map;
106 	vm_paddr_t		sc_sdhci_buffer_phys;
107 	uint32_t		cmd_and_mode;
108 	bus_addr_t		dmamap_seg_addrs[NUM_DMA_SEGS];
109 	bus_size_t		dmamap_seg_sizes[NUM_DMA_SEGS];
110 	int			dmamap_seg_count;
111 	int			dmamap_seg_index;
112 	int			dmamap_status;
113 };
114 
115 static int bcm_sdhci_probe(device_t);
116 static int bcm_sdhci_attach(device_t);
117 static int bcm_sdhci_detach(device_t);
118 static void bcm_sdhci_intr(void *);
119 
120 static int bcm_sdhci_get_ro(device_t, device_t);
121 static void bcm_sdhci_dma_intr(int ch, void *arg);
122 
123 #define	bcm_sdhci_lock(_sc)						\
124     mtx_lock(&_sc->sc_mtx);
125 #define	bcm_sdhci_unlock(_sc)						\
126     mtx_unlock(&_sc->sc_mtx);
127 
128 static void
129 bcm_sdhci_dmacb(void *arg, bus_dma_segment_t *segs, int nseg, int err)
130 {
131 	struct bcm_sdhci_softc *sc = arg;
132 	int i;
133 
134 	sc->dmamap_status = err;
135 	sc->dmamap_seg_count = nseg;
136 
137 	/* Note nseg is guaranteed to be zero if err is non-zero. */
138 	for (i = 0; i < nseg; i++) {
139 		sc->dmamap_seg_addrs[i] = segs[i].ds_addr;
140 		sc->dmamap_seg_sizes[i] = segs[i].ds_len;
141 	}
142 }
143 
144 static int
145 bcm_sdhci_probe(device_t dev)
146 {
147 
148 	if (!ofw_bus_status_okay(dev))
149 		return (ENXIO);
150 
151 	if (!ofw_bus_is_compatible(dev, "broadcom,bcm2835-sdhci"))
152 		return (ENXIO);
153 
154 	device_set_desc(dev, "Broadcom 2708 SDHCI controller");
155 	return (BUS_PROBE_DEFAULT);
156 }
157 
158 static int
159 bcm_sdhci_attach(device_t dev)
160 {
161 	struct bcm_sdhci_softc *sc = device_get_softc(dev);
162 	int rid, err;
163 	phandle_t node;
164 	pcell_t cell;
165 	u_int default_freq;
166 
167 	sc->sc_dev = dev;
168 	sc->sc_req = NULL;
169 
170 	err = bcm2835_mbox_set_power_state(dev, BCM2835_MBOX_POWER_ID_EMMC,
171 	    TRUE);
172 	if (err != 0) {
173 		if (bootverbose)
174 			device_printf(dev, "Unable to enable the power\n");
175 		return (err);
176 	}
177 
178 	default_freq = 0;
179 	err = bcm2835_mbox_get_clock_rate(dev, BCM2835_MBOX_CLOCK_ID_EMMC,
180 	    &default_freq);
181 	if (err == 0) {
182 		/* Convert to MHz */
183 		default_freq /= 1000000;
184 		if (bootverbose)
185 			device_printf(dev, "default frequency: %dMHz\n",
186 			    default_freq);
187 	}
188 	if (default_freq == 0)
189 		default_freq = BCM2835_DEFAULT_SDHCI_FREQ;
190 
191 	node = ofw_bus_get_node(sc->sc_dev);
192 	if ((OF_getprop(node, "clock-frequency", &cell, sizeof(cell))) > 0)
193 		default_freq = fdt32_to_cpu(cell)/1000000;
194 
195 	if (bootverbose)
196 		device_printf(dev, "SDHCI frequency: %dMHz\n", default_freq);
197 
198 	mtx_init(&sc->sc_mtx, "bcm sdhci", "sdhci", MTX_DEF);
199 
200 	rid = 0;
201 	sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
202 	    RF_ACTIVE);
203 	if (!sc->sc_mem_res) {
204 		device_printf(dev, "cannot allocate memory window\n");
205 		err = ENXIO;
206 		goto fail;
207 	}
208 
209 	sc->sc_bst = rman_get_bustag(sc->sc_mem_res);
210 	sc->sc_bsh = rman_get_bushandle(sc->sc_mem_res);
211 
212 	rid = 0;
213 	sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
214 	    RF_ACTIVE);
215 	if (!sc->sc_irq_res) {
216 		device_printf(dev, "cannot allocate interrupt\n");
217 		err = ENXIO;
218 		goto fail;
219 	}
220 
221 	if (bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_BIO | INTR_MPSAFE,
222 	    NULL, bcm_sdhci_intr, sc, &sc->sc_intrhand)) {
223 		device_printf(dev, "cannot setup interrupt handler\n");
224 		err = ENXIO;
225 		goto fail;
226 	}
227 
228 	if (!bcm2835_sdhci_pio_mode)
229 		sc->sc_slot.opt = SDHCI_PLATFORM_TRANSFER;
230 
231 	sc->sc_slot.caps = SDHCI_CAN_VDD_330 | SDHCI_CAN_VDD_180;
232 	if (bcm2835_sdhci_hs)
233 		sc->sc_slot.caps |= SDHCI_CAN_DO_HISPD;
234 	sc->sc_slot.caps |= (default_freq << SDHCI_CLOCK_BASE_SHIFT);
235 	sc->sc_slot.quirks = SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK
236 		| SDHCI_QUIRK_BROKEN_TIMEOUT_VAL
237 		| SDHCI_QUIRK_DONT_SET_HISPD_BIT
238 		| SDHCI_QUIRK_MISSING_CAPS;
239 
240 	sdhci_init_slot(dev, &sc->sc_slot, 0);
241 
242 	sc->sc_dma_ch = bcm_dma_allocate(BCM_DMA_CH_FAST1);
243 	if (sc->sc_dma_ch == BCM_DMA_CH_INVALID)
244 		sc->sc_dma_ch = bcm_dma_allocate(BCM_DMA_CH_FAST2);
245 	if (sc->sc_dma_ch == BCM_DMA_CH_INVALID)
246 		sc->sc_dma_ch = bcm_dma_allocate(BCM_DMA_CH_ANY);
247 	if (sc->sc_dma_ch == BCM_DMA_CH_INVALID)
248 		goto fail;
249 
250 	bcm_dma_setup_intr(sc->sc_dma_ch, bcm_sdhci_dma_intr, sc);
251 
252 	/* Allocate bus_dma resources. */
253 	err = bus_dma_tag_create(bus_get_dma_tag(dev),
254 	    1, 0, BUS_SPACE_MAXADDR_32BIT,
255 	    BUS_SPACE_MAXADDR, NULL, NULL,
256 	    BCM_SDHCI_BUFFER_SIZE, NUM_DMA_SEGS, BCM_SDHCI_BUFFER_SIZE,
257 	    BUS_DMA_ALLOCNOW, NULL, NULL,
258 	    &sc->sc_dma_tag);
259 
260 	if (err) {
261 		device_printf(dev, "failed allocate DMA tag");
262 		goto fail;
263 	}
264 
265 	err = bus_dmamap_create(sc->sc_dma_tag, 0, &sc->sc_dma_map);
266 	if (err) {
267 		device_printf(dev, "bus_dmamap_create failed\n");
268 		goto fail;
269 	}
270 
271 	sc->sc_sdhci_buffer_phys = BUS_SPACE_PHYSADDR(sc->sc_mem_res,
272 	    SDHCI_BUFFER);
273 
274 	bus_generic_probe(dev);
275 	bus_generic_attach(dev);
276 
277 	sdhci_start_slot(&sc->sc_slot);
278 
279 	return (0);
280 
281 fail:
282 	if (sc->sc_intrhand)
283 		bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_intrhand);
284 	if (sc->sc_irq_res)
285 		bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res);
286 	if (sc->sc_mem_res)
287 		bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res);
288 	mtx_destroy(&sc->sc_mtx);
289 
290 	return (err);
291 }
292 
293 static int
294 bcm_sdhci_detach(device_t dev)
295 {
296 
297 	return (EBUSY);
298 }
299 
300 static void
301 bcm_sdhci_intr(void *arg)
302 {
303 	struct bcm_sdhci_softc *sc = arg;
304 
305 	sdhci_generic_intr(&sc->sc_slot);
306 }
307 
308 static int
309 bcm_sdhci_get_ro(device_t bus, device_t child)
310 {
311 
312 	return (0);
313 }
314 
315 static inline uint32_t
316 RD4(struct bcm_sdhci_softc *sc, bus_size_t off)
317 {
318 	uint32_t val = bus_space_read_4(sc->sc_bst, sc->sc_bsh, off);
319 	return val;
320 }
321 
322 static inline void
323 WR4(struct bcm_sdhci_softc *sc, bus_size_t off, uint32_t val)
324 {
325 
326 	bus_space_write_4(sc->sc_bst, sc->sc_bsh, off, val);
327 	/*
328 	 * The Arasan HC has a bug where it may lose the content of
329 	 * consecutive writes to registers that are within two SD-card
330 	 * clock cycles of each other (a clock domain crossing problem).
331 	 */
332 	if (sc->sc_slot.clock > 0)
333 		DELAY(((2 * 1000000) / sc->sc_slot.clock) + 1);
334 }
335 
336 static uint8_t
337 bcm_sdhci_read_1(device_t dev, struct sdhci_slot *slot, bus_size_t off)
338 {
339 	struct bcm_sdhci_softc *sc = device_get_softc(dev);
340 	uint32_t val = RD4(sc, off & ~3);
341 
342 	return ((val >> (off & 3)*8) & 0xff);
343 }
344 
345 static uint16_t
346 bcm_sdhci_read_2(device_t dev, struct sdhci_slot *slot, bus_size_t off)
347 {
348 	struct bcm_sdhci_softc *sc = device_get_softc(dev);
349 	uint32_t val = RD4(sc, off & ~3);
350 
351 	/*
352 	 * Standard 32-bit handling of command and transfer mode.
353 	 */
354 	if (off == SDHCI_TRANSFER_MODE) {
355 		return (sc->cmd_and_mode >> 16);
356 	} else if (off == SDHCI_COMMAND_FLAGS) {
357 		return (sc->cmd_and_mode & 0x0000ffff);
358 	}
359 	return ((val >> (off & 3)*8) & 0xffff);
360 }
361 
362 static uint32_t
363 bcm_sdhci_read_4(device_t dev, struct sdhci_slot *slot, bus_size_t off)
364 {
365 	struct bcm_sdhci_softc *sc = device_get_softc(dev);
366 
367 	return RD4(sc, off);
368 }
369 
370 static void
371 bcm_sdhci_read_multi_4(device_t dev, struct sdhci_slot *slot, bus_size_t off,
372     uint32_t *data, bus_size_t count)
373 {
374 	struct bcm_sdhci_softc *sc = device_get_softc(dev);
375 
376 	bus_space_read_multi_4(sc->sc_bst, sc->sc_bsh, off, data, count);
377 }
378 
379 static void
380 bcm_sdhci_write_1(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint8_t val)
381 {
382 	struct bcm_sdhci_softc *sc = device_get_softc(dev);
383 	uint32_t val32 = RD4(sc, off & ~3);
384 	val32 &= ~(0xff << (off & 3)*8);
385 	val32 |= (val << (off & 3)*8);
386 	WR4(sc, off & ~3, val32);
387 }
388 
389 static void
390 bcm_sdhci_write_2(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint16_t val)
391 {
392 	struct bcm_sdhci_softc *sc = device_get_softc(dev);
393 	uint32_t val32;
394 	if (off == SDHCI_COMMAND_FLAGS)
395 		val32 = sc->cmd_and_mode;
396 	else
397 		val32 = RD4(sc, off & ~3);
398 	val32 &= ~(0xffff << (off & 3)*8);
399 	val32 |= (val << (off & 3)*8);
400 	if (off == SDHCI_TRANSFER_MODE)
401 		sc->cmd_and_mode = val32;
402 	else {
403 		WR4(sc, off & ~3, val32);
404 		if (off == SDHCI_COMMAND_FLAGS)
405 			sc->cmd_and_mode = val32;
406 	}
407 }
408 
409 static void
410 bcm_sdhci_write_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint32_t val)
411 {
412 	struct bcm_sdhci_softc *sc = device_get_softc(dev);
413 	WR4(sc, off, val);
414 }
415 
416 static void
417 bcm_sdhci_write_multi_4(device_t dev, struct sdhci_slot *slot, bus_size_t off,
418     uint32_t *data, bus_size_t count)
419 {
420 	struct bcm_sdhci_softc *sc = device_get_softc(dev);
421 
422 	bus_space_write_multi_4(sc->sc_bst, sc->sc_bsh, off, data, count);
423 }
424 
425 static void
426 bcm_sdhci_start_dma_seg(struct bcm_sdhci_softc *sc)
427 {
428 	struct sdhci_slot *slot;
429 	vm_paddr_t pdst, psrc;
430 	int err, idx, len, sync_op;
431 
432 	slot = &sc->sc_slot;
433 	idx = sc->dmamap_seg_index++;
434 	len = sc->dmamap_seg_sizes[idx];
435 	slot->offset += len;
436 
437 	if (slot->curcmd->data->flags & MMC_DATA_READ) {
438 		bcm_dma_setup_src(sc->sc_dma_ch, BCM_DMA_DREQ_EMMC,
439 		    BCM_DMA_SAME_ADDR, BCM_DMA_32BIT);
440 		bcm_dma_setup_dst(sc->sc_dma_ch, BCM_DMA_DREQ_NONE,
441 		    BCM_DMA_INC_ADDR,
442 		    (len & 0xf) ? BCM_DMA_32BIT : BCM_DMA_128BIT);
443 		psrc = sc->sc_sdhci_buffer_phys;
444 		pdst = sc->dmamap_seg_addrs[idx];
445 		sync_op = BUS_DMASYNC_PREREAD;
446 	} else {
447 		bcm_dma_setup_src(sc->sc_dma_ch, BCM_DMA_DREQ_NONE,
448 		    BCM_DMA_INC_ADDR,
449 		    (len & 0xf) ? BCM_DMA_32BIT : BCM_DMA_128BIT);
450 		bcm_dma_setup_dst(sc->sc_dma_ch, BCM_DMA_DREQ_EMMC,
451 		    BCM_DMA_SAME_ADDR, BCM_DMA_32BIT);
452 		psrc = sc->dmamap_seg_addrs[idx];
453 		pdst = sc->sc_sdhci_buffer_phys;
454 		sync_op = BUS_DMASYNC_PREWRITE;
455 	}
456 
457 	/*
458 	 * When starting a new DMA operation do the busdma sync operation, and
459 	 * disable SDCHI data interrrupts because we'll be driven by DMA
460 	 * interrupts (or SDHCI error interrupts) until the IO is done.
461 	 */
462 	if (idx == 0) {
463 		bus_dmamap_sync(sc->sc_dma_tag, sc->sc_dma_map, sync_op);
464 		slot->intmask &= ~(SDHCI_INT_DATA_AVAIL |
465 		    SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_END);
466 		bcm_sdhci_write_4(sc->sc_dev, &sc->sc_slot, SDHCI_SIGNAL_ENABLE,
467 		    slot->intmask);
468 	}
469 
470 	/*
471 	 * Start the DMA transfer.  Only programming errors (like failing to
472 	 * allocate a channel) cause a non-zero return from bcm_dma_start().
473 	 */
474 	err = bcm_dma_start(sc->sc_dma_ch, psrc, pdst, len);
475 	KASSERT((err == 0), ("bcm2835_sdhci: failed DMA start"));
476 }
477 
478 static void
479 bcm_sdhci_dma_intr(int ch, void *arg)
480 {
481 	struct bcm_sdhci_softc *sc = (struct bcm_sdhci_softc *)arg;
482 	struct sdhci_slot *slot = &sc->sc_slot;
483 	uint32_t reg, mask;
484 	int left, sync_op;
485 
486 	mtx_lock(&slot->mtx);
487 
488 	/*
489 	 * If there are more segments for the current dma, start the next one.
490 	 * Otherwise unload the dma map and decide what to do next based on the
491 	 * status of the sdhci controller and whether there's more data left.
492 	 */
493 	if (sc->dmamap_seg_index < sc->dmamap_seg_count) {
494 		bcm_sdhci_start_dma_seg(sc);
495 		mtx_unlock(&slot->mtx);
496 		return;
497 	}
498 
499 	if (slot->curcmd->data->flags & MMC_DATA_READ) {
500 		sync_op = BUS_DMASYNC_POSTREAD;
501 		mask = SDHCI_INT_DATA_AVAIL;
502 	} else {
503 		sync_op = BUS_DMASYNC_POSTWRITE;
504 		mask = SDHCI_INT_SPACE_AVAIL;
505 	}
506 	bus_dmamap_sync(sc->sc_dma_tag, sc->sc_dma_map, sync_op);
507 	bus_dmamap_unload(sc->sc_dma_tag, sc->sc_dma_map);
508 
509 	sc->dmamap_seg_count = 0;
510 	sc->dmamap_seg_index = 0;
511 
512 	left = min(BCM_SDHCI_BUFFER_SIZE,
513 	    slot->curcmd->data->len - slot->offset);
514 
515 	/* DATA END? */
516 	reg = bcm_sdhci_read_4(slot->bus, slot, SDHCI_INT_STATUS);
517 
518 	if (reg & SDHCI_INT_DATA_END) {
519 		/* ACK for all outstanding interrupts */
520 		bcm_sdhci_write_4(slot->bus, slot, SDHCI_INT_STATUS, reg);
521 
522 		/* enable INT */
523 		slot->intmask |= SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL
524 		    | SDHCI_INT_DATA_END;
525 		bcm_sdhci_write_4(slot->bus, slot, SDHCI_SIGNAL_ENABLE,
526 		    slot->intmask);
527 
528 		/* finish this data */
529 		sdhci_finish_data(slot);
530 	}
531 	else {
532 		/* already available? */
533 		if (reg & mask) {
534 
535 			/* ACK for DATA_AVAIL or SPACE_AVAIL */
536 			bcm_sdhci_write_4(slot->bus, slot,
537 			    SDHCI_INT_STATUS, mask);
538 
539 			/* continue next DMA transfer */
540 			if (bus_dmamap_load(sc->sc_dma_tag, sc->sc_dma_map,
541 			    (uint8_t *)slot->curcmd->data->data +
542 			    slot->offset, left, bcm_sdhci_dmacb, sc,
543 			    BUS_DMA_NOWAIT) != 0 || sc->dmamap_status != 0) {
544 				slot->curcmd->error = MMC_ERR_NO_MEMORY;
545 				sdhci_finish_data(slot);
546 			} else {
547 				bcm_sdhci_start_dma_seg(sc);
548 			}
549 		} else {
550 			/* wait for next data by INT */
551 
552 			/* enable INT */
553 			slot->intmask |= SDHCI_INT_DATA_AVAIL |
554 			    SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_END;
555 			bcm_sdhci_write_4(slot->bus, slot, SDHCI_SIGNAL_ENABLE,
556 			    slot->intmask);
557 		}
558 	}
559 
560 	mtx_unlock(&slot->mtx);
561 }
562 
563 static void
564 bcm_sdhci_read_dma(device_t dev, struct sdhci_slot *slot)
565 {
566 	struct bcm_sdhci_softc *sc = device_get_softc(slot->bus);
567 	size_t left;
568 
569 	if (sc->dmamap_seg_count != 0) {
570 		device_printf(sc->sc_dev, "DMA in use\n");
571 		return;
572 	}
573 
574 	left = min(BCM_SDHCI_BUFFER_SIZE,
575 	    slot->curcmd->data->len - slot->offset);
576 
577 	KASSERT((left & 3) == 0,
578 	    ("%s: len = %d, not word-aligned", __func__, left));
579 
580 	if (bus_dmamap_load(sc->sc_dma_tag, sc->sc_dma_map,
581 	    (uint8_t *)slot->curcmd->data->data + slot->offset, left,
582 	    bcm_sdhci_dmacb, sc, BUS_DMA_NOWAIT) != 0 ||
583 	    sc->dmamap_status != 0) {
584 		slot->curcmd->error = MMC_ERR_NO_MEMORY;
585 		return;
586 	}
587 
588 	/* DMA start */
589 	bcm_sdhci_start_dma_seg(sc);
590 }
591 
592 static void
593 bcm_sdhci_write_dma(device_t dev, struct sdhci_slot *slot)
594 {
595 	struct bcm_sdhci_softc *sc = device_get_softc(slot->bus);
596 	size_t left;
597 
598 	if (sc->dmamap_seg_count != 0) {
599 		device_printf(sc->sc_dev, "DMA in use\n");
600 		return;
601 	}
602 
603 	left = min(BCM_SDHCI_BUFFER_SIZE,
604 	    slot->curcmd->data->len - slot->offset);
605 
606 	KASSERT((left & 3) == 0,
607 	    ("%s: len = %d, not word-aligned", __func__, left));
608 
609 	if (bus_dmamap_load(sc->sc_dma_tag, sc->sc_dma_map,
610 	    (uint8_t *)slot->curcmd->data->data + slot->offset, left,
611 	    bcm_sdhci_dmacb, sc, BUS_DMA_NOWAIT) != 0 ||
612 	    sc->dmamap_status != 0) {
613 		slot->curcmd->error = MMC_ERR_NO_MEMORY;
614 		return;
615 	}
616 
617 	/* DMA start */
618 	bcm_sdhci_start_dma_seg(sc);
619 }
620 
621 static int
622 bcm_sdhci_will_handle_transfer(device_t dev, struct sdhci_slot *slot)
623 {
624 	size_t left;
625 
626 	/*
627 	 * Do not use DMA for transfers less than block size or with a length
628 	 * that is not a multiple of four.
629 	 */
630 	left = min(BCM_DMA_BLOCK_SIZE,
631 	    slot->curcmd->data->len - slot->offset);
632 	if (left < BCM_DMA_BLOCK_SIZE)
633 		return (0);
634 	if (left & 0x03)
635 		return (0);
636 
637 	return (1);
638 }
639 
640 static void
641 bcm_sdhci_start_transfer(device_t dev, struct sdhci_slot *slot,
642     uint32_t *intmask)
643 {
644 
645 	/* DMA transfer FIFO 1KB */
646 	if (slot->curcmd->data->flags & MMC_DATA_READ)
647 		bcm_sdhci_read_dma(dev, slot);
648 	else
649 		bcm_sdhci_write_dma(dev, slot);
650 }
651 
652 static void
653 bcm_sdhci_finish_transfer(device_t dev, struct sdhci_slot *slot)
654 {
655 
656 	sdhci_finish_data(slot);
657 }
658 
659 static device_method_t bcm_sdhci_methods[] = {
660 	/* Device interface */
661 	DEVMETHOD(device_probe,		bcm_sdhci_probe),
662 	DEVMETHOD(device_attach,	bcm_sdhci_attach),
663 	DEVMETHOD(device_detach,	bcm_sdhci_detach),
664 
665 	/* Bus interface */
666 	DEVMETHOD(bus_read_ivar,	sdhci_generic_read_ivar),
667 	DEVMETHOD(bus_write_ivar,	sdhci_generic_write_ivar),
668 	DEVMETHOD(bus_print_child,	bus_generic_print_child),
669 
670 	/* MMC bridge interface */
671 	DEVMETHOD(mmcbr_update_ios,	sdhci_generic_update_ios),
672 	DEVMETHOD(mmcbr_request,	sdhci_generic_request),
673 	DEVMETHOD(mmcbr_get_ro,		bcm_sdhci_get_ro),
674 	DEVMETHOD(mmcbr_acquire_host,	sdhci_generic_acquire_host),
675 	DEVMETHOD(mmcbr_release_host,	sdhci_generic_release_host),
676 
677 	/* Platform transfer methods */
678 	DEVMETHOD(sdhci_platform_will_handle,		bcm_sdhci_will_handle_transfer),
679 	DEVMETHOD(sdhci_platform_start_transfer,	bcm_sdhci_start_transfer),
680 	DEVMETHOD(sdhci_platform_finish_transfer,	bcm_sdhci_finish_transfer),
681 	/* SDHCI registers accessors */
682 	DEVMETHOD(sdhci_read_1,		bcm_sdhci_read_1),
683 	DEVMETHOD(sdhci_read_2,		bcm_sdhci_read_2),
684 	DEVMETHOD(sdhci_read_4,		bcm_sdhci_read_4),
685 	DEVMETHOD(sdhci_read_multi_4,	bcm_sdhci_read_multi_4),
686 	DEVMETHOD(sdhci_write_1,	bcm_sdhci_write_1),
687 	DEVMETHOD(sdhci_write_2,	bcm_sdhci_write_2),
688 	DEVMETHOD(sdhci_write_4,	bcm_sdhci_write_4),
689 	DEVMETHOD(sdhci_write_multi_4,	bcm_sdhci_write_multi_4),
690 
691 	{ 0, 0 }
692 };
693 
694 static devclass_t bcm_sdhci_devclass;
695 
696 static driver_t bcm_sdhci_driver = {
697 	"sdhci_bcm",
698 	bcm_sdhci_methods,
699 	sizeof(struct bcm_sdhci_softc),
700 };
701 
702 DRIVER_MODULE(sdhci_bcm, simplebus, bcm_sdhci_driver, bcm_sdhci_devclass, 0, 0);
703 MODULE_DEPEND(sdhci_bcm, sdhci, 1, 1, 1);
704