1 /*- 2 * Copyright (c) 2012 Oleksandr Tymoshenko <gonzo@freebsd.org> 3 * Copyright (c) 2013 Luiz Otavio O Souza <loos@freebsd.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 */ 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 #include <sys/param.h> 32 #include <sys/systm.h> 33 #include <sys/bus.h> 34 35 #include <sys/kernel.h> 36 #include <sys/module.h> 37 #include <sys/rman.h> 38 #include <sys/lock.h> 39 #include <sys/mutex.h> 40 #include <sys/sysctl.h> 41 42 #include <machine/bus.h> 43 #include <machine/cpu.h> 44 #include <machine/cpufunc.h> 45 #include <machine/resource.h> 46 #include <machine/intr.h> 47 48 #include <dev/fdt/fdt_common.h> 49 #include <dev/ofw/ofw_bus.h> 50 #include <dev/ofw/ofw_bus_subr.h> 51 52 #include <dev/spibus/spi.h> 53 #include <dev/spibus/spibusvar.h> 54 55 #include <arm/broadcom/bcm2835/bcm2835_gpio.h> 56 #include <arm/broadcom/bcm2835/bcm2835_spireg.h> 57 #include <arm/broadcom/bcm2835/bcm2835_spivar.h> 58 59 #include "spibus_if.h" 60 61 static void bcm_spi_intr(void *); 62 63 #ifdef BCM_SPI_DEBUG 64 static void 65 bcm_spi_printr(device_t dev) 66 { 67 struct bcm_spi_softc *sc; 68 uint32_t reg; 69 70 sc = device_get_softc(dev); 71 reg = BCM_SPI_READ(sc, SPI_CS); 72 device_printf(dev, "CS=%b\n", reg, 73 "\20\1CS0\2CS1\3CPHA\4CPOL\7CSPOL" 74 "\10TA\11DMAEN\12INTD\13INTR\14ADCS\15REN\16LEN" 75 "\21DONE\22RXD\23TXD\24RXR\25RXF\26CSPOL0\27CSPOL1" 76 "\30CSPOL2\31DMA_LEN\32LEN_LONG"); 77 reg = BCM_SPI_READ(sc, SPI_CLK) & SPI_CLK_MASK; 78 if (reg % 2) 79 reg--; 80 if (reg == 0) 81 reg = 65536; 82 device_printf(dev, "CLK=%uMhz/%d=%luhz\n", 83 SPI_CORE_CLK / 1000000, reg, SPI_CORE_CLK / reg); 84 reg = BCM_SPI_READ(sc, SPI_DLEN) & SPI_DLEN_MASK; 85 device_printf(dev, "DLEN=%d\n", reg); 86 reg = BCM_SPI_READ(sc, SPI_LTOH) & SPI_LTOH_MASK; 87 device_printf(dev, "LTOH=%d\n", reg); 88 reg = BCM_SPI_READ(sc, SPI_DC); 89 device_printf(dev, "DC=RPANIC=%#x RDREQ=%#x TPANIC=%#x TDREQ=%#x\n", 90 (reg & SPI_DC_RPANIC_MASK) >> SPI_DC_RPANIC_SHIFT, 91 (reg & SPI_DC_RDREQ_MASK) >> SPI_DC_RDREQ_SHIFT, 92 (reg & SPI_DC_TPANIC_MASK) >> SPI_DC_TPANIC_SHIFT, 93 (reg & SPI_DC_TDREQ_MASK) >> SPI_DC_TDREQ_SHIFT); 94 } 95 #endif 96 97 static void 98 bcm_spi_modifyreg(struct bcm_spi_softc *sc, uint32_t off, uint32_t mask, 99 uint32_t value) 100 { 101 uint32_t reg; 102 103 mtx_assert(&sc->sc_mtx, MA_OWNED); 104 reg = BCM_SPI_READ(sc, off); 105 reg &= ~mask; 106 reg |= value; 107 BCM_SPI_WRITE(sc, off, reg); 108 } 109 110 static int 111 bcm_spi_clock_proc(SYSCTL_HANDLER_ARGS) 112 { 113 struct bcm_spi_softc *sc; 114 uint32_t clk; 115 int error; 116 117 sc = (struct bcm_spi_softc *)arg1; 118 119 BCM_SPI_LOCK(sc); 120 clk = BCM_SPI_READ(sc, SPI_CLK); 121 BCM_SPI_UNLOCK(sc); 122 clk &= 0xffff; 123 if (clk == 0) 124 clk = 65536; 125 clk = SPI_CORE_CLK / clk; 126 127 error = sysctl_handle_int(oidp, &clk, sizeof(clk), req); 128 if (error != 0 || req->newptr == NULL) 129 return (error); 130 131 clk = SPI_CORE_CLK / clk; 132 if (clk <= 1) 133 clk = 2; 134 else if (clk % 2) 135 clk--; 136 if (clk > 0xffff) 137 clk = 0; 138 BCM_SPI_LOCK(sc); 139 BCM_SPI_WRITE(sc, SPI_CLK, clk); 140 BCM_SPI_UNLOCK(sc); 141 142 return (0); 143 } 144 145 static int 146 bcm_spi_cs_bit_proc(SYSCTL_HANDLER_ARGS, uint32_t bit) 147 { 148 struct bcm_spi_softc *sc; 149 uint32_t reg; 150 int error; 151 152 sc = (struct bcm_spi_softc *)arg1; 153 BCM_SPI_LOCK(sc); 154 reg = BCM_SPI_READ(sc, SPI_CS); 155 BCM_SPI_UNLOCK(sc); 156 reg = (reg & bit) ? 1 : 0; 157 158 error = sysctl_handle_int(oidp, ®, sizeof(reg), req); 159 if (error != 0 || req->newptr == NULL) 160 return (error); 161 162 if (reg) 163 reg = bit; 164 BCM_SPI_LOCK(sc); 165 bcm_spi_modifyreg(sc, SPI_CS, bit, reg); 166 BCM_SPI_UNLOCK(sc); 167 168 return (0); 169 } 170 171 static int 172 bcm_spi_cpol_proc(SYSCTL_HANDLER_ARGS) 173 { 174 175 return (bcm_spi_cs_bit_proc(oidp, arg1, arg2, req, SPI_CS_CPOL)); 176 } 177 178 static int 179 bcm_spi_cpha_proc(SYSCTL_HANDLER_ARGS) 180 { 181 182 return (bcm_spi_cs_bit_proc(oidp, arg1, arg2, req, SPI_CS_CPHA)); 183 } 184 185 static int 186 bcm_spi_cspol0_proc(SYSCTL_HANDLER_ARGS) 187 { 188 189 return (bcm_spi_cs_bit_proc(oidp, arg1, arg2, req, SPI_CS_CSPOL0)); 190 } 191 192 static int 193 bcm_spi_cspol1_proc(SYSCTL_HANDLER_ARGS) 194 { 195 196 return (bcm_spi_cs_bit_proc(oidp, arg1, arg2, req, SPI_CS_CSPOL1)); 197 } 198 199 static void 200 bcm_spi_sysctl_init(struct bcm_spi_softc *sc) 201 { 202 struct sysctl_ctx_list *ctx; 203 struct sysctl_oid *tree_node; 204 struct sysctl_oid_list *tree; 205 206 /* 207 * Add system sysctl tree/handlers. 208 */ 209 ctx = device_get_sysctl_ctx(sc->sc_dev); 210 tree_node = device_get_sysctl_tree(sc->sc_dev); 211 tree = SYSCTL_CHILDREN(tree_node); 212 SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "clock", 213 CTLFLAG_RW | CTLTYPE_UINT, sc, sizeof(*sc), 214 bcm_spi_clock_proc, "IU", "SPI BUS clock frequency"); 215 SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "cpol", 216 CTLFLAG_RW | CTLTYPE_UINT, sc, sizeof(*sc), 217 bcm_spi_cpol_proc, "IU", "SPI BUS clock polarity"); 218 SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "cpha", 219 CTLFLAG_RW | CTLTYPE_UINT, sc, sizeof(*sc), 220 bcm_spi_cpha_proc, "IU", "SPI BUS clock phase"); 221 SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "cspol0", 222 CTLFLAG_RW | CTLTYPE_UINT, sc, sizeof(*sc), 223 bcm_spi_cspol0_proc, "IU", "SPI BUS chip select 0 polarity"); 224 SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "cspol1", 225 CTLFLAG_RW | CTLTYPE_UINT, sc, sizeof(*sc), 226 bcm_spi_cspol1_proc, "IU", "SPI BUS chip select 1 polarity"); 227 } 228 229 static int 230 bcm_spi_probe(device_t dev) 231 { 232 233 if (!ofw_bus_status_okay(dev)) 234 return (ENXIO); 235 236 if (!ofw_bus_is_compatible(dev, "broadcom,bcm2835-spi")) 237 return (ENXIO); 238 239 device_set_desc(dev, "BCM2708/2835 SPI controller"); 240 241 return (BUS_PROBE_DEFAULT); 242 } 243 244 static int 245 bcm_spi_attach(device_t dev) 246 { 247 struct bcm_spi_softc *sc; 248 device_t gpio; 249 int i, rid; 250 251 if (device_get_unit(dev) != 0) { 252 device_printf(dev, "only one SPI controller supported\n"); 253 return (ENXIO); 254 } 255 256 sc = device_get_softc(dev); 257 sc->sc_dev = dev; 258 259 /* Configure the GPIO pins to ALT0 function to enable SPI the pins. */ 260 gpio = devclass_get_device(devclass_find("gpio"), 0); 261 if (!gpio) { 262 device_printf(dev, "cannot find gpio0\n"); 263 return (ENXIO); 264 } 265 for (i = 0; i < nitems(bcm_spi_pins); i++) 266 bcm_gpio_set_alternate(gpio, bcm_spi_pins[i], BCM_GPIO_ALT0); 267 268 rid = 0; 269 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 270 RF_ACTIVE); 271 if (!sc->sc_mem_res) { 272 device_printf(dev, "cannot allocate memory window\n"); 273 return (ENXIO); 274 } 275 276 sc->sc_bst = rman_get_bustag(sc->sc_mem_res); 277 sc->sc_bsh = rman_get_bushandle(sc->sc_mem_res); 278 279 rid = 0; 280 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 281 RF_ACTIVE); 282 if (!sc->sc_irq_res) { 283 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); 284 device_printf(dev, "cannot allocate interrupt\n"); 285 return (ENXIO); 286 } 287 288 /* Hook up our interrupt handler. */ 289 if (bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_MISC | INTR_MPSAFE, 290 NULL, bcm_spi_intr, sc, &sc->sc_intrhand)) { 291 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res); 292 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); 293 device_printf(dev, "cannot setup the interrupt handler\n"); 294 return (ENXIO); 295 } 296 297 mtx_init(&sc->sc_mtx, "bcm_spi", NULL, MTX_DEF); 298 299 /* Add sysctl nodes. */ 300 bcm_spi_sysctl_init(sc); 301 302 #ifdef BCM_SPI_DEBUG 303 bcm_spi_printr(dev); 304 #endif 305 306 /* 307 * Enable the SPI controller. Clear the rx and tx FIFO. 308 * Defaults to SPI mode 0. 309 */ 310 BCM_SPI_WRITE(sc, SPI_CS, SPI_CS_CLEAR_RXFIFO | SPI_CS_CLEAR_TXFIFO); 311 312 /* Set the SPI clock to 500Khz. */ 313 BCM_SPI_WRITE(sc, SPI_CLK, SPI_CORE_CLK / 500000); 314 315 #ifdef BCM_SPI_DEBUG 316 bcm_spi_printr(dev); 317 #endif 318 319 device_add_child(dev, "spibus", -1); 320 321 return (bus_generic_attach(dev)); 322 } 323 324 static int 325 bcm_spi_detach(device_t dev) 326 { 327 struct bcm_spi_softc *sc; 328 329 bus_generic_detach(dev); 330 331 sc = device_get_softc(dev); 332 mtx_destroy(&sc->sc_mtx); 333 if (sc->sc_intrhand) 334 bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_intrhand); 335 if (sc->sc_irq_res) 336 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res); 337 if (sc->sc_mem_res) 338 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); 339 340 return (0); 341 } 342 343 static void 344 bcm_spi_fill_fifo(struct bcm_spi_softc *sc) 345 { 346 struct spi_command *cmd; 347 uint32_t cs, written; 348 uint8_t *data; 349 350 cmd = sc->sc_cmd; 351 cs = BCM_SPI_READ(sc, SPI_CS) & (SPI_CS_TA | SPI_CS_TXD); 352 while (sc->sc_written < sc->sc_len && 353 cs == (SPI_CS_TA | SPI_CS_TXD)) { 354 data = (uint8_t *)cmd->tx_cmd; 355 written = sc->sc_written++; 356 if (written >= cmd->tx_cmd_sz) { 357 data = (uint8_t *)cmd->tx_data; 358 written -= cmd->tx_cmd_sz; 359 } 360 BCM_SPI_WRITE(sc, SPI_FIFO, data[written]); 361 cs = BCM_SPI_READ(sc, SPI_CS) & (SPI_CS_TA | SPI_CS_TXD); 362 } 363 } 364 365 static void 366 bcm_spi_drain_fifo(struct bcm_spi_softc *sc) 367 { 368 struct spi_command *cmd; 369 uint32_t cs, read; 370 uint8_t *data; 371 372 cmd = sc->sc_cmd; 373 cs = BCM_SPI_READ(sc, SPI_CS) & SPI_CS_RXD; 374 while (sc->sc_read < sc->sc_len && cs == SPI_CS_RXD) { 375 data = (uint8_t *)cmd->rx_cmd; 376 read = sc->sc_read++; 377 if (read >= cmd->rx_cmd_sz) { 378 data = (uint8_t *)cmd->rx_data; 379 read -= cmd->rx_cmd_sz; 380 } 381 data[read] = BCM_SPI_READ(sc, SPI_FIFO) & 0xff; 382 cs = BCM_SPI_READ(sc, SPI_CS) & SPI_CS_RXD; 383 } 384 } 385 386 static void 387 bcm_spi_intr(void *arg) 388 { 389 struct bcm_spi_softc *sc; 390 391 sc = (struct bcm_spi_softc *)arg; 392 BCM_SPI_LOCK(sc); 393 394 /* Filter stray interrupts. */ 395 if ((sc->sc_flags & BCM_SPI_BUSY) == 0) { 396 BCM_SPI_UNLOCK(sc); 397 return; 398 } 399 400 /* TX - Fill up the FIFO. */ 401 bcm_spi_fill_fifo(sc); 402 403 /* RX - Drain the FIFO. */ 404 bcm_spi_drain_fifo(sc); 405 406 /* Check for end of transfer. */ 407 if (sc->sc_written == sc->sc_len && sc->sc_read == sc->sc_len) { 408 /* Disable interrupts and the SPI engine. */ 409 bcm_spi_modifyreg(sc, SPI_CS, 410 SPI_CS_TA | SPI_CS_INTR | SPI_CS_INTD, 0); 411 wakeup(sc->sc_dev); 412 } 413 414 BCM_SPI_UNLOCK(sc); 415 } 416 417 static int 418 bcm_spi_transfer(device_t dev, device_t child, struct spi_command *cmd) 419 { 420 struct bcm_spi_softc *sc; 421 int cs, err; 422 423 sc = device_get_softc(dev); 424 425 KASSERT(cmd->tx_cmd_sz == cmd->rx_cmd_sz, 426 ("TX/RX command sizes should be equal")); 427 KASSERT(cmd->tx_data_sz == cmd->rx_data_sz, 428 ("TX/RX data sizes should be equal")); 429 430 BCM_SPI_LOCK(sc); 431 432 /* If the controller is in use wait until it is available. */ 433 while (sc->sc_flags & BCM_SPI_BUSY) 434 mtx_sleep(dev, &sc->sc_mtx, 0, "bcm_spi", 0); 435 436 /* Now we have control over SPI controller. */ 437 sc->sc_flags = BCM_SPI_BUSY; 438 439 /* Clear the FIFO. */ 440 bcm_spi_modifyreg(sc, SPI_CS, 441 SPI_CS_CLEAR_RXFIFO | SPI_CS_CLEAR_TXFIFO, 442 SPI_CS_CLEAR_RXFIFO | SPI_CS_CLEAR_TXFIFO); 443 444 /* Get the proper chip select for this child. */ 445 spibus_get_cs(child, &cs); 446 if (cs < 0 || cs > 2) { 447 device_printf(dev, 448 "Invalid chip select %d requested by %s\n", cs, 449 device_get_nameunit(child)); 450 BCM_SPI_UNLOCK(sc); 451 return (EINVAL); 452 } 453 454 /* Save a pointer to the SPI command. */ 455 sc->sc_cmd = cmd; 456 sc->sc_read = 0; 457 sc->sc_written = 0; 458 sc->sc_len = cmd->tx_cmd_sz + cmd->tx_data_sz; 459 460 /* 461 * Set the CS for this transaction, enable interrupts and announce 462 * we're ready to tx. This will kick off the first interrupt. 463 */ 464 bcm_spi_modifyreg(sc, SPI_CS, 465 SPI_CS_MASK | SPI_CS_TA | SPI_CS_INTR | SPI_CS_INTD, 466 cs | SPI_CS_TA | SPI_CS_INTR | SPI_CS_INTD); 467 468 /* Wait for the transaction to complete. */ 469 err = mtx_sleep(dev, &sc->sc_mtx, 0, "bcm_spi", hz * 2); 470 471 /* Make sure the SPI engine and interrupts are disabled. */ 472 bcm_spi_modifyreg(sc, SPI_CS, SPI_CS_TA | SPI_CS_INTR | SPI_CS_INTD, 0); 473 474 /* Clear the controller flags. */ 475 sc->sc_flags = 0; 476 477 /* 478 * Check for transfer timeout. The SPI controller doesn't 479 * return errors. 480 */ 481 if (err == EWOULDBLOCK) { 482 device_printf(sc->sc_dev, "SPI error\n"); 483 err = EIO; 484 } 485 486 BCM_SPI_UNLOCK(sc); 487 488 return (err); 489 } 490 491 static phandle_t 492 bcm_spi_get_node(device_t bus, device_t dev) 493 { 494 495 /* We only have one child, the SPI bus, which needs our own node. */ 496 return (ofw_bus_get_node(bus)); 497 } 498 499 static device_method_t bcm_spi_methods[] = { 500 /* Device interface */ 501 DEVMETHOD(device_probe, bcm_spi_probe), 502 DEVMETHOD(device_attach, bcm_spi_attach), 503 DEVMETHOD(device_detach, bcm_spi_detach), 504 505 /* SPI interface */ 506 DEVMETHOD(spibus_transfer, bcm_spi_transfer), 507 508 /* ofw_bus interface */ 509 DEVMETHOD(ofw_bus_get_node, bcm_spi_get_node), 510 511 DEVMETHOD_END 512 }; 513 514 static devclass_t bcm_spi_devclass; 515 516 static driver_t bcm_spi_driver = { 517 "spi", 518 bcm_spi_methods, 519 sizeof(struct bcm_spi_softc), 520 }; 521 522 DRIVER_MODULE(bcm2835_spi, simplebus, bcm_spi_driver, bcm_spi_devclass, 0, 0); 523