1 /*- 2 * SPDX-License-Identifier: ISC 3 * 4 * Copyright (c) 2020 Dr Robert Harvey Crowston <crowston@protonmail.com> 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 * 18 * 19 */ 20 21 /* 22 * BCM2838-compatible PCI-express controller. 23 * 24 * Broadcom likes to give the same chip lots of different names. The name of 25 * this driver is taken from the Raspberry Pi 4 Broadcom 2838 chip. 26 */ 27 28 #include <sys/cdefs.h> 29 #include <sys/param.h> 30 #include <sys/systm.h> 31 #include <sys/endian.h> 32 #include <sys/kernel.h> 33 #include <sys/module.h> 34 #include <sys/bus.h> 35 #include <sys/proc.h> 36 #include <sys/rman.h> 37 #include <sys/intr.h> 38 #include <sys/mutex.h> 39 40 #include <dev/ofw/openfirm.h> 41 #include <dev/ofw/ofw_bus.h> 42 #include <dev/ofw/ofw_bus_subr.h> 43 44 #include <dev/pci/pci_host_generic.h> 45 #include <dev/pci/pci_host_generic_fdt.h> 46 #include <dev/pci/pcivar.h> 47 #include <dev/pci/pcireg.h> 48 #include <dev/pci/pcib_private.h> 49 50 #include <machine/bus.h> 51 #include <machine/intr.h> 52 53 #include "pcib_if.h" 54 #include "msi_if.h" 55 56 #define PCI_ID_VAL3 0x43c 57 #define CLASS_SHIFT 0x10 58 #define SUBCLASS_SHIFT 0x8 59 60 #define REG_CONTROLLER_HW_REV 0x406c 61 #define REG_BRIDGE_CTRL 0x9210 62 #define BRIDGE_DISABLE_FLAG 0x1 63 #define BRIDGE_RESET_FLAG 0x2 64 #define REG_BRIDGE_SERDES_MODE 0x4204 65 #define REG_DMA_CONFIG 0x4008 66 #define REG_DMA_WINDOW_LOW 0x4034 67 #define REG_DMA_WINDOW_HIGH 0x4038 68 #define REG_DMA_WINDOW_1 0x403c 69 #define REG_BRIDGE_GISB_WINDOW 0x402c 70 #define REG_BRIDGE_STATE 0x4068 71 #define REG_BRIDGE_LINK_STATE 0x00bc 72 #define REG_BUS_WINDOW_LOW 0x400c 73 #define REG_BUS_WINDOW_HIGH 0x4010 74 #define REG_CPU_WINDOW_LOW 0x4070 75 #define REG_CPU_WINDOW_START_HIGH 0x4080 76 #define REG_CPU_WINDOW_END_HIGH 0x4084 77 78 #define REG_MSI_ADDR_LOW 0x4044 79 #define REG_MSI_ADDR_HIGH 0x4048 80 #define REG_MSI_CONFIG 0x404c 81 #define REG_MSI_CLR 0x4508 82 #define REG_MSI_MASK_CLR 0x4514 83 #define REG_MSI_RAISED 0x4500 84 #define REG_MSI_EOI 0x4060 85 #define NUM_MSI 32 86 87 #define REG_EP_CONFIG_CHOICE 0x9000 88 #define REG_EP_CONFIG_DATA 0x8000 89 90 /* 91 * The system memory controller can address up to 16 GiB of physical memory 92 * (although at time of writing the largest memory size available for purchase 93 * is 8 GiB). However, the system DMA controller is capable of accessing only a 94 * limited portion of the address space. Worse, the PCI-e controller has further 95 * constraints for DMA, and those limitations are not wholly clear to the 96 * author. NetBSD and Linux allow DMA on the lower 3 GiB of the physical memory, 97 * but experimentation shows DMA performed above 960 MiB results in data 98 * corruption with this driver. The limit of 960 MiB is taken from OpenBSD, but 99 * apparently that value was chosen for satisfying a constraint of an unrelated 100 * peripheral. 101 * 102 * Whatever the true maximum address, 960 MiB works. 103 */ 104 #define DMA_HIGH_LIMIT 0x3c000000 105 #define MAX_MEMORY_LOG2 0x21 106 #define REG_VALUE_DMA_WINDOW_LOW (MAX_MEMORY_LOG2 - 0xf) 107 #define REG_VALUE_DMA_WINDOW_HIGH 0x0 108 #define DMA_WINDOW_ENABLE 0x3000 109 #define REG_VALUE_DMA_WINDOW_CONFIG \ 110 (((MAX_MEMORY_LOG2 - 0xf) << 0x1b) | DMA_WINDOW_ENABLE) 111 112 #define REG_VALUE_MSI_CONFIG 0xffe06540 113 114 struct bcm_pcib_irqsrc { 115 struct intr_irqsrc isrc; 116 u_int irq; 117 bool allocated; 118 }; 119 120 struct bcm_pcib_softc { 121 struct generic_pcie_fdt_softc base; 122 device_t dev; 123 bus_dma_tag_t dmat; 124 struct mtx config_mtx; 125 struct mtx msi_mtx; 126 struct resource *msi_irq_res; 127 void *msi_intr_cookie; 128 struct bcm_pcib_irqsrc *msi_isrcs; 129 pci_addr_t msi_addr; 130 }; 131 132 static struct ofw_compat_data compat_data[] = { 133 {"brcm,bcm2711-pcie", 1}, 134 {"brcm,bcm7211-pcie", 1}, 135 {"brcm,bcm7445-pcie", 1}, 136 {NULL, 0} 137 }; 138 139 static int 140 bcm_pcib_probe(device_t dev) 141 { 142 143 if (!ofw_bus_status_okay(dev)) 144 return (ENXIO); 145 146 if (!ofw_bus_search_compatible(dev, compat_data)->ocd_data) 147 return (ENXIO); 148 149 device_set_desc(dev, 150 "BCM2838-compatible PCI-express controller"); 151 return (BUS_PROBE_DEFAULT); 152 } 153 154 static bus_dma_tag_t 155 bcm_pcib_get_dma_tag(device_t dev, device_t child) 156 { 157 struct bcm_pcib_softc *sc; 158 159 sc = device_get_softc(dev); 160 return (sc->dmat); 161 } 162 163 static void 164 bcm_pcib_set_reg(struct bcm_pcib_softc *sc, uint32_t reg, uint32_t val) 165 { 166 167 bus_write_4(sc->base.base.res, reg, htole32(val)); 168 } 169 170 static uint32_t 171 bcm_pcib_read_reg(struct bcm_pcib_softc *sc, uint32_t reg) 172 { 173 174 return (le32toh(bus_read_4(sc->base.base.res, reg))); 175 } 176 177 static void 178 bcm_pcib_reset_controller(struct bcm_pcib_softc *sc) 179 { 180 uint32_t val; 181 182 val = bcm_pcib_read_reg(sc, REG_BRIDGE_CTRL); 183 val = val | BRIDGE_RESET_FLAG | BRIDGE_DISABLE_FLAG; 184 bcm_pcib_set_reg(sc, REG_BRIDGE_CTRL, val); 185 186 DELAY(100); 187 188 val = bcm_pcib_read_reg(sc, REG_BRIDGE_CTRL); 189 val = val & ~BRIDGE_RESET_FLAG; 190 bcm_pcib_set_reg(sc, REG_BRIDGE_CTRL, val); 191 192 DELAY(100); 193 194 bcm_pcib_set_reg(sc, REG_BRIDGE_SERDES_MODE, 0); 195 196 DELAY(100); 197 } 198 199 static void 200 bcm_pcib_enable_controller(struct bcm_pcib_softc *sc) 201 { 202 uint32_t val; 203 204 val = bcm_pcib_read_reg(sc, REG_BRIDGE_CTRL); 205 val = val & ~BRIDGE_DISABLE_FLAG; 206 bcm_pcib_set_reg(sc, REG_BRIDGE_CTRL, val); 207 208 DELAY(100); 209 } 210 211 static int 212 bcm_pcib_check_ranges(device_t dev) 213 { 214 struct bcm_pcib_softc *sc; 215 struct pcie_range *ranges; 216 int error = 0, i; 217 218 sc = device_get_softc(dev); 219 ranges = &sc->base.base.ranges[0]; 220 221 /* The first range needs to be non-zero. */ 222 if (ranges[0].size == 0) { 223 device_printf(dev, "error: first outbound memory range " 224 "(pci addr: 0x%jx, cpu addr: 0x%jx) has zero size.\n", 225 ranges[0].pci_base, ranges[0].phys_base); 226 error = ENXIO; 227 } 228 229 /* 230 * The controller can actually handle three distinct ranges, but we 231 * only implement support for one. 232 */ 233 for (i = 1; (bootverbose || error) && i < MAX_RANGES_TUPLES; ++i) { 234 if (ranges[i].size > 0) 235 device_printf(dev, 236 "note: outbound memory range %d (pci addr: 0x%jx, " 237 "cpu addr: 0x%jx, size: 0x%jx) will be ignored.\n", 238 i, ranges[i].pci_base, ranges[i].phys_base, 239 ranges[i].size); 240 } 241 242 return (error); 243 } 244 245 static const char * 246 bcm_pcib_link_state_string(uint32_t mode) 247 { 248 249 switch(mode & PCIEM_LINK_STA_SPEED) { 250 case 0: 251 return ("not up"); 252 case 1: 253 return ("2.5 GT/s"); 254 case 2: 255 return ("5.0 GT/s"); 256 case 4: 257 return ("8.0 GT/s"); 258 default: 259 return ("unknown"); 260 } 261 } 262 263 static bus_addr_t 264 bcm_get_offset_and_prepare_config(struct bcm_pcib_softc *sc, u_int bus, 265 u_int slot, u_int func, u_int reg) 266 { 267 /* 268 * Config for an end point is only available through a narrow window for 269 * one end point at a time. We first tell the controller which end point 270 * we want, then access it through the window. 271 */ 272 uint32_t func_index; 273 274 if (bus == 0 && slot == 0 && func == 0) 275 /* 276 * Special case for root device; its config is always available 277 * through the zero-offset. 278 */ 279 return (reg); 280 281 /* Tell the controller to show us the config in question. */ 282 func_index = PCIE_ADDR_OFFSET(bus, slot, func, 0); 283 bcm_pcib_set_reg(sc, REG_EP_CONFIG_CHOICE, func_index); 284 285 return (REG_EP_CONFIG_DATA + reg); 286 } 287 288 static bool 289 bcm_pcib_is_valid_quad(struct bcm_pcib_softc *sc, u_int bus, u_int slot, 290 u_int func, u_int reg) 291 { 292 293 if ((bus < sc->base.base.bus_start) || (bus > sc->base.base.bus_end)) 294 return (false); 295 if ((slot > PCI_SLOTMAX) || (func > PCI_FUNCMAX) || (reg > PCIE_REGMAX)) 296 return (false); 297 298 if (bus == 0 && slot == 0 && func == 0) 299 return (true); 300 if (bus == 0) 301 /* 302 * Probing other slots and funcs on bus 0 will lock up the 303 * memory controller. 304 */ 305 return (false); 306 307 return (true); 308 } 309 310 static uint32_t 311 bcm_pcib_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg, 312 int bytes) 313 { 314 struct bcm_pcib_softc *sc; 315 bus_addr_t offset; 316 uint32_t data; 317 318 sc = device_get_softc(dev); 319 if (!bcm_pcib_is_valid_quad(sc, bus, slot, func, reg)) 320 return (~0U); 321 322 mtx_lock(&sc->config_mtx); 323 offset = bcm_get_offset_and_prepare_config(sc, bus, slot, func, reg); 324 325 switch (bytes) { 326 case 1: 327 data = bus_read_1(sc->base.base.res, offset); 328 break; 329 case 2: 330 data = le16toh(bus_read_2(sc->base.base.res, offset)); 331 break; 332 case 4: 333 data = le32toh(bus_read_4(sc->base.base.res, offset)); 334 break; 335 default: 336 data = ~0U; 337 break; 338 } 339 340 mtx_unlock(&sc->config_mtx); 341 return (data); 342 } 343 344 static void 345 bcm_pcib_write_config(device_t dev, u_int bus, u_int slot, 346 u_int func, u_int reg, uint32_t val, int bytes) 347 { 348 struct bcm_pcib_softc *sc; 349 uint32_t offset; 350 351 sc = device_get_softc(dev); 352 if (!bcm_pcib_is_valid_quad(sc, bus, slot, func, reg)) 353 return; 354 355 mtx_lock(&sc->config_mtx); 356 offset = bcm_get_offset_and_prepare_config(sc, bus, slot, func, reg); 357 358 switch (bytes) { 359 case 1: 360 bus_write_1(sc->base.base.res, offset, val); 361 break; 362 case 2: 363 bus_write_2(sc->base.base.res, offset, htole16(val)); 364 break; 365 case 4: 366 bus_write_4(sc->base.base.res, offset, htole32(val)); 367 break; 368 default: 369 break; 370 } 371 372 mtx_unlock(&sc->config_mtx); 373 } 374 375 static void 376 bcm_pcib_msi_intr_process(struct bcm_pcib_softc *sc, uint32_t interrupt_bitmap, 377 struct trapframe *tf) 378 { 379 struct bcm_pcib_irqsrc *irqsrc; 380 uint32_t bit, irq; 381 382 while ((bit = ffs(interrupt_bitmap))) { 383 irq = bit - 1; 384 385 /* Acknowledge interrupt. */ 386 bcm_pcib_set_reg(sc, REG_MSI_CLR, 1 << irq); 387 388 /* Send EOI. */ 389 bcm_pcib_set_reg(sc, REG_MSI_EOI, 1); 390 391 /* Despatch to handler. */ 392 irqsrc = &sc->msi_isrcs[irq]; 393 if (intr_isrc_dispatch(&irqsrc->isrc, tf)) 394 device_printf(sc->dev, 395 "note: unexpected interrupt (%d) triggered.\n", 396 irq); 397 398 /* Done with this interrupt. */ 399 interrupt_bitmap = interrupt_bitmap & ~(1 << irq); 400 } 401 } 402 403 static int 404 bcm_pcib_msi_intr(void *arg) 405 { 406 struct bcm_pcib_softc *sc; 407 struct trapframe *tf; 408 uint32_t interrupt_bitmap; 409 410 sc = (struct bcm_pcib_softc *) arg; 411 tf = curthread->td_intr_frame; 412 413 while ((interrupt_bitmap = bcm_pcib_read_reg(sc, REG_MSI_RAISED))) 414 bcm_pcib_msi_intr_process(sc, interrupt_bitmap, tf); 415 416 return (FILTER_HANDLED); 417 } 418 419 static int 420 bcm_pcib_alloc_msi(device_t dev, device_t child, int count, int maxcount, 421 device_t *pic, struct intr_irqsrc **srcs) 422 { 423 struct bcm_pcib_softc *sc; 424 int first_int, i; 425 426 sc = device_get_softc(dev); 427 mtx_lock(&sc->msi_mtx); 428 429 /* Find a continguous region of free message-signalled interrupts. */ 430 for (first_int = 0; first_int + count < NUM_MSI; ) { 431 for (i = first_int; i < first_int + count; ++i) { 432 if (sc->msi_isrcs[i].allocated) 433 goto next; 434 } 435 goto found; 436 next: 437 first_int = i + 1; 438 } 439 440 /* No appropriate region available. */ 441 mtx_unlock(&sc->msi_mtx); 442 device_printf(dev, "warning: failed to allocate %d MSI messages.\n", 443 count); 444 return (ENXIO); 445 446 found: 447 /* Mark the messages as in use. */ 448 for (i = 0; i < count; ++i) { 449 sc->msi_isrcs[i + first_int].allocated = true; 450 srcs[i] = &(sc->msi_isrcs[i + first_int].isrc); 451 } 452 453 mtx_unlock(&sc->msi_mtx); 454 *pic = device_get_parent(dev); 455 456 return (0); 457 } 458 459 static int 460 bcm_pcib_map_msi(device_t dev, device_t child, struct intr_irqsrc *isrc, 461 uint64_t *addr, uint32_t *data) 462 { 463 struct bcm_pcib_softc *sc; 464 struct bcm_pcib_irqsrc *msi_msg; 465 466 sc = device_get_softc(dev); 467 msi_msg = (struct bcm_pcib_irqsrc *) isrc; 468 469 *addr = sc->msi_addr; 470 *data = (REG_VALUE_MSI_CONFIG & 0xffff) | msi_msg->irq; 471 return (0); 472 } 473 474 static int 475 bcm_pcib_release_msi(device_t dev, device_t child, int count, 476 struct intr_irqsrc **isrc) 477 { 478 struct bcm_pcib_softc *sc; 479 struct bcm_pcib_irqsrc *msi_isrc; 480 int i; 481 482 sc = device_get_softc(dev); 483 mtx_lock(&sc->msi_mtx); 484 485 for (i = 0; i < count; i++) { 486 msi_isrc = (struct bcm_pcib_irqsrc *) isrc[i]; 487 msi_isrc->allocated = false; 488 } 489 490 mtx_unlock(&sc->msi_mtx); 491 return (0); 492 } 493 494 static int 495 bcm_pcib_msi_attach(device_t dev) 496 { 497 struct bcm_pcib_softc *sc; 498 phandle_t node, xref; 499 char const *bcm_name; 500 int error, i, rid; 501 502 sc = device_get_softc(dev); 503 sc->msi_addr = 0xffffffffc; 504 505 /* Clear any pending interrupts. */ 506 bcm_pcib_set_reg(sc, REG_MSI_CLR, 0xffffffff); 507 508 rid = 1; 509 sc->msi_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 510 RF_ACTIVE); 511 if (sc->msi_irq_res == NULL) { 512 device_printf(dev, "could not allocate MSI irq resource.\n"); 513 return (ENXIO); 514 } 515 516 sc->msi_isrcs = malloc(sizeof(*sc->msi_isrcs) * NUM_MSI, M_DEVBUF, 517 M_WAITOK | M_ZERO); 518 519 error = bus_setup_intr(dev, sc->msi_irq_res, INTR_TYPE_BIO | 520 INTR_MPSAFE, bcm_pcib_msi_intr, NULL, sc, &sc->msi_intr_cookie); 521 if (error != 0) { 522 device_printf(dev, "error: failed to setup MSI handler.\n"); 523 return (error); 524 } 525 526 bcm_name = device_get_nameunit(dev); 527 for (i = 0; i < NUM_MSI; i++) { 528 sc->msi_isrcs[i].irq = i; 529 error = intr_isrc_register(&sc->msi_isrcs[i].isrc, dev, 0, 530 "%s,%u", bcm_name, i); 531 if (error != 0) { 532 device_printf(dev, 533 "error: failed to register interrupt %d.\n", i); 534 return (error); 535 } 536 } 537 538 node = ofw_bus_get_node(dev); 539 xref = OF_xref_from_node(node); 540 OF_device_register_xref(xref, dev); 541 542 error = intr_msi_register(dev, xref); 543 if (error != 0) 544 return (error); 545 546 mtx_init(&sc->msi_mtx, "bcm_pcib: msi_mtx", NULL, MTX_DEF); 547 548 bcm_pcib_set_reg(sc, REG_MSI_MASK_CLR, 0xffffffff); 549 bcm_pcib_set_reg(sc, REG_MSI_ADDR_LOW, (sc->msi_addr & 0xffffffff) | 1); 550 bcm_pcib_set_reg(sc, REG_MSI_ADDR_HIGH, (sc->msi_addr >> 32)); 551 bcm_pcib_set_reg(sc, REG_MSI_CONFIG, REG_VALUE_MSI_CONFIG); 552 553 return (0); 554 } 555 556 static void 557 bcm_pcib_relocate_bridge_window(device_t dev) 558 { 559 /* 560 * In principle an out-of-bounds bridge window could be automatically 561 * adjusted at resource-activation time to lie within the bus address 562 * space by pcib_grow_window(), but that is not possible because the 563 * out-of-bounds resource allocation fails at allocation time. Instead, 564 * we will just fix up the window on the controller here, before it is 565 * re-discovered by pcib_probe_windows(). 566 */ 567 568 struct bcm_pcib_softc *sc; 569 pci_addr_t base, size, new_base, new_limit; 570 uint16_t val; 571 572 sc = device_get_softc(dev); 573 574 val = bcm_pcib_read_config(dev, 0, 0, 0, PCIR_MEMBASE_1, 2); 575 base = PCI_PPBMEMBASE(0, val); 576 577 val = bcm_pcib_read_config(dev, 0, 0, 0, PCIR_MEMLIMIT_1, 2); 578 size = PCI_PPBMEMLIMIT(0, val) - base; 579 580 new_base = sc->base.base.ranges[0].pci_base; 581 val = (uint16_t) (new_base >> 16); 582 bcm_pcib_write_config(dev, 0, 0, 0, PCIR_MEMBASE_1, val, 2); 583 584 new_limit = new_base + size; 585 val = (uint16_t) (new_limit >> 16); 586 bcm_pcib_write_config(dev, 0, 0, 0, PCIR_MEMLIMIT_1, val, 2); 587 } 588 589 static uint32_t 590 encode_cpu_window_low(pci_addr_t phys_base, bus_size_t size) 591 { 592 593 return (((phys_base >> 0x10) & 0xfff0) | 594 ((phys_base + size - 1) & 0xfff00000)); 595 } 596 597 static uint32_t 598 encode_cpu_window_start_high(pci_addr_t phys_base) 599 { 600 601 return ((phys_base >> 0x20) & 0xff); 602 } 603 604 static uint32_t 605 encode_cpu_window_end_high(pci_addr_t phys_base, bus_size_t size) 606 { 607 608 return (((phys_base + size - 1) >> 0x20) & 0xff); 609 } 610 611 static int 612 bcm_pcib_attach(device_t dev) 613 { 614 struct bcm_pcib_softc *sc; 615 pci_addr_t phys_base, pci_base; 616 bus_size_t size; 617 uint32_t hardware_rev, bridge_state, link_state; 618 int error, tries; 619 620 sc = device_get_softc(dev); 621 sc->dev = dev; 622 623 /* 624 * This tag will be used in preference to the one created in 625 * pci_host_generic.c. 626 */ 627 error = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 628 1, 0, /* alignment, bounds */ 629 DMA_HIGH_LIMIT, /* lowaddr */ 630 BUS_SPACE_MAXADDR, /* highaddr */ 631 NULL, NULL, /* filter, filterarg */ 632 DMA_HIGH_LIMIT, /* maxsize */ 633 BUS_SPACE_UNRESTRICTED, /* nsegments */ 634 DMA_HIGH_LIMIT, /* maxsegsize */ 635 0, /* flags */ 636 NULL, NULL, /* lockfunc, lockarg */ 637 &sc->dmat); 638 if (error != 0) 639 return (error); 640 641 error = pci_host_generic_setup_fdt(dev); 642 if (error != 0) 643 return (error); 644 645 error = bcm_pcib_check_ranges(dev); 646 if (error != 0) 647 return (error); 648 649 mtx_init(&sc->config_mtx, "bcm_pcib: config_mtx", NULL, MTX_DEF); 650 651 bcm_pcib_reset_controller(sc); 652 653 hardware_rev = bcm_pcib_read_reg(sc, REG_CONTROLLER_HW_REV) & 0xffff; 654 device_printf(dev, "hardware identifies as revision 0x%x.\n", 655 hardware_rev); 656 657 /* 658 * Set PCI->CPU memory window. This encodes the inbound window showing 659 * the system memory to the controller. 660 */ 661 bcm_pcib_set_reg(sc, REG_DMA_WINDOW_LOW, REG_VALUE_DMA_WINDOW_LOW); 662 bcm_pcib_set_reg(sc, REG_DMA_WINDOW_HIGH, REG_VALUE_DMA_WINDOW_HIGH); 663 bcm_pcib_set_reg(sc, REG_DMA_CONFIG, REG_VALUE_DMA_WINDOW_CONFIG); 664 665 bcm_pcib_set_reg(sc, REG_BRIDGE_GISB_WINDOW, 0); 666 bcm_pcib_set_reg(sc, REG_DMA_WINDOW_1, 0); 667 668 bcm_pcib_enable_controller(sc); 669 670 /* Wait for controller to start. */ 671 for(tries = 0; ; ++tries) { 672 bridge_state = bcm_pcib_read_reg(sc, REG_BRIDGE_STATE); 673 674 if ((bridge_state & 0x30) == 0x30) 675 /* Controller ready. */ 676 break; 677 678 if (tries > 100) { 679 device_printf(dev, 680 "error: controller failed to start.\n"); 681 return (ENXIO); 682 } 683 684 DELAY(1000); 685 } 686 687 link_state = bcm_pcib_read_reg(sc, REG_BRIDGE_LINK_STATE) >> 0x10; 688 if (!link_state) { 689 device_printf(dev, "error: controller started but link is not " 690 "up.\n"); 691 return (ENXIO); 692 } 693 if (bootverbose) 694 device_printf(dev, "note: reported link speed is %s.\n", 695 bcm_pcib_link_state_string(link_state)); 696 697 /* 698 * Set the CPU->PCI memory window. The map in this direction is not 1:1. 699 * Addresses seen by the CPU need to be adjusted to make sense to the 700 * controller as they pass through the window. 701 */ 702 pci_base = sc->base.base.ranges[0].pci_base; 703 phys_base = sc->base.base.ranges[0].phys_base; 704 size = sc->base.base.ranges[0].size; 705 706 bcm_pcib_set_reg(sc, REG_BUS_WINDOW_LOW, pci_base & 0xffffffff); 707 bcm_pcib_set_reg(sc, REG_BUS_WINDOW_HIGH, pci_base >> 32); 708 709 bcm_pcib_set_reg(sc, REG_CPU_WINDOW_LOW, 710 encode_cpu_window_low(phys_base, size)); 711 bcm_pcib_set_reg(sc, REG_CPU_WINDOW_START_HIGH, 712 encode_cpu_window_start_high(phys_base)); 713 bcm_pcib_set_reg(sc, REG_CPU_WINDOW_END_HIGH, 714 encode_cpu_window_end_high(phys_base, size)); 715 716 /* 717 * The controller starts up declaring itself an endpoint; readvertise it 718 * as a bridge. 719 */ 720 bcm_pcib_set_reg(sc, PCI_ID_VAL3, 721 PCIC_BRIDGE << CLASS_SHIFT | PCIS_BRIDGE_PCI << SUBCLASS_SHIFT); 722 723 bcm_pcib_set_reg(sc, REG_BRIDGE_SERDES_MODE, 0x2); 724 DELAY(100); 725 726 bcm_pcib_relocate_bridge_window(dev); 727 728 /* Configure interrupts. */ 729 error = bcm_pcib_msi_attach(dev); 730 if (error != 0) 731 return (error); 732 733 /* Done. */ 734 device_add_child(dev, "pci", -1); 735 return (bus_generic_attach(dev)); 736 } 737 738 /* 739 * Device method table. 740 */ 741 static device_method_t bcm_pcib_methods[] = { 742 /* Bus interface. */ 743 DEVMETHOD(bus_get_dma_tag, bcm_pcib_get_dma_tag), 744 745 /* Device interface. */ 746 DEVMETHOD(device_probe, bcm_pcib_probe), 747 DEVMETHOD(device_attach, bcm_pcib_attach), 748 749 /* PCIB interface. */ 750 DEVMETHOD(pcib_read_config, bcm_pcib_read_config), 751 DEVMETHOD(pcib_write_config, bcm_pcib_write_config), 752 753 /* MSI interface. */ 754 DEVMETHOD(msi_alloc_msi, bcm_pcib_alloc_msi), 755 DEVMETHOD(msi_release_msi, bcm_pcib_release_msi), 756 DEVMETHOD(msi_map_msi, bcm_pcib_map_msi), 757 758 DEVMETHOD_END 759 }; 760 761 DEFINE_CLASS_1(pcib, bcm_pcib_driver, bcm_pcib_methods, 762 sizeof(struct bcm_pcib_softc), generic_pcie_fdt_driver); 763 764 DRIVER_MODULE(bcm_pcib, simplebus, bcm_pcib_driver, 0, 0); 765 766