1 /*- 2 * Copyright (c) 2013 Ian Lepore <ian@freebsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 #include "opt_platform.h" 28 29 #include <sys/cdefs.h> 30 __FBSDID("$FreeBSD$"); 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/bus.h> 35 #include <sys/reboot.h> 36 37 #include <vm/vm.h> 38 39 #include <machine/bus.h> 40 #include <machine/devmap.h> 41 #include <machine/intr.h> 42 #include <machine/machdep.h> 43 #include <machine/platformvar.h> 44 45 #include <arm/arm/mpcore_timervar.h> 46 #include <arm/freescale/imx/imx6_anatopreg.h> 47 #include <arm/freescale/imx/imx6_anatopvar.h> 48 #include <arm/freescale/imx/imx_machdep.h> 49 50 #include <dev/fdt/fdt_common.h> 51 #include <dev/ofw/openfirm.h> 52 53 #include "platform_if.h" 54 55 struct fdt_fixup_entry fdt_fixup_table[] = { 56 { NULL, NULL } 57 }; 58 59 static uint32_t gpio1_node; 60 61 #ifndef ARM_INTRNG 62 /* 63 * Work around the linux workaround for imx6 erratum 006687, in which some 64 * ethernet interrupts don't go to the GPC and thus won't wake the system from 65 * Wait mode. We don't use Wait mode (which halts the GIC, leaving only GPC 66 * interrupts able to wake the system), so we don't experience the bug at all. 67 * The linux workaround is to reconfigure GPIO1_6 as the ENET interrupt by 68 * writing magic values to an undocumented IOMUX register, then letting the gpio 69 * interrupt driver notify the ethernet driver. We'll be able to do all that 70 * (even though we don't need to) once the INTRNG project is committed and the 71 * imx_gpio driver becomes an interrupt driver. Until then, this crazy little 72 * workaround watches for requests to map an interrupt 6 with the interrupt 73 * controller node referring to gpio1, and it substitutes the proper ffec 74 * interrupt number. 75 */ 76 static int 77 imx6_decode_fdt(uint32_t iparent, uint32_t *intr, int *interrupt, 78 int *trig, int *pol) 79 { 80 81 if (fdt32_to_cpu(intr[0]) == 6 && 82 OF_node_from_xref(iparent) == gpio1_node) { 83 *interrupt = 150; 84 *trig = INTR_TRIGGER_CONFORM; 85 *pol = INTR_POLARITY_CONFORM; 86 return (0); 87 } 88 return (gic_decode_fdt(iparent, intr, interrupt, trig, pol)); 89 } 90 91 fdt_pic_decode_t fdt_pic_table[] = { 92 &imx6_decode_fdt, 93 NULL 94 }; 95 #endif 96 97 static vm_offset_t 98 imx6_lastaddr(platform_t plat) 99 { 100 101 return (arm_devmap_lastaddr()); 102 } 103 104 static int 105 imx6_attach(platform_t plat) 106 { 107 108 /* Inform the MPCore timer driver that its clock is variable. */ 109 arm_tmr_change_frequency(ARM_TMR_FREQUENCY_VARIES); 110 111 return (0); 112 } 113 114 static void 115 imx6_late_init(platform_t plat) 116 { 117 118 /* Cache the gpio1 node handle for imx6_decode_fdt() workaround code. */ 119 gpio1_node = OF_node_from_xref( 120 OF_finddevice("/soc/aips-bus@02000000/gpio@0209c000")); 121 } 122 123 /* 124 * Set up static device mappings. 125 * 126 * This attempts to cover the most-used devices with 1MB section mappings, which 127 * is good for performance (uses fewer TLB entries for device access). 128 * 129 * ARMMP covers the interrupt controller, MPCore timers, global timer, and the 130 * L2 cache controller. Most of the 1MB range is unused reserved space. 131 * 132 * AIPS1/AIPS2 cover most of the on-chip devices such as uart, spi, i2c, etc. 133 * 134 * Notably not mapped right now are HDMI, GPU, and other devices below ARMMP in 135 * the memory map. When we get support for graphics it might make sense to 136 * static map some of that area. Be careful with other things in that area such 137 * as OCRAM that probably shouldn't be mapped as PTE_DEVICE memory. 138 */ 139 static int 140 imx6_devmap_init(platform_t plat) 141 { 142 const uint32_t IMX6_ARMMP_PHYS = 0x00a00000; 143 const uint32_t IMX6_ARMMP_SIZE = 0x00100000; 144 const uint32_t IMX6_AIPS1_PHYS = 0x02000000; 145 const uint32_t IMX6_AIPS1_SIZE = 0x00100000; 146 const uint32_t IMX6_AIPS2_PHYS = 0x02100000; 147 const uint32_t IMX6_AIPS2_SIZE = 0x00100000; 148 149 arm_devmap_add_entry(IMX6_ARMMP_PHYS, IMX6_ARMMP_SIZE); 150 arm_devmap_add_entry(IMX6_AIPS1_PHYS, IMX6_AIPS1_SIZE); 151 arm_devmap_add_entry(IMX6_AIPS2_PHYS, IMX6_AIPS2_SIZE); 152 153 return (0); 154 } 155 156 void 157 cpu_reset(void) 158 { 159 const uint32_t IMX6_WDOG_CR_PHYS = 0x020bc000; 160 161 imx_wdog_cpu_reset(IMX6_WDOG_CR_PHYS); 162 } 163 164 /* 165 * Determine what flavor of imx6 we're running on. 166 * 167 * This code is based on the way u-boot does it. Information found on the web 168 * indicates that Freescale themselves were the original source of this logic, 169 * including the strange check for number of CPUs in the SCU configuration 170 * register, which is apparently needed on some revisions of the SOLO. 171 * 172 * According to the documentation, there is such a thing as an i.MX6 Dual 173 * (non-lite flavor). However, Freescale doesn't seem to have assigned it a 174 * number or provided any logic to handle it in their detection code. 175 * 176 * Note that the ANALOG_DIGPROG and SCU configuration registers are not 177 * documented in the chip reference manual. (SCU configuration is mentioned, 178 * but not mapped out in detail.) I think the bottom two bits of the scu config 179 * register may be ncpu-1. 180 * 181 * This hasn't been tested yet on a dual[-lite]. 182 * 183 * On a solo: 184 * digprog = 0x00610001 185 * hwsoc = 0x00000062 186 * scu config = 0x00000500 187 * On a quad: 188 * digprog = 0x00630002 189 * hwsoc = 0x00000063 190 * scu config = 0x00005503 191 */ 192 u_int imx_soc_type() 193 { 194 uint32_t digprog, hwsoc; 195 uint32_t *pcr; 196 static u_int soctype; 197 const vm_offset_t SCU_CONFIG_PHYSADDR = 0x00a00004; 198 #define HWSOC_MX6SL 0x60 199 #define HWSOC_MX6DL 0x61 200 #define HWSOC_MX6SOLO 0x62 201 #define HWSOC_MX6Q 0x63 202 203 if (soctype != 0) 204 return (soctype); 205 206 digprog = imx6_anatop_read_4(IMX6_ANALOG_DIGPROG_SL); 207 hwsoc = (digprog >> IMX6_ANALOG_DIGPROG_SOCTYPE_SHIFT) & 208 IMX6_ANALOG_DIGPROG_SOCTYPE_MASK; 209 210 if (hwsoc != HWSOC_MX6SL) { 211 digprog = imx6_anatop_read_4(IMX6_ANALOG_DIGPROG); 212 hwsoc = (digprog & IMX6_ANALOG_DIGPROG_SOCTYPE_MASK) >> 213 IMX6_ANALOG_DIGPROG_SOCTYPE_SHIFT; 214 /*printf("digprog = 0x%08x\n", digprog);*/ 215 if (hwsoc == HWSOC_MX6DL) { 216 pcr = arm_devmap_ptov(SCU_CONFIG_PHYSADDR, 4); 217 if (pcr != NULL) { 218 /*printf("scu config = 0x%08x\n", *pcr);*/ 219 if ((*pcr & 0x03) == 0) { 220 hwsoc = HWSOC_MX6SOLO; 221 } 222 } 223 } 224 } 225 /* printf("hwsoc 0x%08x\n", hwsoc); */ 226 227 switch (hwsoc) { 228 case HWSOC_MX6SL: 229 soctype = IMXSOC_6SL; 230 break; 231 case HWSOC_MX6SOLO: 232 soctype = IMXSOC_6S; 233 break; 234 case HWSOC_MX6DL: 235 soctype = IMXSOC_6DL; 236 break; 237 case HWSOC_MX6Q : 238 soctype = IMXSOC_6Q; 239 break; 240 default: 241 printf("imx_soc_type: Don't understand hwsoc 0x%02x, " 242 "digprog 0x%08x; assuming IMXSOC_6Q\n", hwsoc, digprog); 243 soctype = IMXSOC_6Q; 244 break; 245 } 246 247 return (soctype); 248 } 249 250 /* 251 * Early putc routine for EARLY_PRINTF support. To use, add to kernel config: 252 * option SOCDEV_PA=0x02000000 253 * option SOCDEV_VA=0x02000000 254 * option EARLY_PRINTF 255 * Resist the temptation to change the #if 0 to #ifdef EARLY_PRINTF here. It 256 * makes sense now, but if multiple SOCs do that it will make early_putc another 257 * duplicate symbol to be eliminated on the path to a generic kernel. 258 */ 259 #if 0 260 static void 261 imx6_early_putc(int c) 262 { 263 volatile uint32_t * UART_STAT_REG = (uint32_t *)0x02020098; 264 volatile uint32_t * UART_TX_REG = (uint32_t *)0x02020040; 265 const uint32_t UART_TXRDY = (1 << 3); 266 267 while ((*UART_STAT_REG & UART_TXRDY) == 0) 268 continue; 269 *UART_TX_REG = c; 270 } 271 early_putc_t *early_putc = imx6_early_putc; 272 #endif 273 274 static platform_method_t imx6_methods[] = { 275 PLATFORMMETHOD(platform_attach, imx6_attach), 276 PLATFORMMETHOD(platform_lastaddr, imx6_lastaddr), 277 PLATFORMMETHOD(platform_devmap_init, imx6_devmap_init), 278 PLATFORMMETHOD(platform_late_init, imx6_late_init), 279 280 PLATFORMMETHOD_END, 281 }; 282 283 FDT_PLATFORM_DEF2(imx6, imx6s, "i.MX6 Solo", 0, "fsl,imx6s"); 284 FDT_PLATFORM_DEF2(imx6, imx6d, "i.MX6 Dual", 0, "fsl,imx6d"); 285 FDT_PLATFORM_DEF2(imx6, imx6q, "i.MX6 Quad", 0, "fsl,imx6q"); 286