1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2014 Juergen Weiss <weiss@uni-mainz.de> 5 * Copyright (c) 2014 Ian Lepore <ian@freebsd.org> 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 #include <sys/param.h> 31 #include <sys/systm.h> 32 #include <sys/bus.h> 33 #include <sys/kernel.h> 34 #include <sys/lock.h> 35 #include <sys/mutex.h> 36 #include <sys/smp.h> 37 38 #include <vm/vm.h> 39 #include <vm/pmap.h> 40 41 #include <machine/cpu.h> 42 #include <machine/smp.h> 43 #include <machine/fdt.h> 44 #include <machine/intr.h> 45 #include <machine/platform.h> 46 #include <machine/platformvar.h> 47 48 #include <arm/freescale/imx/imx6_machdep.h> 49 50 #define SCU_PHYSBASE 0x00a00000 51 #define SCU_SIZE 0x00001000 52 53 #define SCU_CONTROL_REG 0x00 54 #define SCU_CONTROL_ENABLE (1 << 0) 55 #define SCU_CONFIG_REG 0x04 56 #define SCU_CONFIG_REG_NCPU_MASK 0x03 57 #define SCU_CPUPOWER_REG 0x08 58 #define SCU_INV_TAGS_REG 0x0c 59 #define SCU_DIAG_CONTROL 0x30 60 #define SCU_DIAG_DISABLE_MIGBIT (1 << 0) 61 #define SCU_FILTER_START_REG 0x40 62 #define SCU_FILTER_END_REG 0x44 63 #define SCU_SECURE_ACCESS_REG 0x50 64 #define SCU_NONSECURE_ACCESS_REG 0x54 65 66 #define SRC_PHYSBASE 0x020d8000 67 #define SRC_SIZE 0x4000 68 #define SRC_CONTROL_REG 0x00 69 #define SRC_CONTROL_C1ENA_SHIFT 22 /* Bit for Core 1 enable */ 70 #define SRC_CONTROL_C1RST_SHIFT 14 /* Bit for Core 1 reset */ 71 #define SRC_GPR0_C1FUNC 0x20 /* Register for Core 1 entry func */ 72 #define SRC_GPR1_C1ARG 0x24 /* Register for Core 1 entry arg */ 73 74 void 75 imx6_mp_setmaxid(platform_t plat) 76 { 77 bus_space_handle_t scu; 78 int hwcpu, ncpu; 79 uint32_t val; 80 81 /* If we've already set the global vars don't bother to do it again. */ 82 if (mp_ncpus != 0) 83 return; 84 85 if (bus_space_map(fdtbus_bs_tag, SCU_PHYSBASE, SCU_SIZE, 0, &scu) != 0) 86 panic("Couldn't map the SCU\n"); 87 val = bus_space_read_4(fdtbus_bs_tag, scu, SCU_CONFIG_REG); 88 hwcpu = (val & SCU_CONFIG_REG_NCPU_MASK) + 1; 89 bus_space_unmap(fdtbus_bs_tag, scu, SCU_SIZE); 90 91 ncpu = hwcpu; 92 TUNABLE_INT_FETCH("hw.ncpu", &ncpu); 93 if (ncpu < 1 || ncpu > hwcpu) 94 ncpu = hwcpu; 95 96 mp_ncpus = ncpu; 97 mp_maxid = ncpu - 1; 98 } 99 100 void 101 imx6_mp_start_ap(platform_t plat) 102 { 103 bus_space_handle_t scu; 104 bus_space_handle_t src; 105 106 uint32_t val; 107 int i; 108 109 if (bus_space_map(fdtbus_bs_tag, SCU_PHYSBASE, SCU_SIZE, 0, &scu) != 0) 110 panic("Couldn't map the SCU\n"); 111 if (bus_space_map(fdtbus_bs_tag, SRC_PHYSBASE, SRC_SIZE, 0, &src) != 0) 112 panic("Couldn't map the system reset controller (SRC)\n"); 113 114 /* 115 * Invalidate SCU cache tags. The 0x0000ffff constant invalidates all 116 * ways on all cores 0-3. Per the ARM docs, it's harmless to write to 117 * the bits for cores that are not present. 118 */ 119 bus_space_write_4(fdtbus_bs_tag, scu, SCU_INV_TAGS_REG, 0x0000ffff); 120 121 /* 122 * Erratum ARM/MP: 764369 (problems with cache maintenance). 123 * Setting the "disable-migratory bit" in the undocumented SCU 124 * Diagnostic Control Register helps work around the problem. 125 */ 126 val = bus_space_read_4(fdtbus_bs_tag, scu, SCU_DIAG_CONTROL); 127 bus_space_write_4(fdtbus_bs_tag, scu, SCU_DIAG_CONTROL, 128 val | SCU_DIAG_DISABLE_MIGBIT); 129 130 /* 131 * Enable the SCU, then clean the cache on this core. After these two 132 * operations the cache tag ram in the SCU is coherent with the contents 133 * of the cache on this core. The other cores aren't running yet so 134 * their caches can't contain valid data yet, but we've initialized 135 * their SCU tag ram above, so they will be coherent from startup. 136 */ 137 val = bus_space_read_4(fdtbus_bs_tag, scu, SCU_CONTROL_REG); 138 bus_space_write_4(fdtbus_bs_tag, scu, SCU_CONTROL_REG, 139 val | SCU_CONTROL_ENABLE); 140 dcache_wbinv_poc_all(); 141 142 /* 143 * For each AP core, set the entry point address and argument registers, 144 * and set the core-enable and core-reset bits in the control register. 145 */ 146 val = bus_space_read_4(fdtbus_bs_tag, src, SRC_CONTROL_REG); 147 for (i=1; i < mp_ncpus; i++) { 148 bus_space_write_4(fdtbus_bs_tag, src, SRC_GPR0_C1FUNC + 8*i, 149 pmap_kextract((vm_offset_t)mpentry)); 150 bus_space_write_4(fdtbus_bs_tag, src, SRC_GPR1_C1ARG + 8*i, 0); 151 152 val |= ((1 << (SRC_CONTROL_C1ENA_SHIFT - 1 + i )) | 153 ( 1 << (SRC_CONTROL_C1RST_SHIFT - 1 + i))); 154 } 155 bus_space_write_4(fdtbus_bs_tag, src, SRC_CONTROL_REG, val); 156 157 dsb(); 158 sev(); 159 160 bus_space_unmap(fdtbus_bs_tag, scu, SCU_SIZE); 161 bus_space_unmap(fdtbus_bs_tag, src, SRC_SIZE); 162 } 163