1 /*- 2 * Copyright (C) 2008-2009 Semihalf, Michal Hajduk 3 * Copyright (c) 2012, 2013 The FreeBSD Foundation 4 * Copyright (c) 2015 Ian Lepore <ian@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Portions of this software were developed by Oleksandr Rybalko 8 * under sponsorship from the FreeBSD Foundation. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 */ 31 32 /* 33 * I2C driver for Freescale i.MX hardware. 34 * 35 * Note that the hardware is capable of running as both a master and a slave. 36 * This driver currently implements only master-mode operations. 37 * 38 * This driver supports multi-master i2c buses, by detecting bus arbitration 39 * loss and returning IIC_EBUSBSY status. Notably, it does not do any kind of 40 * retries if some other master jumps onto the bus and interrupts one of our 41 * transfer cycles resulting in arbitration loss in mid-transfer. The caller 42 * must handle retries in a way that makes sense for the slave being addressed. 43 */ 44 45 #include <sys/cdefs.h> 46 __FBSDID("$FreeBSD$"); 47 48 #include <sys/param.h> 49 #include <sys/systm.h> 50 #include <sys/bus.h> 51 #include <sys/kernel.h> 52 #include <sys/limits.h> 53 #include <sys/module.h> 54 #include <sys/resource.h> 55 56 #include <machine/bus.h> 57 #include <machine/resource.h> 58 #include <sys/rman.h> 59 60 #include <arm/freescale/imx/imx_ccmvar.h> 61 62 #include <dev/iicbus/iiconf.h> 63 #include <dev/iicbus/iicbus.h> 64 #include "iicbus_if.h" 65 66 #include <dev/ofw/openfirm.h> 67 #include <dev/ofw/ofw_bus.h> 68 #include <dev/ofw/ofw_bus_subr.h> 69 70 #define I2C_ADDR_REG 0x00 /* I2C slave address register */ 71 #define I2C_FDR_REG 0x04 /* I2C frequency divider register */ 72 #define I2C_CONTROL_REG 0x08 /* I2C control register */ 73 #define I2C_STATUS_REG 0x0C /* I2C status register */ 74 #define I2C_DATA_REG 0x10 /* I2C data register */ 75 #define I2C_DFSRR_REG 0x14 /* I2C Digital Filter Sampling rate */ 76 77 #define I2CCR_MEN (1 << 7) /* Module enable */ 78 #define I2CCR_MSTA (1 << 5) /* Master/slave mode */ 79 #define I2CCR_MTX (1 << 4) /* Transmit/receive mode */ 80 #define I2CCR_TXAK (1 << 3) /* Transfer acknowledge */ 81 #define I2CCR_RSTA (1 << 2) /* Repeated START */ 82 83 #define I2CSR_MCF (1 << 7) /* Data transfer */ 84 #define I2CSR_MASS (1 << 6) /* Addressed as a slave */ 85 #define I2CSR_MBB (1 << 5) /* Bus busy */ 86 #define I2CSR_MAL (1 << 4) /* Arbitration lost */ 87 #define I2CSR_SRW (1 << 2) /* Slave read/write */ 88 #define I2CSR_MIF (1 << 1) /* Module interrupt */ 89 #define I2CSR_RXAK (1 << 0) /* Received acknowledge */ 90 91 #define I2C_BAUD_RATE_FAST 0x31 92 #define I2C_BAUD_RATE_DEF 0x3F 93 #define I2C_DFSSR_DIV 0x10 94 95 /* 96 * A table of available divisors and the associated coded values to put in the 97 * FDR register to achieve that divisor.. There is no algorithmic relationship I 98 * can see between divisors and the codes that go into the register. The table 99 * begins and ends with entries that handle insane configuration values. 100 */ 101 struct clkdiv { 102 u_int divisor; 103 u_int regcode; 104 }; 105 static struct clkdiv clkdiv_table[] = { 106 { 0, 0x20 }, { 22, 0x20 }, { 24, 0x21 }, { 26, 0x22 }, 107 { 28, 0x23 }, { 30, 0x00 }, { 32, 0x24 }, { 36, 0x25 }, 108 { 40, 0x26 }, { 42, 0x03 }, { 44, 0x27 }, { 48, 0x28 }, 109 { 52, 0x05 }, { 56, 0x29 }, { 60, 0x06 }, { 64, 0x2a }, 110 { 72, 0x2b }, { 80, 0x2c }, { 88, 0x09 }, { 96, 0x2d }, 111 { 104, 0x0a }, { 112, 0x2e }, { 128, 0x2f }, { 144, 0x0c }, 112 { 160, 0x30 }, { 192, 0x31 }, { 224, 0x32 }, { 240, 0x0f }, 113 { 256, 0x33 }, { 288, 0x10 }, { 320, 0x34 }, { 384, 0x35 }, 114 { 448, 0x36 }, { 480, 0x13 }, { 512, 0x37 }, { 576, 0x14 }, 115 { 640, 0x38 }, { 768, 0x39 }, { 896, 0x3a }, { 960, 0x17 }, 116 { 1024, 0x3b }, { 1152, 0x18 }, { 1280, 0x3c }, { 1536, 0x3d }, 117 { 1792, 0x3e }, { 1920, 0x1b }, { 2048, 0x3f }, { 2304, 0x1c }, 118 { 2560, 0x1d }, { 3072, 0x1e }, { 3840, 0x1f }, {UINT_MAX, 0x1f} 119 }; 120 121 static struct ofw_compat_data compat_data[] = { 122 {"fsl,imx6q-i2c", 1}, 123 {"fsl,imx-i2c", 1}, 124 {NULL, 0} 125 }; 126 127 struct i2c_softc { 128 device_t dev; 129 device_t iicbus; 130 struct resource *res; 131 int rid; 132 sbintime_t byte_time_sbt; 133 }; 134 135 static phandle_t i2c_get_node(device_t, device_t); 136 static int i2c_probe(device_t); 137 static int i2c_attach(device_t); 138 139 static int i2c_repeated_start(device_t, u_char, int); 140 static int i2c_start(device_t, u_char, int); 141 static int i2c_stop(device_t); 142 static int i2c_reset(device_t, u_char, u_char, u_char *); 143 static int i2c_read(device_t, char *, int, int *, int, int); 144 static int i2c_write(device_t, const char *, int, int *, int); 145 146 static device_method_t i2c_methods[] = { 147 DEVMETHOD(device_probe, i2c_probe), 148 DEVMETHOD(device_attach, i2c_attach), 149 150 /* OFW methods */ 151 DEVMETHOD(ofw_bus_get_node, i2c_get_node), 152 153 DEVMETHOD(iicbus_callback, iicbus_null_callback), 154 DEVMETHOD(iicbus_repeated_start, i2c_repeated_start), 155 DEVMETHOD(iicbus_start, i2c_start), 156 DEVMETHOD(iicbus_stop, i2c_stop), 157 DEVMETHOD(iicbus_reset, i2c_reset), 158 DEVMETHOD(iicbus_read, i2c_read), 159 DEVMETHOD(iicbus_write, i2c_write), 160 DEVMETHOD(iicbus_transfer, iicbus_transfer_gen), 161 162 DEVMETHOD_END 163 }; 164 165 static driver_t i2c_driver = { 166 "iichb", 167 i2c_methods, 168 sizeof(struct i2c_softc), 169 }; 170 static devclass_t i2c_devclass; 171 172 DRIVER_MODULE(i2c, simplebus, i2c_driver, i2c_devclass, 0, 0); 173 DRIVER_MODULE(iicbus, i2c, iicbus_driver, iicbus_devclass, 0, 0); 174 175 static phandle_t 176 i2c_get_node(device_t bus, device_t dev) 177 { 178 /* 179 * Share controller node with iicbus device 180 */ 181 return ofw_bus_get_node(bus); 182 } 183 184 static __inline void 185 i2c_write_reg(struct i2c_softc *sc, bus_size_t off, uint8_t val) 186 { 187 188 bus_write_1(sc->res, off, val); 189 } 190 191 static __inline uint8_t 192 i2c_read_reg(struct i2c_softc *sc, bus_size_t off) 193 { 194 195 return (bus_read_1(sc->res, off)); 196 } 197 198 static __inline void 199 i2c_flag_set(struct i2c_softc *sc, bus_size_t off, uint8_t mask) 200 { 201 uint8_t status; 202 203 status = i2c_read_reg(sc, off); 204 status |= mask; 205 i2c_write_reg(sc, off, status); 206 } 207 208 /* Wait for bus to become busy or not-busy. */ 209 static int 210 wait_for_busbusy(struct i2c_softc *sc, int wantbusy) 211 { 212 int retry, srb; 213 214 retry = 1000; 215 while (retry --) { 216 srb = i2c_read_reg(sc, I2C_STATUS_REG) & I2CSR_MBB; 217 if ((srb && wantbusy) || (!srb && !wantbusy)) 218 return (IIC_NOERR); 219 DELAY(1); 220 } 221 return (IIC_ETIMEOUT); 222 } 223 224 /* Wait for transfer to complete, optionally check RXAK. */ 225 static int 226 wait_for_xfer(struct i2c_softc *sc, int checkack) 227 { 228 int retry, sr; 229 230 /* 231 * Sleep for about the time it takes to transfer a byte (with precision 232 * set to tolerate 5% oversleep). We calculate the approximate byte 233 * transfer time when we set the bus speed divisor. Slaves are allowed 234 * to do clock-stretching so the actual transfer time can be larger, but 235 * this gets the bulk of the waiting out of the way without tying up the 236 * processor the whole time. 237 */ 238 pause_sbt("imxi2c", sc->byte_time_sbt, sc->byte_time_sbt / 20, 0); 239 240 retry = 10000; 241 while (retry --) { 242 sr = i2c_read_reg(sc, I2C_STATUS_REG); 243 if (sr & I2CSR_MIF) { 244 if (sr & I2CSR_MAL) 245 return (IIC_EBUSERR); 246 else if (checkack && (sr & I2CSR_RXAK)) 247 return (IIC_ENOACK); 248 else 249 return (IIC_NOERR); 250 } 251 DELAY(1); 252 } 253 return (IIC_ETIMEOUT); 254 } 255 256 /* 257 * Implement the error handling shown in the state diagram of the imx6 reference 258 * manual. If there was an error, then: 259 * - Clear master mode (MSTA and MTX). 260 * - Wait for the bus to become free or for a timeout to happen. 261 * - Disable the controller. 262 */ 263 static int 264 i2c_error_handler(struct i2c_softc *sc, int error) 265 { 266 267 if (error != 0) { 268 i2c_write_reg(sc, I2C_STATUS_REG, 0); 269 i2c_write_reg(sc, I2C_CONTROL_REG, I2CCR_MEN); 270 wait_for_busbusy(sc, false); 271 i2c_write_reg(sc, I2C_CONTROL_REG, 0); 272 } 273 return (error); 274 } 275 276 static int 277 i2c_probe(device_t dev) 278 { 279 280 if (!ofw_bus_status_okay(dev)) 281 return (ENXIO); 282 283 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) 284 return (ENXIO); 285 286 device_set_desc(dev, "Freescale i.MX I2C"); 287 288 return (BUS_PROBE_DEFAULT); 289 } 290 291 static int 292 i2c_attach(device_t dev) 293 { 294 struct i2c_softc *sc; 295 296 sc = device_get_softc(dev); 297 sc->dev = dev; 298 sc->rid = 0; 299 300 sc->res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->rid, 301 RF_ACTIVE); 302 if (sc->res == NULL) { 303 device_printf(dev, "could not allocate resources"); 304 return (ENXIO); 305 } 306 307 sc->iicbus = device_add_child(dev, "iicbus", -1); 308 if (sc->iicbus == NULL) { 309 device_printf(dev, "could not add iicbus child"); 310 return (ENXIO); 311 } 312 313 bus_generic_attach(dev); 314 return (0); 315 } 316 317 static int 318 i2c_repeated_start(device_t dev, u_char slave, int timeout) 319 { 320 struct i2c_softc *sc; 321 int error; 322 323 sc = device_get_softc(dev); 324 325 if ((i2c_read_reg(sc, I2C_STATUS_REG) & I2CSR_MBB) == 0) { 326 return (IIC_EBUSERR); 327 } 328 329 /* 330 * Set repeated start condition, delay (per reference manual, min 156nS) 331 * before writing slave address, wait for ack after write. 332 */ 333 i2c_flag_set(sc, I2C_CONTROL_REG, I2CCR_RSTA); 334 DELAY(1); 335 i2c_write_reg(sc, I2C_STATUS_REG, 0x0); 336 i2c_write_reg(sc, I2C_DATA_REG, slave); 337 error = wait_for_xfer(sc, true); 338 return (i2c_error_handler(sc, error)); 339 } 340 341 static int 342 i2c_start(device_t dev, u_char slave, int timeout) 343 { 344 struct i2c_softc *sc; 345 int error; 346 347 sc = device_get_softc(dev); 348 349 i2c_write_reg(sc, I2C_CONTROL_REG, I2CCR_MEN); 350 DELAY(10); /* Delay for controller to sample bus state. */ 351 if (i2c_read_reg(sc, I2C_STATUS_REG) & I2CSR_MBB) { 352 return (i2c_error_handler(sc, IIC_EBUSERR)); 353 } 354 i2c_write_reg(sc, I2C_CONTROL_REG, I2CCR_MEN | I2CCR_MSTA | I2CCR_MTX); 355 if ((error = wait_for_busbusy(sc, true)) != IIC_NOERR) 356 return (i2c_error_handler(sc, error)); 357 i2c_write_reg(sc, I2C_STATUS_REG, 0); 358 i2c_write_reg(sc, I2C_DATA_REG, slave); 359 error = wait_for_xfer(sc, true); 360 return (i2c_error_handler(sc, error)); 361 } 362 363 static int 364 i2c_stop(device_t dev) 365 { 366 struct i2c_softc *sc; 367 368 sc = device_get_softc(dev); 369 370 i2c_write_reg(sc, I2C_CONTROL_REG, I2CCR_MEN); 371 wait_for_busbusy(sc, false); 372 i2c_write_reg(sc, I2C_CONTROL_REG, 0); 373 return (IIC_NOERR); 374 } 375 376 static int 377 i2c_reset(device_t dev, u_char speed, u_char addr, u_char *oldadr) 378 { 379 struct i2c_softc *sc; 380 u_int busfreq, div, i, ipgfreq; 381 382 sc = device_get_softc(dev); 383 384 /* 385 * Look up the divisor that gives the nearest speed that doesn't exceed 386 * the configured value for the bus. 387 */ 388 ipgfreq = imx_ccm_ipg_hz(); 389 busfreq = IICBUS_GET_FREQUENCY(sc->iicbus, speed); 390 div = howmany(ipgfreq, busfreq); 391 for (i = 0; i < nitems(clkdiv_table); i++) { 392 if (clkdiv_table[i].divisor >= div) 393 break; 394 } 395 396 /* 397 * Calculate roughly how long it will take to transfer a byte (which 398 * requires 9 clock cycles) at the new bus speed. This value is used to 399 * pause() while waiting for transfer-complete. With a 66MHz IPG clock 400 * and the actual i2c bus speeds that leads to, for nominal 100KHz and 401 * 400KHz bus speeds the transfer times are roughly 104uS and 22uS. 402 */ 403 busfreq = ipgfreq / clkdiv_table[i].divisor; 404 sc->byte_time_sbt = SBT_1US * (9000000 / busfreq); 405 406 /* 407 * Disable the controller (do the reset), and set the new clock divisor. 408 */ 409 i2c_write_reg(sc, I2C_STATUS_REG, 0x0); 410 i2c_write_reg(sc, I2C_CONTROL_REG, 0x0); 411 i2c_write_reg(sc, I2C_FDR_REG, (uint8_t)clkdiv_table[i].regcode); 412 return (IIC_NOERR); 413 } 414 415 static int 416 i2c_read(device_t dev, char *buf, int len, int *read, int last, int delay) 417 { 418 struct i2c_softc *sc; 419 int error, reg; 420 421 sc = device_get_softc(dev); 422 *read = 0; 423 424 if (len) { 425 if (len == 1) 426 i2c_write_reg(sc, I2C_CONTROL_REG, I2CCR_MEN | 427 I2CCR_MSTA | I2CCR_TXAK); 428 else 429 i2c_write_reg(sc, I2C_CONTROL_REG, I2CCR_MEN | 430 I2CCR_MSTA); 431 /* Dummy read to prime the receiver. */ 432 i2c_write_reg(sc, I2C_STATUS_REG, 0x0); 433 i2c_read_reg(sc, I2C_DATA_REG); 434 } 435 436 error = 0; 437 *read = 0; 438 while (*read < len) { 439 if ((error = wait_for_xfer(sc, false)) != IIC_NOERR) 440 break; 441 i2c_write_reg(sc, I2C_STATUS_REG, 0x0); 442 if (last) { 443 if (*read == len - 2) { 444 /* NO ACK on last byte */ 445 i2c_write_reg(sc, I2C_CONTROL_REG, I2CCR_MEN | 446 I2CCR_MSTA | I2CCR_TXAK); 447 } else if (*read == len - 1) { 448 /* Transfer done, signal stop. */ 449 i2c_write_reg(sc, I2C_CONTROL_REG, I2CCR_MEN | 450 I2CCR_TXAK); 451 wait_for_busbusy(sc, false); 452 } 453 } 454 reg = i2c_read_reg(sc, I2C_DATA_REG); 455 *buf++ = reg; 456 (*read)++; 457 } 458 459 return (i2c_error_handler(sc, error)); 460 } 461 462 static int 463 i2c_write(device_t dev, const char *buf, int len, int *sent, int timeout) 464 { 465 struct i2c_softc *sc; 466 int error; 467 468 sc = device_get_softc(dev); 469 470 error = 0; 471 *sent = 0; 472 while (*sent < len) { 473 i2c_write_reg(sc, I2C_STATUS_REG, 0x0); 474 i2c_write_reg(sc, I2C_DATA_REG, *buf++); 475 if ((error = wait_for_xfer(sc, true)) != IIC_NOERR) 476 break; 477 (*sent)++; 478 } 479 480 return (i2c_error_handler(sc, error)); 481 } 482