1 /*- 2 * Copyright (c) 2014 Ruslan Bukin <br@bsdpad.com> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 /* 28 * Vybrid Family 12-bit Analog to Digital Converter (ADC) 29 * Chapter 37, Vybrid Reference Manual, Rev. 5, 07/2013 30 */ 31 32 #include <sys/cdefs.h> 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/bus.h> 36 #include <sys/kernel.h> 37 #include <sys/module.h> 38 #include <sys/malloc.h> 39 #include <sys/rman.h> 40 #include <sys/timeet.h> 41 #include <sys/timetc.h> 42 43 #include <dev/ofw/openfirm.h> 44 #include <dev/ofw/ofw_bus.h> 45 #include <dev/ofw/ofw_bus_subr.h> 46 47 #include <machine/bus.h> 48 #include <machine/cpu.h> 49 #include <machine/intr.h> 50 51 #include <arm/freescale/vybrid/vf_common.h> 52 #include <arm/freescale/vybrid/vf_adc.h> 53 54 #define ADC_HC0 0x00 /* Ctrl reg for hardware triggers */ 55 #define ADC_HC1 0x04 /* Ctrl reg for hardware triggers */ 56 #define HC_AIEN (1 << 7) /* Conversion Complete Int Control */ 57 #define HC_ADCH_M 0x1f /* Input Channel Select Mask */ 58 #define HC_ADCH_S 0 /* Input Channel Select Shift */ 59 #define ADC_HS 0x08 /* Status register for HW triggers */ 60 #define HS_COCO0 (1 << 0) /* Conversion Complete Flag */ 61 #define HS_COCO1 (1 << 1) /* Conversion Complete Flag */ 62 #define ADC_R0 0x0C /* Data result reg for HW triggers */ 63 #define ADC_R1 0x10 /* Data result reg for HW triggers */ 64 #define ADC_CFG 0x14 /* Configuration register */ 65 #define CFG_OVWREN (1 << 16) /* Data Overwrite Enable */ 66 #define CFG_AVGS_M 0x3 /* Hardware Average select Mask */ 67 #define CFG_AVGS_S 14 /* Hardware Average select Shift */ 68 #define CFG_ADTRG (1 << 13) /* Conversion Trigger Select */ 69 #define CFG_REFSEL_M 0x3 /* Voltage Reference Select Mask */ 70 #define CFG_REFSEL_S 11 /* Voltage Reference Select Shift */ 71 #define CFG_ADHSC (1 << 10) /* High Speed Configuration */ 72 #define CFG_ADSTS_M 0x3 /* Defines the sample time duration */ 73 #define CFG_ADSTS_S 8 /* Defines the sample time duration */ 74 #define CFG_ADLPC (1 << 7) /* Low-Power Configuration */ 75 #define CFG_ADIV_M 0x3 /* Clock Divide Select */ 76 #define CFG_ADIV_S 5 /* Clock Divide Select */ 77 #define CFG_ADLSMP (1 << 4) /* Long Sample Time Configuration */ 78 #define CFG_MODE_M 0x3 /* Conversion Mode Selection Mask */ 79 #define CFG_MODE_S 2 /* Conversion Mode Selection Shift */ 80 #define CFG_MODE_12 0x2 /* 12-bit mode */ 81 #define CFG_ADICLK_M 0x3 /* Input Clock Select Mask */ 82 #define CFG_ADICLK_S 0 /* Input Clock Select Shift */ 83 #define ADC_GC 0x18 /* General control register */ 84 #define GC_CAL (1 << 7) /* Calibration */ 85 #define GC_ADCO (1 << 6) /* Continuous Conversion Enable */ 86 #define GC_AVGE (1 << 5) /* Hardware average enable */ 87 #define GC_ACFE (1 << 4) /* Compare Function Enable */ 88 #define GC_ACFGT (1 << 3) /* Compare Function Greater Than En */ 89 #define GC_ACREN (1 << 2) /* Compare Function Range En */ 90 #define GC_DMAEN (1 << 1) /* DMA Enable */ 91 #define GC_ADACKEN (1 << 0) /* Asynchronous clock output enable */ 92 #define ADC_GS 0x1C /* General status register */ 93 #define GS_AWKST (1 << 2) /* Asynchronous wakeup int status */ 94 #define GS_CALF (1 << 1) /* Calibration Failed Flag */ 95 #define GS_ADACT (1 << 0) /* Conversion Active */ 96 #define ADC_CV 0x20 /* Compare value register */ 97 #define CV_CV2_M 0xfff /* Compare Value 2 Mask */ 98 #define CV_CV2_S 16 /* Compare Value 2 Shift */ 99 #define CV_CV1_M 0xfff /* Compare Value 1 Mask */ 100 #define CV_CV1_S 0 /* Compare Value 1 Shift */ 101 #define ADC_OFS 0x24 /* Offset correction value register */ 102 #define OFS_SIGN 12 /* Sign bit */ 103 #define OFS_M 0xfff /* Offset value Mask */ 104 #define OFS_S 0 /* Offset value Shift */ 105 #define ADC_CAL 0x28 /* Calibration value register */ 106 #define CAL_CODE_M 0xf /* Calibration Result Value Mask */ 107 #define CAL_CODE_S 0 /* Calibration Result Value Shift */ 108 #define ADC_PCTL 0x30 /* Pin control register */ 109 110 struct adc_softc { 111 struct resource *res[2]; 112 bus_space_tag_t bst; 113 bus_space_handle_t bsh; 114 void *ih; 115 }; 116 117 struct adc_softc *adc_sc; 118 119 static struct resource_spec adc_spec[] = { 120 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 121 { SYS_RES_IRQ, 0, RF_ACTIVE }, 122 { -1, 0 } 123 }; 124 125 static int 126 adc_probe(device_t dev) 127 { 128 129 if (!ofw_bus_status_okay(dev)) 130 return (ENXIO); 131 132 if (!ofw_bus_is_compatible(dev, "fsl,mvf600-adc")) 133 return (ENXIO); 134 135 device_set_desc(dev, "Vybrid Family " 136 "12-bit Analog to Digital Converter"); 137 return (BUS_PROBE_DEFAULT); 138 } 139 140 static void 141 adc_intr(void *arg) 142 { 143 144 /* Conversation complete */ 145 } 146 147 uint32_t 148 adc_read(void) 149 { 150 struct adc_softc *sc; 151 152 sc = adc_sc; 153 if (sc == NULL) 154 return (0); 155 156 return (READ4(sc, ADC_R0)); 157 } 158 159 uint32_t 160 adc_enable(int channel) 161 { 162 struct adc_softc *sc; 163 int reg; 164 165 sc = adc_sc; 166 if (sc == NULL) 167 return (1); 168 169 reg = READ4(sc, ADC_HC0); 170 reg &= ~(HC_ADCH_M << HC_ADCH_S); 171 reg |= (channel << HC_ADCH_S); 172 WRITE4(sc, ADC_HC0, reg); 173 174 return (0); 175 } 176 177 static int 178 adc_attach(device_t dev) 179 { 180 struct adc_softc *sc; 181 int err; 182 int reg; 183 184 sc = device_get_softc(dev); 185 186 if (bus_alloc_resources(dev, adc_spec, sc->res)) { 187 device_printf(dev, "could not allocate resources\n"); 188 return (ENXIO); 189 } 190 191 /* Memory interface */ 192 sc->bst = rman_get_bustag(sc->res[0]); 193 sc->bsh = rman_get_bushandle(sc->res[0]); 194 195 adc_sc = sc; 196 197 /* Setup interrupt handler */ 198 err = bus_setup_intr(dev, sc->res[1], INTR_TYPE_BIO | INTR_MPSAFE, 199 NULL, adc_intr, sc, &sc->ih); 200 if (err) { 201 device_printf(dev, "Unable to alloc interrupt resource.\n"); 202 return (ENXIO); 203 } 204 205 /* Configure 12-bit mode */ 206 reg = READ4(sc, ADC_CFG); 207 reg &= ~(CFG_MODE_M << CFG_MODE_S); 208 reg |= (CFG_MODE_12 << CFG_MODE_S); /* 12bit */ 209 WRITE4(sc, ADC_CFG, reg); 210 211 /* Configure for continuous conversion */ 212 reg = READ4(sc, ADC_GC); 213 reg |= (GC_ADCO | GC_AVGE); 214 WRITE4(sc, ADC_GC, reg); 215 216 /* Disable interrupts */ 217 reg = READ4(sc, ADC_HC0); 218 reg &= HC_AIEN; 219 WRITE4(sc, ADC_HC0, reg); 220 221 return (0); 222 } 223 224 static device_method_t adc_methods[] = { 225 DEVMETHOD(device_probe, adc_probe), 226 DEVMETHOD(device_attach, adc_attach), 227 { 0, 0 } 228 }; 229 230 static driver_t adc_driver = { 231 "adc", 232 adc_methods, 233 sizeof(struct adc_softc), 234 }; 235 236 DRIVER_MODULE(adc, simplebus, adc_driver, 0, 0); 237