xref: /freebsd/sys/arm/freescale/vybrid/vf_anadig.c (revision 4d846d26)
15c263f43SRuslan Bukin /*-
24d846d26SWarner Losh  * SPDX-License-Identifier: BSD-2-Clause
3af3dc4a7SPedro F. Giffuni  *
4896fc918SRuslan Bukin  * Copyright (c) 2013-2014 Ruslan Bukin <br@bsdpad.com>
55c263f43SRuslan Bukin  * All rights reserved.
65c263f43SRuslan Bukin  *
75c263f43SRuslan Bukin  * Redistribution and use in source and binary forms, with or without
85c263f43SRuslan Bukin  * modification, are permitted provided that the following conditions
95c263f43SRuslan Bukin  * are met:
105c263f43SRuslan Bukin  * 1. Redistributions of source code must retain the above copyright
115c263f43SRuslan Bukin  *    notice, this list of conditions and the following disclaimer.
125c263f43SRuslan Bukin  * 2. Redistributions in binary form must reproduce the above copyright
135c263f43SRuslan Bukin  *    notice, this list of conditions and the following disclaimer in the
145c263f43SRuslan Bukin  *    documentation and/or other materials provided with the distribution.
155c263f43SRuslan Bukin  *
165c263f43SRuslan Bukin  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
175c263f43SRuslan Bukin  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
185c263f43SRuslan Bukin  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
195c263f43SRuslan Bukin  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
205c263f43SRuslan Bukin  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
215c263f43SRuslan Bukin  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
225c263f43SRuslan Bukin  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
235c263f43SRuslan Bukin  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
245c263f43SRuslan Bukin  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
255c263f43SRuslan Bukin  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
265c263f43SRuslan Bukin  * SUCH DAMAGE.
275c263f43SRuslan Bukin  */
285c263f43SRuslan Bukin 
295c263f43SRuslan Bukin /*
305c263f43SRuslan Bukin  * Vybrid Family Analog components control digital interface (ANADIG)
315c263f43SRuslan Bukin  * Chapter 11, Vybrid Reference Manual, Rev. 5, 07/2013
325c263f43SRuslan Bukin  */
335c263f43SRuslan Bukin 
345c263f43SRuslan Bukin #include <sys/cdefs.h>
355c263f43SRuslan Bukin __FBSDID("$FreeBSD$");
365c263f43SRuslan Bukin 
375c263f43SRuslan Bukin #include <sys/param.h>
385c263f43SRuslan Bukin #include <sys/systm.h>
395c263f43SRuslan Bukin #include <sys/bus.h>
405c263f43SRuslan Bukin #include <sys/kernel.h>
415c263f43SRuslan Bukin #include <sys/module.h>
425c263f43SRuslan Bukin #include <sys/malloc.h>
435c263f43SRuslan Bukin #include <sys/rman.h>
445c263f43SRuslan Bukin #include <sys/timeet.h>
455c263f43SRuslan Bukin #include <sys/timetc.h>
465c263f43SRuslan Bukin #include <sys/watchdog.h>
475c263f43SRuslan Bukin 
485c263f43SRuslan Bukin #include <dev/ofw/openfirm.h>
495c263f43SRuslan Bukin #include <dev/ofw/ofw_bus.h>
505c263f43SRuslan Bukin #include <dev/ofw/ofw_bus_subr.h>
515c263f43SRuslan Bukin 
525c263f43SRuslan Bukin #include <machine/bus.h>
535c263f43SRuslan Bukin #include <machine/cpu.h>
545c263f43SRuslan Bukin #include <machine/intr.h>
555c263f43SRuslan Bukin 
565c263f43SRuslan Bukin #include <arm/freescale/vybrid/vf_common.h>
575c263f43SRuslan Bukin 
585c263f43SRuslan Bukin #define	ANADIG_PLL3_CTRL	0x010	/* PLL3 Control */
595c263f43SRuslan Bukin #define	ANADIG_PLL7_CTRL	0x020	/* PLL7 Control */
605c263f43SRuslan Bukin #define	ANADIG_PLL2_CTRL	0x030	/* PLL2 Control */
615c263f43SRuslan Bukin #define	ANADIG_PLL2_SS		0x040	/* PLL2 Spread Spectrum */
625c263f43SRuslan Bukin #define	ANADIG_PLL2_NUM		0x050	/* PLL2 Numerator */
635c263f43SRuslan Bukin #define	ANADIG_PLL2_DENOM	0x060	/* PLL2 Denominator */
645c263f43SRuslan Bukin #define	ANADIG_PLL4_CTRL	0x070	/* PLL4 Control */
655c263f43SRuslan Bukin #define	ANADIG_PLL4_NUM		0x080	/* PLL4 Numerator */
665c263f43SRuslan Bukin #define	ANADIG_PLL4_DENOM	0x090	/* PLL4 Denominator */
675c263f43SRuslan Bukin #define	ANADIG_PLL6_CTRL	0x0A0	/* PLL6 Control */
685c263f43SRuslan Bukin #define	ANADIG_PLL6_NUM		0x0B0	/* PLL6 Numerator */
695c263f43SRuslan Bukin #define	ANADIG_PLL6_DENOM	0x0C0	/* PLL6 Denominator */
705c263f43SRuslan Bukin #define	ANADIG_PLL5_CTRL	0x0E0	/* PLL5 Control */
715c263f43SRuslan Bukin #define	ANADIG_PLL3_PFD		0x0F0	/* PLL3 PFD */
725c263f43SRuslan Bukin #define	ANADIG_PLL2_PFD		0x100	/* PLL2 PFD */
735c263f43SRuslan Bukin #define	ANADIG_REG_1P1		0x110	/* Regulator 1P1 */
745c263f43SRuslan Bukin #define	ANADIG_REG_3P0		0x120	/* Regulator 3P0 */
755c263f43SRuslan Bukin #define	ANADIG_REG_2P5		0x130	/* Regulator 2P5 */
765c263f43SRuslan Bukin #define	ANADIG_ANA_MISC0	0x150	/* Analog Miscellaneous */
775c263f43SRuslan Bukin #define	ANADIG_ANA_MISC1	0x160	/* Analog Miscellaneous */
785c263f43SRuslan Bukin #define	ANADIG_ANADIG_DIGPROG	0x260	/* Digital Program */
795c263f43SRuslan Bukin #define	ANADIG_PLL1_CTRL	0x270	/* PLL1 Control */
805c263f43SRuslan Bukin #define	ANADIG_PLL1_SS		0x280	/* PLL1 Spread Spectrum */
815c263f43SRuslan Bukin #define	ANADIG_PLL1_NUM		0x290	/* PLL1 Numerator */
825c263f43SRuslan Bukin #define	ANADIG_PLL1_DENOM	0x2A0	/* PLL1 Denominator */
835c263f43SRuslan Bukin #define	ANADIG_PLL1_PFD		0x2B0	/* PLL1_PFD */
845c263f43SRuslan Bukin #define	ANADIG_PLL_LOCK		0x2C0	/* PLL Lock */
855c263f43SRuslan Bukin 
865c263f43SRuslan Bukin #define	USB_VBUS_DETECT(n)		(0x1A0 + 0x60 * n)
875c263f43SRuslan Bukin #define	USB_CHRG_DETECT(n)		(0x1B0 + 0x60 * n)
885c263f43SRuslan Bukin #define	USB_VBUS_DETECT_STATUS(n)	(0x1C0 + 0x60 * n)
895c263f43SRuslan Bukin #define	USB_CHRG_DETECT_STATUS(n)	(0x1D0 + 0x60 * n)
905c263f43SRuslan Bukin #define	USB_LOOPBACK(n)			(0x1E0 + 0x60 * n)
915c263f43SRuslan Bukin #define	USB_MISC(n)			(0x1F0 + 0x60 * n)
925c263f43SRuslan Bukin 
937a22215cSEitan Adler #define	ANADIG_PLL_LOCKED	(1U << 31)
945c263f43SRuslan Bukin #define	ENABLE_LINREG		(1 << 0)
955c263f43SRuslan Bukin #define	EN_CLK_TO_UTMI		(1 << 30)
965c263f43SRuslan Bukin 
975c263f43SRuslan Bukin #define	CTRL_BYPASS		(1 << 16)
985c263f43SRuslan Bukin #define	CTRL_PWR		(1 << 12)
995c263f43SRuslan Bukin #define	CTRL_PLL_EN		(1 << 13)
1005c263f43SRuslan Bukin #define	EN_USB_CLKS		(1 << 6)
1015c263f43SRuslan Bukin 
102896fc918SRuslan Bukin #define	PLL4_CTRL_DIV_SEL_S	0
103896fc918SRuslan Bukin #define	PLL4_CTRL_DIV_SEL_M	0x7f
104896fc918SRuslan Bukin 
1055c263f43SRuslan Bukin struct anadig_softc {
1065c263f43SRuslan Bukin 	struct resource		*res[1];
1075c263f43SRuslan Bukin 	bus_space_tag_t		bst;
1085c263f43SRuslan Bukin 	bus_space_handle_t	bsh;
1095c263f43SRuslan Bukin };
1105c263f43SRuslan Bukin 
111896fc918SRuslan Bukin struct anadig_softc *anadig_sc;
112896fc918SRuslan Bukin 
1135c263f43SRuslan Bukin static struct resource_spec anadig_spec[] = {
1145c263f43SRuslan Bukin 	{ SYS_RES_MEMORY,	0,	RF_ACTIVE },
1155c263f43SRuslan Bukin 	{ -1, 0 }
1165c263f43SRuslan Bukin };
1175c263f43SRuslan Bukin 
1185c263f43SRuslan Bukin static int
1195c263f43SRuslan Bukin anadig_probe(device_t dev)
1205c263f43SRuslan Bukin {
1215c263f43SRuslan Bukin 
122add35ed5SIan Lepore 	if (!ofw_bus_status_okay(dev))
123add35ed5SIan Lepore 		return (ENXIO);
124add35ed5SIan Lepore 
1255c263f43SRuslan Bukin 	if (!ofw_bus_is_compatible(dev, "fsl,mvf600-anadig"))
1265c263f43SRuslan Bukin 		return (ENXIO);
1275c263f43SRuslan Bukin 
1285c263f43SRuslan Bukin 	device_set_desc(dev, "Vybrid Family ANADIG Unit");
1295c263f43SRuslan Bukin 	return (BUS_PROBE_DEFAULT);
1305c263f43SRuslan Bukin }
1315c263f43SRuslan Bukin 
1325c263f43SRuslan Bukin static int
1335c263f43SRuslan Bukin enable_pll(struct anadig_softc *sc, int pll_ctrl)
1345c263f43SRuslan Bukin {
1355c263f43SRuslan Bukin 	int reg;
1365c263f43SRuslan Bukin 
1375c263f43SRuslan Bukin 	reg = READ4(sc, pll_ctrl);
1385c263f43SRuslan Bukin 	reg &= ~(CTRL_BYPASS | CTRL_PWR);
1395c263f43SRuslan Bukin 	if (pll_ctrl == ANADIG_PLL3_CTRL || pll_ctrl == ANADIG_PLL7_CTRL) {
1405c263f43SRuslan Bukin 		/* It is USB PLL. Power bit logic is reversed */
1415c263f43SRuslan Bukin 		reg |= (CTRL_PWR | EN_USB_CLKS);
1425c263f43SRuslan Bukin 	}
1435c263f43SRuslan Bukin 	WRITE4(sc, pll_ctrl, reg);
1445c263f43SRuslan Bukin 
1455c263f43SRuslan Bukin 	/* Wait for PLL lock */
1465c263f43SRuslan Bukin 	while (!(READ4(sc, pll_ctrl) & ANADIG_PLL_LOCKED))
1475c263f43SRuslan Bukin 		;
1485c263f43SRuslan Bukin 
1495c263f43SRuslan Bukin 	reg = READ4(sc, pll_ctrl);
1505c263f43SRuslan Bukin 	reg |= (CTRL_PLL_EN);
1515c263f43SRuslan Bukin 	WRITE4(sc, pll_ctrl, reg);
1525c263f43SRuslan Bukin 
1535c263f43SRuslan Bukin 	return (0);
1545c263f43SRuslan Bukin }
1555c263f43SRuslan Bukin 
156896fc918SRuslan Bukin uint32_t
157896fc918SRuslan Bukin pll4_configure_output(uint32_t mfi, uint32_t mfn, uint32_t mfd)
158896fc918SRuslan Bukin {
159896fc918SRuslan Bukin 	struct anadig_softc *sc;
160896fc918SRuslan Bukin 	int reg;
161896fc918SRuslan Bukin 
162896fc918SRuslan Bukin 	sc = anadig_sc;
163896fc918SRuslan Bukin 
164896fc918SRuslan Bukin 	/*
165896fc918SRuslan Bukin 	 * PLLout = Fsys * (MFI+(MFN/MFD))
166896fc918SRuslan Bukin 	 */
167896fc918SRuslan Bukin 
168896fc918SRuslan Bukin 	reg = READ4(sc, ANADIG_PLL4_CTRL);
169896fc918SRuslan Bukin 	reg &= ~(PLL4_CTRL_DIV_SEL_M << PLL4_CTRL_DIV_SEL_S);
170896fc918SRuslan Bukin 	reg |= (mfi << PLL4_CTRL_DIV_SEL_S);
171896fc918SRuslan Bukin 	WRITE4(sc, ANADIG_PLL4_CTRL, reg);
172896fc918SRuslan Bukin 	WRITE4(sc, ANADIG_PLL4_NUM, mfn);
173896fc918SRuslan Bukin 	WRITE4(sc, ANADIG_PLL4_DENOM, mfd);
174896fc918SRuslan Bukin 
175896fc918SRuslan Bukin 	return (0);
176896fc918SRuslan Bukin }
177896fc918SRuslan Bukin 
1785c263f43SRuslan Bukin static int
1795c263f43SRuslan Bukin anadig_attach(device_t dev)
1805c263f43SRuslan Bukin {
1815c263f43SRuslan Bukin 	struct anadig_softc *sc;
1825c263f43SRuslan Bukin 	int reg;
1835c263f43SRuslan Bukin 
1845c263f43SRuslan Bukin 	sc = device_get_softc(dev);
1855c263f43SRuslan Bukin 
1865c263f43SRuslan Bukin 	if (bus_alloc_resources(dev, anadig_spec, sc->res)) {
1875c263f43SRuslan Bukin 		device_printf(dev, "could not allocate resources\n");
1885c263f43SRuslan Bukin 		return (ENXIO);
1895c263f43SRuslan Bukin 	}
1905c263f43SRuslan Bukin 
1915c263f43SRuslan Bukin 	/* Memory interface */
1925c263f43SRuslan Bukin 	sc->bst = rman_get_bustag(sc->res[0]);
1935c263f43SRuslan Bukin 	sc->bsh = rman_get_bushandle(sc->res[0]);
1945c263f43SRuslan Bukin 
195896fc918SRuslan Bukin 	anadig_sc = sc;
196896fc918SRuslan Bukin 
1975c263f43SRuslan Bukin 	/* Enable USB PLLs */
1985c263f43SRuslan Bukin 	enable_pll(sc, ANADIG_PLL3_CTRL);
1995c263f43SRuslan Bukin 	enable_pll(sc, ANADIG_PLL7_CTRL);
2005c263f43SRuslan Bukin 
201896fc918SRuslan Bukin 	/* Enable other PLLs */
2025c263f43SRuslan Bukin 	enable_pll(sc, ANADIG_PLL1_CTRL);
2035c263f43SRuslan Bukin 	enable_pll(sc, ANADIG_PLL2_CTRL);
2045c263f43SRuslan Bukin 	enable_pll(sc, ANADIG_PLL4_CTRL);
2055c263f43SRuslan Bukin 	enable_pll(sc, ANADIG_PLL5_CTRL);
2065c263f43SRuslan Bukin 	enable_pll(sc, ANADIG_PLL6_CTRL);
2075c263f43SRuslan Bukin 
2085c263f43SRuslan Bukin 	/* Enable USB voltage regulator */
2095c263f43SRuslan Bukin 	reg = READ4(sc, ANADIG_REG_3P0);
2105c263f43SRuslan Bukin 	reg |= (ENABLE_LINREG);
2115c263f43SRuslan Bukin 	WRITE4(sc, ANADIG_REG_3P0, reg);
2125c263f43SRuslan Bukin 
2135c263f43SRuslan Bukin 	/* Give clocks to USB */
2145c263f43SRuslan Bukin 	reg = READ4(sc, USB_MISC(0));
2155c263f43SRuslan Bukin 	reg |= (EN_CLK_TO_UTMI);
2165c263f43SRuslan Bukin 	WRITE4(sc, USB_MISC(0), reg);
2175c263f43SRuslan Bukin 
2185c263f43SRuslan Bukin 	reg = READ4(sc, USB_MISC(1));
2195c263f43SRuslan Bukin 	reg |= (EN_CLK_TO_UTMI);
2205c263f43SRuslan Bukin 	WRITE4(sc, USB_MISC(1), reg);
2215c263f43SRuslan Bukin 
2225c263f43SRuslan Bukin #if 0
2235c263f43SRuslan Bukin 	printf("USB_ANALOG_USB_MISC(0) == 0x%08x\n",
2245c263f43SRuslan Bukin 	    READ4(sc, USB_ANALOG_USB_MISC(0)));
2255c263f43SRuslan Bukin 	printf("USB_ANALOG_USB_MISC(1) == 0x%08x\n",
2265c263f43SRuslan Bukin 	    READ4(sc, USB_ANALOG_USB_MISC(1)));
2275c263f43SRuslan Bukin #endif
2285c263f43SRuslan Bukin 
2295c263f43SRuslan Bukin 	return (0);
2305c263f43SRuslan Bukin }
2315c263f43SRuslan Bukin 
2325c263f43SRuslan Bukin static device_method_t anadig_methods[] = {
2335c263f43SRuslan Bukin 	DEVMETHOD(device_probe,		anadig_probe),
2345c263f43SRuslan Bukin 	DEVMETHOD(device_attach,	anadig_attach),
2355c263f43SRuslan Bukin 	{ 0, 0 }
2365c263f43SRuslan Bukin };
2375c263f43SRuslan Bukin 
2385c263f43SRuslan Bukin static driver_t anadig_driver = {
2395c263f43SRuslan Bukin 	"anadig",
2405c263f43SRuslan Bukin 	anadig_methods,
2415c263f43SRuslan Bukin 	sizeof(struct anadig_softc),
2425c263f43SRuslan Bukin };
2435c263f43SRuslan Bukin 
244ea538dabSJohn Baldwin DRIVER_MODULE(anadig, simplebus, anadig_driver, 0, 0);
245