1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2013-2014 Ruslan Bukin <br@bsdpad.com> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* 30 * Vybrid Family Analog components control digital interface (ANADIG) 31 * Chapter 11, Vybrid Reference Manual, Rev. 5, 07/2013 32 */ 33 34 #include <sys/cdefs.h> 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/bus.h> 38 #include <sys/kernel.h> 39 #include <sys/module.h> 40 #include <sys/malloc.h> 41 #include <sys/rman.h> 42 #include <sys/timeet.h> 43 #include <sys/timetc.h> 44 #include <sys/watchdog.h> 45 46 #include <dev/ofw/openfirm.h> 47 #include <dev/ofw/ofw_bus.h> 48 #include <dev/ofw/ofw_bus_subr.h> 49 50 #include <machine/bus.h> 51 #include <machine/cpu.h> 52 #include <machine/intr.h> 53 54 #include <arm/freescale/vybrid/vf_common.h> 55 56 #define ANADIG_PLL3_CTRL 0x010 /* PLL3 Control */ 57 #define ANADIG_PLL7_CTRL 0x020 /* PLL7 Control */ 58 #define ANADIG_PLL2_CTRL 0x030 /* PLL2 Control */ 59 #define ANADIG_PLL2_SS 0x040 /* PLL2 Spread Spectrum */ 60 #define ANADIG_PLL2_NUM 0x050 /* PLL2 Numerator */ 61 #define ANADIG_PLL2_DENOM 0x060 /* PLL2 Denominator */ 62 #define ANADIG_PLL4_CTRL 0x070 /* PLL4 Control */ 63 #define ANADIG_PLL4_NUM 0x080 /* PLL4 Numerator */ 64 #define ANADIG_PLL4_DENOM 0x090 /* PLL4 Denominator */ 65 #define ANADIG_PLL6_CTRL 0x0A0 /* PLL6 Control */ 66 #define ANADIG_PLL6_NUM 0x0B0 /* PLL6 Numerator */ 67 #define ANADIG_PLL6_DENOM 0x0C0 /* PLL6 Denominator */ 68 #define ANADIG_PLL5_CTRL 0x0E0 /* PLL5 Control */ 69 #define ANADIG_PLL3_PFD 0x0F0 /* PLL3 PFD */ 70 #define ANADIG_PLL2_PFD 0x100 /* PLL2 PFD */ 71 #define ANADIG_REG_1P1 0x110 /* Regulator 1P1 */ 72 #define ANADIG_REG_3P0 0x120 /* Regulator 3P0 */ 73 #define ANADIG_REG_2P5 0x130 /* Regulator 2P5 */ 74 #define ANADIG_ANA_MISC0 0x150 /* Analog Miscellaneous */ 75 #define ANADIG_ANA_MISC1 0x160 /* Analog Miscellaneous */ 76 #define ANADIG_ANADIG_DIGPROG 0x260 /* Digital Program */ 77 #define ANADIG_PLL1_CTRL 0x270 /* PLL1 Control */ 78 #define ANADIG_PLL1_SS 0x280 /* PLL1 Spread Spectrum */ 79 #define ANADIG_PLL1_NUM 0x290 /* PLL1 Numerator */ 80 #define ANADIG_PLL1_DENOM 0x2A0 /* PLL1 Denominator */ 81 #define ANADIG_PLL1_PFD 0x2B0 /* PLL1_PFD */ 82 #define ANADIG_PLL_LOCK 0x2C0 /* PLL Lock */ 83 84 #define USB_VBUS_DETECT(n) (0x1A0 + 0x60 * n) 85 #define USB_CHRG_DETECT(n) (0x1B0 + 0x60 * n) 86 #define USB_VBUS_DETECT_STATUS(n) (0x1C0 + 0x60 * n) 87 #define USB_CHRG_DETECT_STATUS(n) (0x1D0 + 0x60 * n) 88 #define USB_LOOPBACK(n) (0x1E0 + 0x60 * n) 89 #define USB_MISC(n) (0x1F0 + 0x60 * n) 90 91 #define ANADIG_PLL_LOCKED (1U << 31) 92 #define ENABLE_LINREG (1 << 0) 93 #define EN_CLK_TO_UTMI (1 << 30) 94 95 #define CTRL_BYPASS (1 << 16) 96 #define CTRL_PWR (1 << 12) 97 #define CTRL_PLL_EN (1 << 13) 98 #define EN_USB_CLKS (1 << 6) 99 100 #define PLL4_CTRL_DIV_SEL_S 0 101 #define PLL4_CTRL_DIV_SEL_M 0x7f 102 103 struct anadig_softc { 104 struct resource *res[1]; 105 bus_space_tag_t bst; 106 bus_space_handle_t bsh; 107 }; 108 109 struct anadig_softc *anadig_sc; 110 111 static struct resource_spec anadig_spec[] = { 112 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 113 { -1, 0 } 114 }; 115 116 static int 117 anadig_probe(device_t dev) 118 { 119 120 if (!ofw_bus_status_okay(dev)) 121 return (ENXIO); 122 123 if (!ofw_bus_is_compatible(dev, "fsl,mvf600-anadig")) 124 return (ENXIO); 125 126 device_set_desc(dev, "Vybrid Family ANADIG Unit"); 127 return (BUS_PROBE_DEFAULT); 128 } 129 130 static int 131 enable_pll(struct anadig_softc *sc, int pll_ctrl) 132 { 133 int reg; 134 135 reg = READ4(sc, pll_ctrl); 136 reg &= ~(CTRL_BYPASS | CTRL_PWR); 137 if (pll_ctrl == ANADIG_PLL3_CTRL || pll_ctrl == ANADIG_PLL7_CTRL) { 138 /* It is USB PLL. Power bit logic is reversed */ 139 reg |= (CTRL_PWR | EN_USB_CLKS); 140 } 141 WRITE4(sc, pll_ctrl, reg); 142 143 /* Wait for PLL lock */ 144 while (!(READ4(sc, pll_ctrl) & ANADIG_PLL_LOCKED)) 145 ; 146 147 reg = READ4(sc, pll_ctrl); 148 reg |= (CTRL_PLL_EN); 149 WRITE4(sc, pll_ctrl, reg); 150 151 return (0); 152 } 153 154 uint32_t 155 pll4_configure_output(uint32_t mfi, uint32_t mfn, uint32_t mfd) 156 { 157 struct anadig_softc *sc; 158 int reg; 159 160 sc = anadig_sc; 161 162 /* 163 * PLLout = Fsys * (MFI+(MFN/MFD)) 164 */ 165 166 reg = READ4(sc, ANADIG_PLL4_CTRL); 167 reg &= ~(PLL4_CTRL_DIV_SEL_M << PLL4_CTRL_DIV_SEL_S); 168 reg |= (mfi << PLL4_CTRL_DIV_SEL_S); 169 WRITE4(sc, ANADIG_PLL4_CTRL, reg); 170 WRITE4(sc, ANADIG_PLL4_NUM, mfn); 171 WRITE4(sc, ANADIG_PLL4_DENOM, mfd); 172 173 return (0); 174 } 175 176 static int 177 anadig_attach(device_t dev) 178 { 179 struct anadig_softc *sc; 180 int reg; 181 182 sc = device_get_softc(dev); 183 184 if (bus_alloc_resources(dev, anadig_spec, sc->res)) { 185 device_printf(dev, "could not allocate resources\n"); 186 return (ENXIO); 187 } 188 189 /* Memory interface */ 190 sc->bst = rman_get_bustag(sc->res[0]); 191 sc->bsh = rman_get_bushandle(sc->res[0]); 192 193 anadig_sc = sc; 194 195 /* Enable USB PLLs */ 196 enable_pll(sc, ANADIG_PLL3_CTRL); 197 enable_pll(sc, ANADIG_PLL7_CTRL); 198 199 /* Enable other PLLs */ 200 enable_pll(sc, ANADIG_PLL1_CTRL); 201 enable_pll(sc, ANADIG_PLL2_CTRL); 202 enable_pll(sc, ANADIG_PLL4_CTRL); 203 enable_pll(sc, ANADIG_PLL5_CTRL); 204 enable_pll(sc, ANADIG_PLL6_CTRL); 205 206 /* Enable USB voltage regulator */ 207 reg = READ4(sc, ANADIG_REG_3P0); 208 reg |= (ENABLE_LINREG); 209 WRITE4(sc, ANADIG_REG_3P0, reg); 210 211 /* Give clocks to USB */ 212 reg = READ4(sc, USB_MISC(0)); 213 reg |= (EN_CLK_TO_UTMI); 214 WRITE4(sc, USB_MISC(0), reg); 215 216 reg = READ4(sc, USB_MISC(1)); 217 reg |= (EN_CLK_TO_UTMI); 218 WRITE4(sc, USB_MISC(1), reg); 219 220 #if 0 221 printf("USB_ANALOG_USB_MISC(0) == 0x%08x\n", 222 READ4(sc, USB_ANALOG_USB_MISC(0))); 223 printf("USB_ANALOG_USB_MISC(1) == 0x%08x\n", 224 READ4(sc, USB_ANALOG_USB_MISC(1))); 225 #endif 226 227 return (0); 228 } 229 230 static device_method_t anadig_methods[] = { 231 DEVMETHOD(device_probe, anadig_probe), 232 DEVMETHOD(device_attach, anadig_attach), 233 { 0, 0 } 234 }; 235 236 static driver_t anadig_driver = { 237 "anadig", 238 anadig_methods, 239 sizeof(struct anadig_softc), 240 }; 241 242 DRIVER_MODULE(anadig, simplebus, anadig_driver, 0, 0); 243