1 /* $NetBSD: armreg.h,v 1.37 2007/01/06 00:50:54 christos Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 2001 Ben Harris 5 * Copyright (c) 1994-1996 Mark Brinicombe. 6 * Copyright (c) 1994 Brini. 7 * All rights reserved. 8 * 9 * This code is derived from software written for Brini by Mark Brinicombe 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by Brini. 22 * 4. The name of the company nor the name of the author may be used to 23 * endorse or promote products derived from this software without specific 24 * prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED 27 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 28 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 29 * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 30 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 31 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 32 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 36 * SUCH DAMAGE. 37 * 38 * $FreeBSD$ 39 */ 40 41 #ifndef MACHINE_ARMREG_H 42 #define MACHINE_ARMREG_H 43 44 #define INSN_SIZE 4 45 #define INSN_COND_MASK 0xf0000000 /* Condition mask */ 46 #define PSR_MODE 0x0000001f /* mode mask */ 47 #define PSR_USR26_MODE 0x00000000 48 #define PSR_FIQ26_MODE 0x00000001 49 #define PSR_IRQ26_MODE 0x00000002 50 #define PSR_SVC26_MODE 0x00000003 51 #define PSR_USR32_MODE 0x00000010 52 #define PSR_FIQ32_MODE 0x00000011 53 #define PSR_IRQ32_MODE 0x00000012 54 #define PSR_SVC32_MODE 0x00000013 55 #define PSR_ABT32_MODE 0x00000017 56 #define PSR_UND32_MODE 0x0000001b 57 #define PSR_SYS32_MODE 0x0000001f 58 #define PSR_32_MODE 0x00000010 59 #define PSR_FLAGS 0xf0000000 /* flags */ 60 61 #define PSR_C_bit (1 << 29) /* carry */ 62 63 /* The high-order byte is always the implementor */ 64 #define CPU_ID_IMPLEMENTOR_MASK 0xff000000 65 #define CPU_ID_ARM_LTD 0x41000000 /* 'A' */ 66 #define CPU_ID_DEC 0x44000000 /* 'D' */ 67 #define CPU_ID_INTEL 0x69000000 /* 'i' */ 68 #define CPU_ID_TI 0x54000000 /* 'T' */ 69 #define CPU_ID_FARADAY 0x66000000 /* 'f' */ 70 71 /* How to decide what format the CPUID is in. */ 72 #define CPU_ID_ISOLD(x) (((x) & 0x0000f000) == 0x00000000) 73 #define CPU_ID_IS7(x) (((x) & 0x0000f000) == 0x00007000) 74 #define CPU_ID_ISNEW(x) (!CPU_ID_ISOLD(x) && !CPU_ID_IS7(x)) 75 76 /* On ARM3 and ARM6, this byte holds the foundry ID. */ 77 #define CPU_ID_FOUNDRY_MASK 0x00ff0000 78 #define CPU_ID_FOUNDRY_VLSI 0x00560000 79 80 /* On ARM7 it holds the architecture and variant (sub-model) */ 81 #define CPU_ID_7ARCH_MASK 0x00800000 82 #define CPU_ID_7ARCH_V3 0x00000000 83 #define CPU_ID_7ARCH_V4T 0x00800000 84 #define CPU_ID_7VARIANT_MASK 0x007f0000 85 86 /* On more recent ARMs, it does the same, but in a different format */ 87 #define CPU_ID_ARCH_MASK 0x000f0000 88 #define CPU_ID_ARCH_V3 0x00000000 89 #define CPU_ID_ARCH_V4 0x00010000 90 #define CPU_ID_ARCH_V4T 0x00020000 91 #define CPU_ID_ARCH_V5 0x00030000 92 #define CPU_ID_ARCH_V5T 0x00040000 93 #define CPU_ID_ARCH_V5TE 0x00050000 94 #define CPU_ID_ARCH_V5TEJ 0x00060000 95 #define CPU_ID_ARCH_V6 0x00070000 96 #define CPU_ID_CPUID_SCHEME 0x000f0000 97 #define CPU_ID_VARIANT_MASK 0x00f00000 98 99 /* Next three nybbles are part number */ 100 #define CPU_ID_PARTNO_MASK 0x0000fff0 101 102 /* Intel XScale has sub fields in part number */ 103 #define CPU_ID_XSCALE_COREGEN_MASK 0x0000e000 /* core generation */ 104 #define CPU_ID_XSCALE_COREREV_MASK 0x00001c00 /* core revision */ 105 #define CPU_ID_XSCALE_PRODUCT_MASK 0x000003f0 /* product number */ 106 107 /* And finally, the revision number. */ 108 #define CPU_ID_REVISION_MASK 0x0000000f 109 110 /* Individual CPUs are probably best IDed by everything but the revision. */ 111 #define CPU_ID_CPU_MASK 0xfffffff0 112 113 /* Fake CPU IDs for ARMs without CP15 */ 114 #define CPU_ID_ARM2 0x41560200 115 #define CPU_ID_ARM250 0x41560250 116 117 /* Pre-ARM7 CPUs -- [15:12] == 0 */ 118 #define CPU_ID_ARM3 0x41560300 119 #define CPU_ID_ARM600 0x41560600 120 #define CPU_ID_ARM610 0x41560610 121 #define CPU_ID_ARM620 0x41560620 122 123 /* ARM7 CPUs -- [15:12] == 7 */ 124 #define CPU_ID_ARM700 0x41007000 /* XXX This is a guess. */ 125 #define CPU_ID_ARM710 0x41007100 126 #define CPU_ID_ARM7500 0x41027100 127 #define CPU_ID_ARM710A 0x41047100 /* inc ARM7100 */ 128 #define CPU_ID_ARM7500FE 0x41077100 129 #define CPU_ID_ARM710T 0x41807100 130 #define CPU_ID_ARM720T 0x41807200 131 #define CPU_ID_ARM740T8K 0x41807400 /* XXX no MMU, 8KB cache */ 132 #define CPU_ID_ARM740T4K 0x41817400 /* XXX no MMU, 4KB cache */ 133 134 /* Post-ARM7 CPUs */ 135 #define CPU_ID_ARM810 0x41018100 136 #define CPU_ID_ARM920T 0x41129200 137 #define CPU_ID_ARM920T_ALT 0x41009200 138 #define CPU_ID_ARM922T 0x41029220 139 #define CPU_ID_ARM926EJS 0x41069260 140 #define CPU_ID_ARM940T 0x41029400 /* XXX no MMU */ 141 #define CPU_ID_ARM946ES 0x41049460 /* XXX no MMU */ 142 #define CPU_ID_ARM966ES 0x41049660 /* XXX no MMU */ 143 #define CPU_ID_ARM966ESR1 0x41059660 /* XXX no MMU */ 144 #define CPU_ID_ARM1020E 0x4115a200 /* (AKA arm10 rev 1) */ 145 #define CPU_ID_ARM1022ES 0x4105a220 146 #define CPU_ID_ARM1026EJS 0x4106a260 147 #define CPU_ID_ARM1136JS 0x4107b360 148 #define CPU_ID_ARM1136JSR1 0x4117b360 149 #define CPU_ID_ARM1176JZS 0x410fb760 150 #define CPU_ID_CORTEXA8R1 0x411fc080 151 #define CPU_ID_CORTEXA8R2 0x412fc080 152 #define CPU_ID_CORTEXA8R3 0x413fc080 153 #define CPU_ID_CORTEXA9R1 0x411fc090 154 #define CPU_ID_CORTEXA9R2 0x412fc090 155 #define CPU_ID_CORTEXA9R3 0x413fc090 156 #define CPU_ID_CORTEXA15 0x410fc0f0 157 #define CPU_ID_SA110 0x4401a100 158 #define CPU_ID_SA1100 0x4401a110 159 #define CPU_ID_TI925T 0x54029250 160 #define CPU_ID_MV88FR131 0x56251310 /* Marvell Feroceon 88FR131 Core */ 161 #define CPU_ID_MV88FR331 0x56153310 /* Marvell Feroceon 88FR331 Core */ 162 #define CPU_ID_MV88FR571_VD 0x56155710 /* Marvell Feroceon 88FR571-VD Core (ID from datasheet) */ 163 164 /* 165 * LokiPlus core has also ID set to 0x41159260 and this define cause execution of unsupported 166 * L2-cache instructions so need to disable it. 0x41159260 is a generic ARM926E-S ID. 167 */ 168 #ifdef SOC_MV_LOKIPLUS 169 #define CPU_ID_MV88FR571_41 0x00000000 170 #else 171 #define CPU_ID_MV88FR571_41 0x41159260 /* Marvell Feroceon 88FR571-VD Core (actual ID from CPU reg) */ 172 #endif 173 174 #define CPU_ID_MV88SV581X_V6 0x560F5810 /* Marvell Sheeva 88SV581x v6 Core */ 175 #define CPU_ID_MV88SV581X_V7 0x561F5810 /* Marvell Sheeva 88SV581x v7 Core */ 176 #define CPU_ID_MV88SV584X_V6 0x561F5840 /* Marvell Sheeva 88SV584x v6 Core */ 177 #define CPU_ID_MV88SV584X_V7 0x562F5840 /* Marvell Sheeva 88SV584x v7 Core */ 178 /* Marvell's CPUIDs with ARM ID in implementor field */ 179 #define CPU_ID_ARM_88SV581X_V6 0x410fb760 /* Marvell Sheeva 88SV581x v6 Core */ 180 #define CPU_ID_ARM_88SV581X_V7 0x413FC080 /* Marvell Sheeva 88SV581x v7 Core */ 181 #define CPU_ID_ARM_88SV584X_V6 0x410FB020 /* Marvell Sheeva 88SV584x v6 Core */ 182 183 #define CPU_ID_FA526 0x66015260 184 #define CPU_ID_FA626TE 0x66056260 185 #define CPU_ID_SA1110 0x6901b110 186 #define CPU_ID_IXP1200 0x6901c120 187 #define CPU_ID_80200 0x69052000 188 #define CPU_ID_PXA250 0x69052100 /* sans core revision */ 189 #define CPU_ID_PXA210 0x69052120 190 #define CPU_ID_PXA250A 0x69052100 /* 1st version Core */ 191 #define CPU_ID_PXA210A 0x69052120 /* 1st version Core */ 192 #define CPU_ID_PXA250B 0x69052900 /* 3rd version Core */ 193 #define CPU_ID_PXA210B 0x69052920 /* 3rd version Core */ 194 #define CPU_ID_PXA250C 0x69052d00 /* 4th version Core */ 195 #define CPU_ID_PXA210C 0x69052d20 /* 4th version Core */ 196 #define CPU_ID_PXA27X 0x69054110 197 #define CPU_ID_80321_400 0x69052420 198 #define CPU_ID_80321_600 0x69052430 199 #define CPU_ID_80321_400_B0 0x69052c20 200 #define CPU_ID_80321_600_B0 0x69052c30 201 #define CPU_ID_80219_400 0x69052e20 /* A0 stepping/revision. */ 202 #define CPU_ID_80219_600 0x69052e30 /* A0 stepping/revision. */ 203 #define CPU_ID_81342 0x69056810 204 #define CPU_ID_IXP425 0x690541c0 205 #define CPU_ID_IXP425_533 0x690541c0 206 #define CPU_ID_IXP425_400 0x690541d0 207 #define CPU_ID_IXP425_266 0x690541f0 208 #define CPU_ID_IXP435 0x69054040 209 #define CPU_ID_IXP465 0x69054200 210 211 /* ARM3-specific coprocessor 15 registers */ 212 #define ARM3_CP15_FLUSH 1 213 #define ARM3_CP15_CONTROL 2 214 #define ARM3_CP15_CACHEABLE 3 215 #define ARM3_CP15_UPDATEABLE 4 216 #define ARM3_CP15_DISRUPTIVE 5 217 218 /* ARM3 Control register bits */ 219 #define ARM3_CTL_CACHE_ON 0x00000001 220 #define ARM3_CTL_SHARED 0x00000002 221 #define ARM3_CTL_MONITOR 0x00000004 222 223 /* CPUID registers */ 224 #define ARM_PFR0_ARM_ISA_MASK 0x0000000f 225 226 #define ARM_PFR0_THUMB_MASK 0x000000f0 227 #define ARM_PFR0_THUMB 0x10 228 #define ARM_PFR0_THUMB2 0x30 229 230 #define ARM_PFR0_JAZELLE_MASK 0x00000f00 231 #define ARM_PFR0_THUMBEE_MASK 0x0000f000 232 233 #define ARM_PFR1_ARMV4_MASK 0x0000000f 234 #define ARM_PFR1_SEC_EXT_MASK 0x000000f0 235 #define ARM_PFR1_MICROCTRL_MASK 0x00000f00 236 237 /* 238 * Post-ARM3 CP15 registers: 239 * 240 * 1 Control register 241 * 242 * 2 Translation Table Base 243 * 244 * 3 Domain Access Control 245 * 246 * 4 Reserved 247 * 248 * 5 Fault Status 249 * 250 * 6 Fault Address 251 * 252 * 7 Cache/write-buffer Control 253 * 254 * 8 TLB Control 255 * 256 * 9 Cache Lockdown 257 * 258 * 10 TLB Lockdown 259 * 260 * 11 Reserved 261 * 262 * 12 Reserved 263 * 264 * 13 Process ID (for FCSE) 265 * 266 * 14 Reserved 267 * 268 * 15 Implementation Dependent 269 */ 270 271 /* Some of the definitions below need cleaning up for V3/V4 architectures */ 272 273 /* CPU control register (CP15 register 1) */ 274 #define CPU_CONTROL_MMU_ENABLE 0x00000001 /* M: MMU/Protection unit enable */ 275 #define CPU_CONTROL_AFLT_ENABLE 0x00000002 /* A: Alignment fault enable */ 276 #define CPU_CONTROL_DC_ENABLE 0x00000004 /* C: IDC/DC enable */ 277 #define CPU_CONTROL_WBUF_ENABLE 0x00000008 /* W: Write buffer enable */ 278 #define CPU_CONTROL_32BP_ENABLE 0x00000010 /* P: 32-bit exception handlers */ 279 #define CPU_CONTROL_32BD_ENABLE 0x00000020 /* D: 32-bit addressing */ 280 #define CPU_CONTROL_LABT_ENABLE 0x00000040 /* L: Late abort enable */ 281 #define CPU_CONTROL_BEND_ENABLE 0x00000080 /* B: Big-endian mode */ 282 #define CPU_CONTROL_SYST_ENABLE 0x00000100 /* S: System protection bit */ 283 #define CPU_CONTROL_ROM_ENABLE 0x00000200 /* R: ROM protection bit */ 284 #define CPU_CONTROL_CPCLK 0x00000400 /* F: Implementation defined */ 285 #define CPU_CONTROL_BPRD_ENABLE 0x00000800 /* Z: Branch prediction enable */ 286 #define CPU_CONTROL_IC_ENABLE 0x00001000 /* I: IC enable */ 287 #define CPU_CONTROL_VECRELOC 0x00002000 /* V: Vector relocation */ 288 #define CPU_CONTROL_ROUNDROBIN 0x00004000 /* RR: Predictable replacement */ 289 #define CPU_CONTROL_V4COMPAT 0x00008000 /* L4: ARMv4 compat LDR R15 etc */ 290 #define CPU_CONTROL_FI_ENABLE 0x00200000 /* FI: Low interrupt latency */ 291 #define CPU_CONTROL_UNAL_ENABLE 0x00400000 /* U: unaligned data access */ 292 #define CPU_CONTROL_V6_EXTPAGE 0x00800000 /* XP: ARMv6 extended page tables */ 293 #define CPU_CONTROL_L2_ENABLE 0x04000000 /* L2 Cache enabled */ 294 #define CPU_CONTROL_AF_ENABLE 0x20000000 /* Access Flag enable */ 295 296 #define CPU_CONTROL_IDC_ENABLE CPU_CONTROL_DC_ENABLE 297 298 /* ARM11x6 Auxiliary Control Register (CP15 register 1, opcode2 1) */ 299 #define ARM11X6_AUXCTL_RS 0x00000001 /* return stack */ 300 #define ARM11X6_AUXCTL_DB 0x00000002 /* dynamic branch prediction */ 301 #define ARM11X6_AUXCTL_SB 0x00000004 /* static branch prediction */ 302 #define ARM11X6_AUXCTL_TR 0x00000008 /* MicroTLB replacement strat. */ 303 #define ARM11X6_AUXCTL_EX 0x00000010 /* exclusive L1/L2 cache */ 304 #define ARM11X6_AUXCTL_RA 0x00000020 /* clean entire cache disable */ 305 #define ARM11X6_AUXCTL_RV 0x00000040 /* block transfer cache disable */ 306 #define ARM11X6_AUXCTL_CZ 0x00000080 /* restrict cache size */ 307 308 /* ARM1136 Auxiliary Control Register (CP15 register 1, opcode2 1) */ 309 #define ARM1136_AUXCTL_PFI 0x80000000 /* PFI: partial FI mode. */ 310 /* This is an undocumented flag 311 * used to work around a cache bug 312 * in r0 steppings. See errata 313 * 364296. 314 */ 315 /* ARM1176 Auxiliary Control Register (CP15 register 1, opcode2 1) */ 316 #define ARM1176_AUXCTL_PHD 0x10000000 /* inst. prefetch halting disable */ 317 #define ARM1176_AUXCTL_BFD 0x20000000 /* branch folding disable */ 318 #define ARM1176_AUXCTL_FSD 0x40000000 /* force speculative ops disable */ 319 #define ARM1176_AUXCTL_FIO 0x80000000 /* low intr latency override */ 320 321 /* XScale Auxillary Control Register (CP15 register 1, opcode2 1) */ 322 #define XSCALE_AUXCTL_K 0x00000001 /* dis. write buffer coalescing */ 323 #define XSCALE_AUXCTL_P 0x00000002 /* ECC protect page table access */ 324 /* Note: XSCale core 3 uses those for LLR DCcahce attributes */ 325 #define XSCALE_AUXCTL_MD_WB_RA 0x00000000 /* mini-D$ wb, read-allocate */ 326 #define XSCALE_AUXCTL_MD_WB_RWA 0x00000010 /* mini-D$ wb, read/write-allocate */ 327 #define XSCALE_AUXCTL_MD_WT 0x00000020 /* mini-D$ wt, read-allocate */ 328 #define XSCALE_AUXCTL_MD_MASK 0x00000030 329 330 /* Xscale Core 3 only */ 331 #define XSCALE_AUXCTL_LLR 0x00000400 /* Enable L2 for LLR Cache */ 332 333 /* Marvell Extra Features Register (CP15 register 1, opcode2 0) */ 334 #define MV_DC_REPLACE_LOCK 0x80000000 /* Replace DCache Lock */ 335 #define MV_DC_STREAM_ENABLE 0x20000000 /* DCache Streaming Switch */ 336 #define MV_WA_ENABLE 0x10000000 /* Enable Write Allocate */ 337 #define MV_L2_PREFETCH_DISABLE 0x01000000 /* L2 Cache Prefetch Disable */ 338 #define MV_L2_INV_EVICT_ERR 0x00800000 /* L2 Invalidates Uncorrectable Error Line Eviction */ 339 #define MV_L2_ENABLE 0x00400000 /* L2 Cache enable */ 340 #define MV_IC_REPLACE_LOCK 0x00080000 /* Replace ICache Lock */ 341 #define MV_BGH_ENABLE 0x00040000 /* Branch Global History Register Enable */ 342 #define MV_BTB_DISABLE 0x00020000 /* Branch Target Buffer Disable */ 343 #define MV_L1_PARERR_ENABLE 0x00010000 /* L1 Parity Error Enable */ 344 345 /* Cache type register definitions */ 346 #define CPU_CT_ISIZE(x) ((x) & 0xfff) /* I$ info */ 347 #define CPU_CT_DSIZE(x) (((x) >> 12) & 0xfff) /* D$ info */ 348 #define CPU_CT_S (1U << 24) /* split cache */ 349 #define CPU_CT_CTYPE(x) (((x) >> 25) & 0xf) /* cache type */ 350 #define CPU_CT_FORMAT(x) ((x) >> 29) 351 352 #define CPU_CT_CTYPE_WT 0 /* write-through */ 353 #define CPU_CT_CTYPE_WB1 1 /* write-back, clean w/ read */ 354 #define CPU_CT_CTYPE_WB2 2 /* w/b, clean w/ cp15,7 */ 355 #define CPU_CT_CTYPE_WB6 6 /* w/b, cp15,7, lockdown fmt A */ 356 #define CPU_CT_CTYPE_WB7 7 /* w/b, cp15,7, lockdown fmt B */ 357 358 #define CPU_CT_xSIZE_LEN(x) ((x) & 0x3) /* line size */ 359 #define CPU_CT_xSIZE_M (1U << 2) /* multiplier */ 360 #define CPU_CT_xSIZE_ASSOC(x) (((x) >> 3) & 0x7) /* associativity */ 361 #define CPU_CT_xSIZE_SIZE(x) (((x) >> 6) & 0x7) /* size */ 362 363 #define CPU_CT_ARMV7 0x4 364 /* ARM v7 Cache type definitions */ 365 #define CPUV7_CT_CTYPE_WT (1 << 31) 366 #define CPUV7_CT_CTYPE_WB (1 << 30) 367 #define CPUV7_CT_CTYPE_RA (1 << 29) 368 #define CPUV7_CT_CTYPE_WA (1 << 28) 369 370 #define CPUV7_CT_xSIZE_LEN(x) ((x) & 0x7) /* line size */ 371 #define CPUV7_CT_xSIZE_ASSOC(x) (((x) >> 3) & 0x3ff) /* associativity */ 372 #define CPUV7_CT_xSIZE_SET(x) (((x) >> 13) & 0x7fff) /* num sets */ 373 374 #define CPU_CLIDR_CTYPE(reg,x) (((reg) >> ((x) * 3)) & 0x7) 375 #define CPU_CLIDR_LOUIS(reg) (((reg) >> 21) & 0x7) 376 #define CPU_CLIDR_LOC(reg) (((reg) >> 24) & 0x7) 377 #define CPU_CLIDR_LOUU(reg) (((reg) >> 27) & 0x7) 378 379 #define CACHE_ICACHE 1 380 #define CACHE_DCACHE 2 381 #define CACHE_SEP_CACHE 3 382 #define CACHE_UNI_CACHE 4 383 384 /* Fault status register definitions */ 385 386 #define FAULT_TYPE_MASK 0x0f 387 #define FAULT_USER 0x10 388 389 #define FAULT_WRTBUF_0 0x00 /* Vector Exception */ 390 #define FAULT_WRTBUF_1 0x02 /* Terminal Exception */ 391 #define FAULT_BUSERR_0 0x04 /* External Abort on Linefetch -- Section */ 392 #define FAULT_BUSERR_1 0x06 /* External Abort on Linefetch -- Page */ 393 #define FAULT_BUSERR_2 0x08 /* External Abort on Non-linefetch -- Section */ 394 #define FAULT_BUSERR_3 0x0a /* External Abort on Non-linefetch -- Page */ 395 #define FAULT_BUSTRNL1 0x0c /* External abort on Translation -- Level 1 */ 396 #define FAULT_BUSTRNL2 0x0e /* External abort on Translation -- Level 2 */ 397 #define FAULT_ALIGN_0 0x01 /* Alignment */ 398 #define FAULT_ALIGN_1 0x03 /* Alignment */ 399 #define FAULT_TRANS_S 0x05 /* Translation -- Section */ 400 #define FAULT_TRANS_F 0x06 /* Translation -- Flag */ 401 #define FAULT_TRANS_P 0x07 /* Translation -- Page */ 402 #define FAULT_DOMAIN_S 0x09 /* Domain -- Section */ 403 #define FAULT_DOMAIN_P 0x0b /* Domain -- Page */ 404 #define FAULT_PERM_S 0x0d /* Permission -- Section */ 405 #define FAULT_PERM_P 0x0f /* Permission -- Page */ 406 407 #define FAULT_IMPRECISE 0x400 /* Imprecise exception (XSCALE) */ 408 409 /* 410 * Address of the vector page, low and high versions. 411 */ 412 #ifndef __ASSEMBLER__ 413 #define ARM_VECTORS_LOW 0x00000000U 414 #define ARM_VECTORS_HIGH 0xffff0000U 415 #else 416 #define ARM_VECTORS_LOW 0 417 #define ARM_VECTORS_HIGH 0xffff0000 418 #endif 419 420 /* 421 * ARM Instructions 422 * 423 * 3 3 2 2 2 424 * 1 0 9 8 7 0 425 * +-------+-------------------------------------------------------+ 426 * | cond | instruction dependant | 427 * |c c c c| | 428 * +-------+-------------------------------------------------------+ 429 */ 430 431 #define INSN_SIZE 4 /* Always 4 bytes */ 432 #define INSN_COND_MASK 0xf0000000 /* Condition mask */ 433 #define INSN_COND_AL 0xe0000000 /* Always condition */ 434 435 #define THUMB_INSN_SIZE 2 /* Some are 4 bytes. */ 436 437 #endif /* !MACHINE_ARMREG_H */ 438