1 /* $NetBSD: pte.h,v 1.1 2001/11/23 17:39:04 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1994 Mark Brinicombe. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by the RiscBSD team. 18 * 4. The name "RiscBSD" nor the name of the author may be used to 19 * endorse or promote products derived from this software without specific 20 * prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY RISCBSD ``AS IS'' AND ANY EXPRESS OR IMPLIED 23 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 24 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL RISCBSD OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 26 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 27 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 * 34 * $FreeBSD$ 35 */ 36 #ifdef ARM_NEW_PMAP 37 #include <machine/pte-v6.h> 38 #else /* ARM_NEW_PMAP */ 39 40 #ifndef _MACHINE_PTE_H_ 41 #define _MACHINE_PTE_H_ 42 43 #ifndef LOCORE 44 typedef uint32_t pd_entry_t; /* page directory entry */ 45 typedef uint32_t pt_entry_t; /* page table entry */ 46 typedef pt_entry_t pt2_entry_t; /* compatibility with v6 */ 47 #endif 48 49 #define PG_FRAME 0xfffff000 50 51 /* The PT_SIZE definition is misleading... A page table is only 0x400 52 * bytes long. But since VM mapping can only be done to 0x1000 a single 53 * 1KB blocks cannot be steered to a va by itself. Therefore the 54 * pages tables are allocated in blocks of 4. i.e. if a 1 KB block 55 * was allocated for a PT then the other 3KB would also get mapped 56 * whenever the 1KB was mapped. 57 */ 58 59 #define PT_RSIZE 0x0400 /* Real page table size */ 60 #define PT_SIZE 0x1000 61 #define PD_SIZE 0x4000 62 63 /* Page table types and masks */ 64 #define L1_PAGE 0x01 /* L1 page table mapping */ 65 #define L1_SECTION 0x02 /* L1 section mapping */ 66 #define L1_FPAGE 0x03 /* L1 fine page mapping */ 67 #define L1_MASK 0x03 /* Mask for L1 entry type */ 68 #define L2_LPAGE 0x01 /* L2 large page (64KB) */ 69 #define L2_SPAGE 0x02 /* L2 small page (4KB) */ 70 #define L2_MASK 0x03 /* Mask for L2 entry type */ 71 #define L2_INVAL 0x00 /* L2 invalid type */ 72 73 /* L1 and L2 address masks */ 74 #define L1_ADDR_MASK 0xfffffc00 75 #define L2_ADDR_MASK 0xfffff000 76 77 /* 78 * The ARM MMU architecture was introduced with ARM v3 (previous ARM 79 * architecture versions used an optional off-CPU memory controller 80 * to perform address translation). 81 * 82 * The ARM MMU consists of a TLB and translation table walking logic. 83 * There is typically one TLB per memory interface (or, put another 84 * way, one TLB per software-visible cache). 85 * 86 * The ARM MMU is capable of mapping memory in the following chunks: 87 * 88 * 1M Sections (L1 table) 89 * 90 * 64K Large Pages (L2 table) 91 * 92 * 4K Small Pages (L2 table) 93 * 94 * 1K Tiny Pages (L2 table) 95 * 96 * There are two types of L2 tables: Coarse Tables and Fine Tables. 97 * Coarse Tables can map Large and Small Pages. Fine Tables can 98 * map Tiny Pages. 99 * 100 * Coarse Tables can define 4 Subpages within Large and Small pages. 101 * Subpages define different permissions for each Subpage within 102 * a Page. 103 * 104 * Coarse Tables are 1K in length. Fine tables are 4K in length. 105 * 106 * The Translation Table Base register holds the pointer to the 107 * L1 Table. The L1 Table is a 16K contiguous chunk of memory 108 * aligned to a 16K boundary. Each entry in the L1 Table maps 109 * 1M of virtual address space, either via a Section mapping or 110 * via an L2 Table. 111 * 112 * In addition, the Fast Context Switching Extension (FCSE) is available 113 * on some ARM v4 and ARM v5 processors. FCSE is a way of eliminating 114 * TLB/cache flushes on context switch by use of a smaller address space 115 * and a "process ID" that modifies the virtual address before being 116 * presented to the translation logic. 117 */ 118 119 /* ARMv6 super-sections. */ 120 #define L1_SUP_SIZE 0x01000000 /* 16M */ 121 #define L1_SUP_OFFSET (L1_SUP_SIZE - 1) 122 #define L1_SUP_FRAME (~L1_SUP_OFFSET) 123 #define L1_SUP_SHIFT 24 124 125 #define L1_S_SIZE 0x00100000 /* 1M */ 126 #define L1_S_OFFSET (L1_S_SIZE - 1) 127 #define L1_S_FRAME (~L1_S_OFFSET) 128 #define L1_S_SHIFT 20 129 130 #define L2_L_SIZE 0x00010000 /* 64K */ 131 #define L2_L_OFFSET (L2_L_SIZE - 1) 132 #define L2_L_FRAME (~L2_L_OFFSET) 133 #define L2_L_SHIFT 16 134 135 #define L2_S_SIZE 0x00001000 /* 4K */ 136 #define L2_S_OFFSET (L2_S_SIZE - 1) 137 #define L2_S_FRAME (~L2_S_OFFSET) 138 #define L2_S_SHIFT 12 139 140 #define L2_T_SIZE 0x00000400 /* 1K */ 141 #define L2_T_OFFSET (L2_T_SIZE - 1) 142 #define L2_T_FRAME (~L2_T_OFFSET) 143 #define L2_T_SHIFT 10 144 145 /* 146 * The NetBSD VM implementation only works on whole pages (4K), 147 * whereas the ARM MMU's Coarse tables are sized in terms of 1K 148 * (16K L1 table, 1K L2 table). 149 * 150 * So, we allocate L2 tables 4 at a time, thus yielding a 4K L2 151 * table. 152 */ 153 #define L1_ADDR_BITS 0xfff00000 /* L1 PTE address bits */ 154 #define L2_ADDR_BITS 0x000ff000 /* L2 PTE address bits */ 155 156 #define L1_TABLE_SIZE 0x4000 /* 16K */ 157 #define L2_TABLE_SIZE 0x1000 /* 4K */ 158 /* 159 * The new pmap deals with the 1KB coarse L2 tables by 160 * allocating them from a pool. Until every port has been converted, 161 * keep the old L2_TABLE_SIZE define lying around. Converted ports 162 * should use L2_TABLE_SIZE_REAL until then. 163 */ 164 #define L2_TABLE_SIZE_REAL 0x400 /* 1K */ 165 166 /* Total number of page table entries in L2 table */ 167 #define L2_PTE_NUM_TOTAL (L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)) 168 169 /* 170 * ARM L1 Descriptors 171 */ 172 173 #define L1_TYPE_INV 0x00 /* Invalid (fault) */ 174 #define L1_TYPE_C 0x01 /* Coarse L2 */ 175 #define L1_TYPE_S 0x02 /* Section */ 176 #define L1_TYPE_F 0x03 /* Fine L2 */ 177 #define L1_TYPE_MASK 0x03 /* mask of type bits */ 178 179 /* L1 Section Descriptor */ 180 #define L1_S_B 0x00000004 /* bufferable Section */ 181 #define L1_S_C 0x00000008 /* cacheable Section */ 182 #define L1_S_IMP 0x00000010 /* implementation defined */ 183 #define L1_S_XN (1 << 4) /* execute not */ 184 #define L1_S_DOM(x) ((x) << 5) /* domain */ 185 #define L1_S_DOM_MASK L1_S_DOM(0xf) 186 #define L1_S_AP(x) ((x) << 10) /* access permissions */ 187 #define L1_S_ADDR_MASK 0xfff00000 /* phys address of section */ 188 #define L1_S_TEX(x) (((x) & 0x7) << 12) /* Type Extension */ 189 #define L1_S_TEX_MASK (0x7 << 12) /* Type Extension */ 190 #define L1_S_APX (1 << 15) 191 #define L1_SHARED (1 << 16) 192 193 #define L1_S_XSCALE_P 0x00000200 /* ECC enable for this section */ 194 #define L1_S_XSCALE_TEX(x) ((x) << 12) /* Type Extension */ 195 196 #define L1_S_SUPERSEC ((1) << 18) /* Section is a super-section. */ 197 198 /* L1 Coarse Descriptor */ 199 #define L1_C_IMP0 0x00000004 /* implementation defined */ 200 #define L1_C_IMP1 0x00000008 /* implementation defined */ 201 #define L1_C_IMP2 0x00000010 /* implementation defined */ 202 #define L1_C_DOM(x) ((x) << 5) /* domain */ 203 #define L1_C_DOM_MASK L1_C_DOM(0xf) 204 #define L1_C_ADDR_MASK 0xfffffc00 /* phys address of L2 Table */ 205 206 #define L1_C_XSCALE_P 0x00000200 /* ECC enable for this section */ 207 208 /* L1 Fine Descriptor */ 209 #define L1_F_IMP0 0x00000004 /* implementation defined */ 210 #define L1_F_IMP1 0x00000008 /* implementation defined */ 211 #define L1_F_IMP2 0x00000010 /* implementation defined */ 212 #define L1_F_DOM(x) ((x) << 5) /* domain */ 213 #define L1_F_DOM_MASK L1_F_DOM(0xf) 214 #define L1_F_ADDR_MASK 0xfffff000 /* phys address of L2 Table */ 215 216 #define L1_F_XSCALE_P 0x00000200 /* ECC enable for this section */ 217 218 /* 219 * ARM L2 Descriptors 220 */ 221 222 #define L2_TYPE_INV 0x00 /* Invalid (fault) */ 223 #define L2_TYPE_L 0x01 /* Large Page */ 224 #define L2_TYPE_S 0x02 /* Small Page */ 225 #define L2_TYPE_T 0x03 /* Tiny Page */ 226 #define L2_TYPE_MASK 0x03 /* mask of type bits */ 227 228 /* 229 * This L2 Descriptor type is available on XScale processors 230 * when using a Coarse L1 Descriptor. The Extended Small 231 * Descriptor has the same format as the XScale Tiny Descriptor, 232 * but describes a 4K page, rather than a 1K page. 233 */ 234 #define L2_TYPE_XSCALE_XS 0x03 /* XScale Extended Small Page */ 235 236 #define L2_B 0x00000004 /* Bufferable page */ 237 #define L2_C 0x00000008 /* Cacheable page */ 238 #define L2_AP0(x) ((x) << 4) /* access permissions (sp 0) */ 239 #define L2_AP1(x) ((x) << 6) /* access permissions (sp 1) */ 240 #define L2_AP2(x) ((x) << 8) /* access permissions (sp 2) */ 241 #define L2_AP3(x) ((x) << 10) /* access permissions (sp 3) */ 242 243 #define L2_SHARED (1 << 10) 244 #define L2_APX (1 << 9) 245 #define L2_XN (1 << 0) 246 #define L2_L_TEX_MASK (0x7 << 12) /* Type Extension */ 247 #define L2_L_TEX(x) (((x) & 0x7) << 12) 248 #define L2_S_TEX_MASK (0x7 << 6) /* Type Extension */ 249 #define L2_S_TEX(x) (((x) & 0x7) << 6) 250 251 #define L2_XSCALE_L_TEX(x) ((x) << 12) /* Type Extension */ 252 #define L2_XSCALE_L_S(x) (1 << 15) /* Shared */ 253 #define L2_XSCALE_T_TEX(x) ((x) << 6) /* Type Extension */ 254 255 /* 256 * Access Permissions for L1 and L2 Descriptors. 257 */ 258 #define AP_W 0x01 /* writable */ 259 #define AP_REF 0x01 /* referenced flag */ 260 #define AP_U 0x02 /* user */ 261 262 /* 263 * Short-hand for common AP_* constants. 264 * 265 * Note: These values assume the S (System) bit is set and 266 * the R (ROM) bit is clear in CP15 register 1. 267 */ 268 #define AP_KR 0x00 /* kernel read */ 269 #define AP_KRW 0x01 /* kernel read/write */ 270 #define AP_KRWUR 0x02 /* kernel read/write usr read */ 271 #define AP_KRWURW 0x03 /* kernel read/write usr read/write */ 272 273 /* 274 * Domain Types for the Domain Access Control Register. 275 */ 276 #define DOMAIN_FAULT 0x00 /* no access */ 277 #define DOMAIN_CLIENT 0x01 /* client */ 278 #define DOMAIN_RESERVED 0x02 /* reserved */ 279 #define DOMAIN_MANAGER 0x03 /* manager */ 280 281 /* 282 * Type Extension bits for XScale processors. 283 * 284 * Behavior of C and B when X == 0: 285 * 286 * C B Cacheable Bufferable Write Policy Line Allocate Policy 287 * 0 0 N N - - 288 * 0 1 N Y - - 289 * 1 0 Y Y Write-through Read Allocate 290 * 1 1 Y Y Write-back Read Allocate 291 * 292 * Behavior of C and B when X == 1: 293 * C B Cacheable Bufferable Write Policy Line Allocate Policy 294 * 0 0 - - - - DO NOT USE 295 * 0 1 N Y - - 296 * 1 0 Mini-Data - - - 297 * 1 1 Y Y Write-back R/W Allocate 298 */ 299 #define TEX_XSCALE_X 0x01 /* X modifies C and B */ 300 #define TEX_XSCALE_E 0x02 301 #define TEX_XSCALE_T 0x04 302 303 /* Xscale core 3 */ 304 305 /* 306 * 307 * Cache attributes with L2 present, S = 0 308 * T E X C B L1 i-cache L1 d-cache L1 DC WP L2 cacheable write coalesce 309 * 0 0 0 0 0 N N - N N 310 * 0 0 0 0 1 N N - N Y 311 * 0 0 0 1 0 Y Y WT N Y 312 * 0 0 0 1 1 Y Y WB Y Y 313 * 0 0 1 0 0 N N - Y Y 314 * 0 0 1 0 1 N N - N N 315 * 0 0 1 1 0 Y Y - - N 316 * 0 0 1 1 1 Y Y WT Y Y 317 * 0 1 0 0 0 N N - N N 318 * 0 1 0 0 1 N/A N/A N/A N/A N/A 319 * 0 1 0 1 0 N/A N/A N/A N/A N/A 320 * 0 1 0 1 1 N/A N/A N/A N/A N/A 321 * 0 1 1 X X N/A N/A N/A N/A N/A 322 * 1 X 0 0 0 N N - N Y 323 * 1 X 0 0 1 Y N WB N Y 324 * 1 X 0 1 0 Y N WT N Y 325 * 1 X 0 1 1 Y N WB Y Y 326 * 1 X 1 0 0 N N - Y Y 327 * 1 X 1 0 1 Y Y WB Y Y 328 * 1 X 1 1 0 Y Y WT Y Y 329 * 1 X 1 1 1 Y Y WB Y Y 330 * 331 * 332 * 333 * 334 * Cache attributes with L2 present, S = 1 335 * T E X C B L1 i-cache L1 d-cache L1 DC WP L2 cacheable write coalesce 336 * 0 0 0 0 0 N N - N N 337 * 0 0 0 0 1 N N - N Y 338 * 0 0 0 1 0 Y Y - N Y 339 * 0 0 0 1 1 Y Y WT Y Y 340 * 0 0 1 0 0 N N - Y Y 341 * 0 0 1 0 1 N N - N N 342 * 0 0 1 1 0 Y Y - - N 343 * 0 0 1 1 1 Y Y WT Y Y 344 * 0 1 0 0 0 N N - N N 345 * 0 1 0 0 1 N/A N/A N/A N/A N/A 346 * 0 1 0 1 0 N/A N/A N/A N/A N/A 347 * 0 1 0 1 1 N/A N/A N/A N/A N/A 348 * 0 1 1 X X N/A N/A N/A N/A N/A 349 * 1 X 0 0 0 N N - N Y 350 * 1 X 0 0 1 Y N - N Y 351 * 1 X 0 1 0 Y N - N Y 352 * 1 X 0 1 1 Y N - Y Y 353 * 1 X 1 0 0 N N - Y Y 354 * 1 X 1 0 1 Y Y WT Y Y 355 * 1 X 1 1 0 Y Y WT Y Y 356 * 1 X 1 1 1 Y Y WT Y Y 357 */ 358 #endif /* !_MACHINE_PTE_H_ */ 359 #endif /* !ARM_NEW_PMAP */ 360 361 /* End of pte.h */ 362