xref: /freebsd/sys/arm/include/sysarch.h (revision e17f5b1d)
1 /*	$NetBSD: sysarch.h,v 1.5 2003/09/11 09:40:12 kleink Exp $	*/
2 
3 /*-
4  * SPDX-License-Identifier: BSD-4-Clause
5  *
6  * Copyright (c) 1996-1997 Mark Brinicombe.
7  * All rights reserved.
8  *
9  * Redistribution and use in source and binary forms, with or without
10  * modification, are permitted provided that the following conditions
11  * are met:
12  * 1. Redistributions of source code must retain the above copyright
13  *    notice, this list of conditions and the following disclaimer.
14  * 2. Redistributions in binary form must reproduce the above copyright
15  *    notice, this list of conditions and the following disclaimer in the
16  *    documentation and/or other materials provided with the distribution.
17  * 3. All advertising materials mentioning features or use of this software
18  *    must display the following acknowledgement:
19  *	This product includes software developed by Mark Brinicombe.
20  * 4. The name of the company nor the name of the author may be used to
21  *    endorse or promote products derived from this software without specific
22  *    prior written permission.
23  *
24  * THIS SOFTWARE IS PROVIDED BY AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
25  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
26  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
27  * IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
28  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
29  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
30  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
31  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
32  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
33  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
34  * SUCH DAMAGE.
35  */
36 
37 /* $FreeBSD$ */
38 
39 #ifndef _ARM_SYSARCH_H_
40 #define _ARM_SYSARCH_H_
41 
42 #include <machine/armreg.h>
43 
44 /*
45  * The ARM_TP_ADDRESS points to a special purpose page, which is used as local
46  * store for the ARM per-thread data and Restartable Atomic Sequences support.
47  * Put it just above the "high" vectors' page.
48  * The cpu_switch() code assumes ARM_RAS_START is ARM_TP_ADDRESS + 4, and
49  * ARM_RAS_END is ARM_TP_ADDRESS + 8, so if that ever changes, be sure to
50  * update the cpu_switch() (and cpu_throw()) code as well.
51  * In addition, code in arm/include/atomic.h and arm/arm/exception.S
52  * assumes that ARM_RAS_END is at ARM_RAS_START+4, so be sure to update those
53  * if ARM_RAS_END moves in relation to ARM_RAS_START (look for occurrences
54  * of ldr/str rm,[rn, #4]).
55  */
56 
57 /* ARM_TP_ADDRESS is needed for processors that don't support
58  * the exclusive-access opcodes introduced with ARMv6K. */
59 #if __ARM_ARCH <= 5
60 #define ARM_TP_ADDRESS		(ARM_VECTORS_HIGH + 0x1000)
61 #define ARM_RAS_START		(ARM_TP_ADDRESS + 4)
62 #define ARM_RAS_END		(ARM_TP_ADDRESS + 8)
63 #endif
64 
65 #ifndef LOCORE
66 #ifndef __ASSEMBLER__
67 
68 /*
69  * Pickup definition of various __types.
70  */
71 #include <sys/_types.h>
72 
73 /*
74  * Architecture specific syscalls (arm)
75  */
76 
77 #define ARM_SYNC_ICACHE		0
78 #define ARM_DRAIN_WRITEBUF	1
79 #define ARM_SET_TP		2
80 #define ARM_GET_TP		3
81 #define ARM_GET_VFPSTATE	4
82 
83 struct arm_sync_icache_args {
84 	__uintptr_t	addr;		/* Virtual start address */
85 	__size_t	len;		/* Region size */
86 };
87 
88 struct arm_get_vfpstate_args {
89 	__size_t	mc_vfp_size;
90 	void 		*mc_vfp;
91 };
92 
93 #ifndef _KERNEL
94 __BEGIN_DECLS
95 int	arm_sync_icache(unsigned int, int);
96 int	arm_drain_writebuf(void);
97 int	sysarch(int, void *);
98 __END_DECLS
99 #endif
100 
101 #endif /* __ASSEMBLER__ */
102 #endif /* LOCORE */
103 
104 #endif /* !_ARM_SYSARCH_H_ */
105