1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2018-2019, Rubicon Communications, LLC (Netgate) 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 * 27 */ 28 29 #include <sys/cdefs.h> 30 #include <sys/param.h> 31 #include <sys/systm.h> 32 #include <sys/bus.h> 33 34 #include <sys/gpio.h> 35 #include <sys/kernel.h> 36 #include <sys/module.h> 37 #include <sys/rman.h> 38 39 #include <machine/bus.h> 40 #include <machine/resource.h> 41 42 #include <dev/gpio/gpiobusvar.h> 43 #include <dev/ofw/ofw_bus.h> 44 #include <dev/ofw/ofw_bus_subr.h> 45 46 #include "gpio_if.h" 47 #include "syscon_if.h" 48 49 struct a37x0_gpio_softc { 50 device_t sc_busdev; 51 int sc_type; 52 uint32_t sc_max_pins; 53 uint32_t sc_npins; 54 struct syscon *syscon; 55 }; 56 57 /* Memory regions. */ 58 #define A37X0_GPIO 0 59 #define A37X0_INTR 1 60 61 /* North Bridge / South Bridge. */ 62 #define A37X0_NB_GPIO 1 63 #define A37X0_SB_GPIO 2 64 65 #define A37X0_GPIO_WRITE(_sc, _off, _val) \ 66 SYSCON_WRITE_4((_sc)->syscon, (_off), (_val)) 67 #define A37X0_GPIO_READ(_sc, _off) \ 68 SYSCON_READ_4((_sc)->syscon, (_off)) 69 70 #define A37X0_GPIO_BIT(_p) (1U << ((_p) % 32)) 71 #define A37X0_GPIO_OUT_EN(_p) (0x0 + ((_p) / 32) * 4) 72 #define A37X0_GPIO_LATCH(_p) (0x8 + ((_p) / 32) * 4) 73 #define A37X0_GPIO_INPUT(_p) (0x10 + ((_p) / 32) * 4) 74 #define A37X0_GPIO_OUTPUT(_p) (0x18 + ((_p) / 32) * 4) 75 #define A37X0_GPIO_SEL 0x30 76 77 static struct ofw_compat_data compat_data[] = { 78 { "marvell,armada3710-nb-pinctrl", A37X0_NB_GPIO }, 79 { "marvell,armada3710-sb-pinctrl", A37X0_SB_GPIO }, 80 { NULL, 0 } 81 }; 82 83 static phandle_t 84 a37x0_gpio_get_node(device_t bus, device_t dev) 85 { 86 87 return (ofw_bus_get_node(bus)); 88 } 89 90 static device_t 91 a37x0_gpio_get_bus(device_t dev) 92 { 93 struct a37x0_gpio_softc *sc; 94 95 sc = device_get_softc(dev); 96 97 return (sc->sc_busdev); 98 } 99 100 static int 101 a37x0_gpio_pin_max(device_t dev, int *maxpin) 102 { 103 struct a37x0_gpio_softc *sc; 104 105 sc = device_get_softc(dev); 106 *maxpin = sc->sc_npins - 1; 107 108 return (0); 109 } 110 111 static int 112 a37x0_gpio_pin_getname(device_t dev, uint32_t pin, char *name) 113 { 114 struct a37x0_gpio_softc *sc; 115 116 sc = device_get_softc(dev); 117 if (pin >= sc->sc_npins) 118 return (EINVAL); 119 snprintf(name, GPIOMAXNAME, "pin %d", pin); 120 121 return (0); 122 } 123 124 static int 125 a37x0_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps) 126 { 127 struct a37x0_gpio_softc *sc; 128 129 sc = device_get_softc(dev); 130 if (pin >= sc->sc_npins) 131 return (EINVAL); 132 *caps = GPIO_PIN_INPUT | GPIO_PIN_OUTPUT; 133 134 return (0); 135 } 136 137 static int 138 a37x0_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags) 139 { 140 struct a37x0_gpio_softc *sc; 141 uint32_t reg; 142 143 sc = device_get_softc(dev); 144 if (pin >= sc->sc_npins) 145 return (EINVAL); 146 reg = A37X0_GPIO_READ(sc, A37X0_GPIO_OUT_EN(pin)); 147 if ((reg & A37X0_GPIO_BIT(pin)) != 0) 148 *flags = GPIO_PIN_OUTPUT; 149 else 150 *flags = GPIO_PIN_INPUT; 151 152 return (0); 153 } 154 155 static int 156 a37x0_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags) 157 { 158 struct a37x0_gpio_softc *sc; 159 uint32_t reg; 160 161 sc = device_get_softc(dev); 162 if (pin >= sc->sc_npins) 163 return (EINVAL); 164 165 reg = A37X0_GPIO_READ(sc, A37X0_GPIO_OUT_EN(pin)); 166 if (flags & GPIO_PIN_OUTPUT) 167 reg |= A37X0_GPIO_BIT(pin); 168 else 169 reg &= ~A37X0_GPIO_BIT(pin); 170 A37X0_GPIO_WRITE(sc, A37X0_GPIO_OUT_EN(pin), reg); 171 172 return (0); 173 } 174 175 static int 176 a37x0_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *val) 177 { 178 struct a37x0_gpio_softc *sc; 179 uint32_t reg; 180 181 sc = device_get_softc(dev); 182 if (pin >= sc->sc_npins) 183 return (EINVAL); 184 185 reg = A37X0_GPIO_READ(sc, A37X0_GPIO_OUT_EN(pin)); 186 if ((reg & A37X0_GPIO_BIT(pin)) != 0) 187 reg = A37X0_GPIO_READ(sc, A37X0_GPIO_OUTPUT(pin)); 188 else 189 reg = A37X0_GPIO_READ(sc, A37X0_GPIO_INPUT(pin)); 190 *val = ((reg & A37X0_GPIO_BIT(pin)) != 0) ? 1 : 0; 191 192 return (0); 193 } 194 195 static int 196 a37x0_gpio_pin_set(device_t dev, uint32_t pin, unsigned int val) 197 { 198 struct a37x0_gpio_softc *sc; 199 uint32_t reg; 200 201 sc = device_get_softc(dev); 202 if (pin >= sc->sc_npins) 203 return (EINVAL); 204 205 reg = A37X0_GPIO_READ(sc, A37X0_GPIO_OUTPUT(pin)); 206 if (val != 0) 207 reg |= A37X0_GPIO_BIT(pin); 208 else 209 reg &= ~A37X0_GPIO_BIT(pin); 210 A37X0_GPIO_WRITE(sc, A37X0_GPIO_OUTPUT(pin), reg); 211 212 return (0); 213 } 214 215 static int 216 a37x0_gpio_pin_toggle(device_t dev, uint32_t pin) 217 { 218 struct a37x0_gpio_softc *sc; 219 uint32_t reg; 220 221 sc = device_get_softc(dev); 222 if (pin >= sc->sc_npins) 223 return (EINVAL); 224 225 reg = A37X0_GPIO_READ(sc, A37X0_GPIO_OUT_EN(pin)); 226 if ((reg & A37X0_GPIO_BIT(pin)) == 0) 227 return (EINVAL); 228 reg = A37X0_GPIO_READ(sc, A37X0_GPIO_OUTPUT(pin)); 229 reg ^= A37X0_GPIO_BIT(pin); 230 A37X0_GPIO_WRITE(sc, A37X0_GPIO_OUTPUT(pin), reg); 231 232 return (0); 233 } 234 235 static int 236 a37x0_gpio_probe(device_t dev) 237 { 238 const char *desc; 239 struct a37x0_gpio_softc *sc; 240 241 if (!OF_hasprop(ofw_bus_get_node(dev), "gpio-controller")) 242 return (ENXIO); 243 244 sc = device_get_softc(dev); 245 sc->sc_type = ofw_bus_search_compatible( 246 device_get_parent(dev), compat_data)->ocd_data; 247 switch (sc->sc_type) { 248 case A37X0_NB_GPIO: 249 sc->sc_max_pins = 36; 250 desc = "Armada 37x0 North Bridge GPIO Controller"; 251 break; 252 case A37X0_SB_GPIO: 253 sc->sc_max_pins = 30; 254 desc = "Armada 37x0 South Bridge GPIO Controller"; 255 break; 256 default: 257 return (ENXIO); 258 } 259 device_set_desc(dev, desc); 260 261 return (BUS_PROBE_DEFAULT); 262 } 263 264 static int 265 a37x0_gpio_attach(device_t dev) 266 { 267 int err, ncells; 268 pcell_t *ranges; 269 struct a37x0_gpio_softc *sc; 270 271 sc = device_get_softc(dev); 272 273 err = syscon_get_handle_default(dev, &sc->syscon); 274 if (err != 0) { 275 device_printf(dev, "Cannot get syscon handle from parent\n"); 276 return (ENXIO); 277 } 278 279 /* Read and verify the "gpio-ranges" property. */ 280 ncells = OF_getencprop_alloc(ofw_bus_get_node(dev), "gpio-ranges", 281 (void **)&ranges); 282 if (ncells == -1) 283 return (ENXIO); 284 if (ncells != sizeof(*ranges) * 4 || ranges[1] != 0 || ranges[2] != 0) { 285 OF_prop_free(ranges); 286 return (ENXIO); 287 } 288 sc->sc_npins = ranges[3]; 289 OF_prop_free(ranges); 290 291 /* Check the number of pins in the DTS vs HW capabilities. */ 292 if (sc->sc_npins > sc->sc_max_pins) 293 return (ENXIO); 294 295 sc->sc_busdev = gpiobus_attach_bus(dev); 296 if (sc->sc_busdev == NULL) 297 return (ENXIO); 298 299 return (0); 300 } 301 302 static int 303 a37x0_gpio_detach(device_t dev) 304 { 305 306 return (EBUSY); 307 } 308 309 static device_method_t a37x0_gpio_methods[] = { 310 /* Device interface */ 311 DEVMETHOD(device_probe, a37x0_gpio_probe), 312 DEVMETHOD(device_attach, a37x0_gpio_attach), 313 DEVMETHOD(device_detach, a37x0_gpio_detach), 314 315 /* GPIO interface */ 316 DEVMETHOD(gpio_get_bus, a37x0_gpio_get_bus), 317 DEVMETHOD(gpio_pin_max, a37x0_gpio_pin_max), 318 DEVMETHOD(gpio_pin_getname, a37x0_gpio_pin_getname), 319 DEVMETHOD(gpio_pin_getcaps, a37x0_gpio_pin_getcaps), 320 DEVMETHOD(gpio_pin_getflags, a37x0_gpio_pin_getflags), 321 DEVMETHOD(gpio_pin_setflags, a37x0_gpio_pin_setflags), 322 DEVMETHOD(gpio_pin_get, a37x0_gpio_pin_get), 323 DEVMETHOD(gpio_pin_set, a37x0_gpio_pin_set), 324 DEVMETHOD(gpio_pin_toggle, a37x0_gpio_pin_toggle), 325 326 /* ofw_bus interface */ 327 DEVMETHOD(ofw_bus_get_node, a37x0_gpio_get_node), 328 329 DEVMETHOD_END 330 }; 331 332 static driver_t a37x0_gpio_driver = { 333 "gpio", 334 a37x0_gpio_methods, 335 sizeof(struct a37x0_gpio_softc), 336 }; 337 338 EARLY_DRIVER_MODULE(a37x0_gpio, simple_mfd, a37x0_gpio_driver, 0, 0, 339 BUS_PASS_INTERRUPT + BUS_PASS_ORDER_LAST); 340