100ad2ec8SZbigniew Bodek /*-
200ad2ec8SZbigniew Bodek * Copyright (c) 2015 Semihalf.
300ad2ec8SZbigniew Bodek * Copyright (c) 2015 Stormshield.
400ad2ec8SZbigniew Bodek * All rights reserved.
500ad2ec8SZbigniew Bodek *
600ad2ec8SZbigniew Bodek * Redistribution and use in source and binary forms, with or without
700ad2ec8SZbigniew Bodek * modification, are permitted provided that the following conditions
800ad2ec8SZbigniew Bodek * are met:
900ad2ec8SZbigniew Bodek * 1. Redistributions of source code must retain the above copyright
1000ad2ec8SZbigniew Bodek * notice, this list of conditions and the following disclaimer.
1100ad2ec8SZbigniew Bodek * 2. Redistributions in binary form must reproduce the above copyright
1200ad2ec8SZbigniew Bodek * notice, this list of conditions and the following disclaimer in the
1300ad2ec8SZbigniew Bodek * documentation and/or other materials provided with the distribution.
1400ad2ec8SZbigniew Bodek *
1500ad2ec8SZbigniew Bodek * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
1600ad2ec8SZbigniew Bodek * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
1700ad2ec8SZbigniew Bodek * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
1800ad2ec8SZbigniew Bodek * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
1900ad2ec8SZbigniew Bodek * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
2000ad2ec8SZbigniew Bodek * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
2100ad2ec8SZbigniew Bodek * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
2200ad2ec8SZbigniew Bodek * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
2300ad2ec8SZbigniew Bodek * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
2400ad2ec8SZbigniew Bodek * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
2500ad2ec8SZbigniew Bodek * SUCH DAMAGE.
2600ad2ec8SZbigniew Bodek */
27*fdafd315SWarner Losh
2800ad2ec8SZbigniew Bodek #include <sys/param.h>
2900ad2ec8SZbigniew Bodek #include <sys/systm.h>
3000ad2ec8SZbigniew Bodek #include <sys/bus.h>
3100ad2ec8SZbigniew Bodek #include <sys/smp.h>
3200ad2ec8SZbigniew Bodek
3300ad2ec8SZbigniew Bodek #include <machine/smp.h>
3400ad2ec8SZbigniew Bodek #include <machine/fdt.h>
3500ad2ec8SZbigniew Bodek #include <machine/intr.h>
36ccc1e6ebSMarcin Wojtas #include <machine/platformvar.h>
3700ad2ec8SZbigniew Bodek
3800ad2ec8SZbigniew Bodek #include <dev/ofw/ofw_bus.h>
3900ad2ec8SZbigniew Bodek #include <dev/ofw/ofw_bus_subr.h>
4000ad2ec8SZbigniew Bodek
4100ad2ec8SZbigniew Bodek #include <arm/mv/mvreg.h>
4200ad2ec8SZbigniew Bodek
43ec22b42aSZbigniew Bodek #include "pmsu.h"
44ec22b42aSZbigniew Bodek
45ccc1e6ebSMarcin Wojtas static int cpu_reset_deassert(void);
46ccc1e6ebSMarcin Wojtas void mv_a38x_platform_mp_setmaxid(platform_t plate);
47ccc1e6ebSMarcin Wojtas void mv_a38x_platform_mp_start_ap(platform_t plate);
4800ad2ec8SZbigniew Bodek
49ccc1e6ebSMarcin Wojtas static int
cpu_reset_deassert(void)5000ad2ec8SZbigniew Bodek cpu_reset_deassert(void)
5100ad2ec8SZbigniew Bodek {
5200ad2ec8SZbigniew Bodek bus_space_handle_t vaddr;
5300ad2ec8SZbigniew Bodek uint32_t reg;
5400ad2ec8SZbigniew Bodek int rv;
5500ad2ec8SZbigniew Bodek
5600ad2ec8SZbigniew Bodek rv = bus_space_map(fdtbus_bs_tag, (bus_addr_t)MV_CPU_RESET_BASE,
5700ad2ec8SZbigniew Bodek MV_CPU_RESET_REGS_LEN, 0, &vaddr);
5800ad2ec8SZbigniew Bodek if (rv != 0)
5900ad2ec8SZbigniew Bodek return (rv);
6000ad2ec8SZbigniew Bodek
6100ad2ec8SZbigniew Bodek /* CPU1 is held at reset by default - clear assert bit to release it */
6200ad2ec8SZbigniew Bodek reg = bus_space_read_4(fdtbus_bs_tag, vaddr, CPU_RESET_OFFSET(1));
6300ad2ec8SZbigniew Bodek reg &= ~CPU_RESET_ASSERT;
6400ad2ec8SZbigniew Bodek
6500ad2ec8SZbigniew Bodek bus_space_write_4(fdtbus_bs_tag, vaddr, CPU_RESET_OFFSET(1), reg);
6600ad2ec8SZbigniew Bodek
6700ad2ec8SZbigniew Bodek bus_space_unmap(fdtbus_bs_tag, vaddr, MV_CPU_RESET_REGS_LEN);
6800ad2ec8SZbigniew Bodek
6900ad2ec8SZbigniew Bodek return (0);
7000ad2ec8SZbigniew Bodek }
7100ad2ec8SZbigniew Bodek
7200ad2ec8SZbigniew Bodek static int
platform_cnt_cpus(void)7300ad2ec8SZbigniew Bodek platform_cnt_cpus(void)
7400ad2ec8SZbigniew Bodek {
7500ad2ec8SZbigniew Bodek bus_space_handle_t vaddr_scu;
7600ad2ec8SZbigniew Bodek phandle_t cpus_node, child;
7700ad2ec8SZbigniew Bodek char device_type[16];
7800ad2ec8SZbigniew Bodek int fdt_cpu_count = 0;
7900ad2ec8SZbigniew Bodek int reg_cpu_count = 0;
8000ad2ec8SZbigniew Bodek uint32_t val;
8100ad2ec8SZbigniew Bodek int rv;
8200ad2ec8SZbigniew Bodek
8300ad2ec8SZbigniew Bodek cpus_node = OF_finddevice("/cpus");
8400ad2ec8SZbigniew Bodek if (cpus_node == -1) {
8500ad2ec8SZbigniew Bodek /* Default is one core */
8600ad2ec8SZbigniew Bodek mp_ncpus = 1;
8700ad2ec8SZbigniew Bodek return (0);
8800ad2ec8SZbigniew Bodek }
8900ad2ec8SZbigniew Bodek
9000ad2ec8SZbigniew Bodek /* Get number of 'cpu' nodes from FDT */
9100ad2ec8SZbigniew Bodek for (child = OF_child(cpus_node); child != 0; child = OF_peer(child)) {
9200ad2ec8SZbigniew Bodek /* Check if child is a CPU */
9300ad2ec8SZbigniew Bodek memset(device_type, 0, sizeof(device_type));
9400ad2ec8SZbigniew Bodek rv = OF_getprop(child, "device_type", device_type,
9500ad2ec8SZbigniew Bodek sizeof(device_type) - 1);
9600ad2ec8SZbigniew Bodek if (rv < 0)
9700ad2ec8SZbigniew Bodek continue;
9800ad2ec8SZbigniew Bodek if (strcmp(device_type, "cpu") != 0)
9900ad2ec8SZbigniew Bodek continue;
10000ad2ec8SZbigniew Bodek
10100ad2ec8SZbigniew Bodek fdt_cpu_count++;
10200ad2ec8SZbigniew Bodek }
10300ad2ec8SZbigniew Bodek
10400ad2ec8SZbigniew Bodek /* Get number of CPU cores from SCU register to cross-check with FDT */
10500ad2ec8SZbigniew Bodek rv = bus_space_map(fdtbus_bs_tag, (bus_addr_t)MV_SCU_BASE,
10600ad2ec8SZbigniew Bodek MV_SCU_REGS_LEN, 0, &vaddr_scu);
10700ad2ec8SZbigniew Bodek if (rv != 0) {
10800ad2ec8SZbigniew Bodek /* Default is one core */
10900ad2ec8SZbigniew Bodek mp_ncpus = 1;
11000ad2ec8SZbigniew Bodek return (0);
11100ad2ec8SZbigniew Bodek }
11200ad2ec8SZbigniew Bodek
11300ad2ec8SZbigniew Bodek val = bus_space_read_4(fdtbus_bs_tag, vaddr_scu, MV_SCU_REG_CONFIG);
11400ad2ec8SZbigniew Bodek bus_space_unmap(fdtbus_bs_tag, vaddr_scu, MV_SCU_REGS_LEN);
11500ad2ec8SZbigniew Bodek reg_cpu_count = (val & SCU_CFG_REG_NCPU_MASK) + 1;
11600ad2ec8SZbigniew Bodek
11700ad2ec8SZbigniew Bodek /* Set mp_ncpus to number of cpus in FDT unless SOC contains only one */
11800ad2ec8SZbigniew Bodek mp_ncpus = min(reg_cpu_count, fdt_cpu_count);
11900ad2ec8SZbigniew Bodek /* mp_ncpus must be at least 1 */
12000ad2ec8SZbigniew Bodek mp_ncpus = max(1, mp_ncpus);
12100ad2ec8SZbigniew Bodek
12200ad2ec8SZbigniew Bodek return (mp_ncpus);
12300ad2ec8SZbigniew Bodek }
12400ad2ec8SZbigniew Bodek
12500ad2ec8SZbigniew Bodek void
mv_a38x_platform_mp_setmaxid(platform_t plate)126ccc1e6ebSMarcin Wojtas mv_a38x_platform_mp_setmaxid(platform_t plate)
12700ad2ec8SZbigniew Bodek {
12800ad2ec8SZbigniew Bodek
12900ad2ec8SZbigniew Bodek /* Armada38x family supports maximum 2 cores */
13000ad2ec8SZbigniew Bodek mp_ncpus = platform_cnt_cpus();
13122a752b4SWojciech Macek mp_maxid = mp_ncpus - 1;
13200ad2ec8SZbigniew Bodek }
13300ad2ec8SZbigniew Bodek
13400ad2ec8SZbigniew Bodek void
mv_a38x_platform_mp_start_ap(platform_t plate)135ccc1e6ebSMarcin Wojtas mv_a38x_platform_mp_start_ap(platform_t plate)
13600ad2ec8SZbigniew Bodek {
13700ad2ec8SZbigniew Bodek int rv;
13800ad2ec8SZbigniew Bodek
13900ad2ec8SZbigniew Bodek /* Write secondary entry address to PMSU register */
14000ad2ec8SZbigniew Bodek rv = pmsu_boot_secondary_cpu();
14100ad2ec8SZbigniew Bodek if (rv != 0)
14200ad2ec8SZbigniew Bodek return;
14300ad2ec8SZbigniew Bodek
14400ad2ec8SZbigniew Bodek /* Release CPU1 from reset */
14500ad2ec8SZbigniew Bodek cpu_reset_deassert();
14600ad2ec8SZbigniew Bodek }
147