1 /*- 2 * Copyright (c) 2015 Semihalf. 3 * Copyright (c) 2015 Stormshield. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include <sys/param.h> 31 #include <sys/systm.h> 32 #include <sys/bus.h> 33 #include <sys/smp.h> 34 35 #include <machine/smp.h> 36 #include <machine/fdt.h> 37 #include <machine/intr.h> 38 39 #include <dev/ofw/ofw_bus.h> 40 #include <dev/ofw/ofw_bus_subr.h> 41 42 #include <arm/mv/mvreg.h> 43 44 #include "pmsu.h" 45 46 int cpu_reset_deassert(void); 47 48 int 49 cpu_reset_deassert(void) 50 { 51 bus_space_handle_t vaddr; 52 uint32_t reg; 53 int rv; 54 55 rv = bus_space_map(fdtbus_bs_tag, (bus_addr_t)MV_CPU_RESET_BASE, 56 MV_CPU_RESET_REGS_LEN, 0, &vaddr); 57 if (rv != 0) 58 return (rv); 59 60 /* CPU1 is held at reset by default - clear assert bit to release it */ 61 reg = bus_space_read_4(fdtbus_bs_tag, vaddr, CPU_RESET_OFFSET(1)); 62 reg &= ~CPU_RESET_ASSERT; 63 64 bus_space_write_4(fdtbus_bs_tag, vaddr, CPU_RESET_OFFSET(1), reg); 65 66 bus_space_unmap(fdtbus_bs_tag, vaddr, MV_CPU_RESET_REGS_LEN); 67 68 return (0); 69 } 70 71 static int 72 platform_cnt_cpus(void) 73 { 74 bus_space_handle_t vaddr_scu; 75 phandle_t cpus_node, child; 76 char device_type[16]; 77 int fdt_cpu_count = 0; 78 int reg_cpu_count = 0; 79 uint32_t val; 80 int rv; 81 82 cpus_node = OF_finddevice("/cpus"); 83 if (cpus_node == -1) { 84 /* Default is one core */ 85 mp_ncpus = 1; 86 return (0); 87 } 88 89 /* Get number of 'cpu' nodes from FDT */ 90 for (child = OF_child(cpus_node); child != 0; child = OF_peer(child)) { 91 /* Check if child is a CPU */ 92 memset(device_type, 0, sizeof(device_type)); 93 rv = OF_getprop(child, "device_type", device_type, 94 sizeof(device_type) - 1); 95 if (rv < 0) 96 continue; 97 if (strcmp(device_type, "cpu") != 0) 98 continue; 99 100 fdt_cpu_count++; 101 } 102 103 /* Get number of CPU cores from SCU register to cross-check with FDT */ 104 rv = bus_space_map(fdtbus_bs_tag, (bus_addr_t)MV_SCU_BASE, 105 MV_SCU_REGS_LEN, 0, &vaddr_scu); 106 if (rv != 0) { 107 /* Default is one core */ 108 mp_ncpus = 1; 109 return (0); 110 } 111 112 val = bus_space_read_4(fdtbus_bs_tag, vaddr_scu, MV_SCU_REG_CONFIG); 113 bus_space_unmap(fdtbus_bs_tag, vaddr_scu, MV_SCU_REGS_LEN); 114 reg_cpu_count = (val & SCU_CFG_REG_NCPU_MASK) + 1; 115 116 /* Set mp_ncpus to number of cpus in FDT unless SOC contains only one */ 117 mp_ncpus = min(reg_cpu_count, fdt_cpu_count); 118 /* mp_ncpus must be at least 1 */ 119 mp_ncpus = max(1, mp_ncpus); 120 121 return (mp_ncpus); 122 } 123 124 void 125 platform_mp_setmaxid(void) 126 { 127 128 /* Armada38x family supports maximum 2 cores */ 129 mp_ncpus = platform_cnt_cpus(); 130 mp_maxid = mp_ncpus - 1; 131 } 132 133 void 134 platform_mp_start_ap(void) 135 { 136 int rv; 137 138 /* Write secondary entry address to PMSU register */ 139 rv = pmsu_boot_secondary_cpu(); 140 if (rv != 0) 141 return; 142 143 /* Release CPU1 from reset */ 144 cpu_reset_deassert(); 145 } 146