1 /*- 2 * Copyright (c) 2015 Semihalf. 3 * Copyright (c) 2015 Stormshield. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 #include <sys/param.h> 32 #include <sys/bus.h> 33 #include <sys/lock.h> 34 #include <sys/time.h> 35 #include <sys/proc.h> 36 #include <sys/conf.h> 37 #include <sys/rman.h> 38 #include <sys/clock.h> 39 #include <sys/systm.h> 40 #include <sys/mutex.h> 41 #include <sys/types.h> 42 #include <sys/kernel.h> 43 #include <sys/module.h> 44 #include <sys/resource.h> 45 46 #include <machine/bus.h> 47 #include <machine/resource.h> 48 49 #include <dev/ofw/ofw_bus.h> 50 #include <dev/ofw/ofw_bus_subr.h> 51 52 #include "clock_if.h" 53 54 #define RTC_RES_US 1000000 55 #define HALF_OF_SEC_NS 500000000 56 57 #define RTC_STATUS 0x0 58 #define RTC_TIME 0xC 59 #define RTC_TEST_CONFIG 0x1C 60 #define RTC_IRQ_1_CONFIG 0x4 61 #define RTC_IRQ_2_CONFIG 0x8 62 #define RTC_ALARM_1 0x10 63 #define RTC_ALARM_2 0x14 64 #define RTC_CLOCK_CORR 0x18 65 66 #define RTC_NOMINAL_TIMING 0x2000 67 #define RTC_NOMINAL_TIMING_MASK 0x7fff 68 69 #define RTC_STATUS_ALARM1_MASK 0x1 70 #define RTC_STATUS_ALARM2_MASK 0x2 71 72 #define MV_RTC_LOCK(sc) mtx_lock_spin(&(sc)->mutex) 73 #define MV_RTC_UNLOCK(sc) mtx_unlock_spin(&(sc)->mutex) 74 75 #define RTC_BRIDGE_TIMING_CTRL 0x0 76 #define RTC_WRCLK_PERIOD_SHIFT 0 77 #define RTC_WRCLK_PERIOD_MASK 0x00000003FF 78 #define RTC_WRCLK_PERIOD_MAX 0x3FF 79 #define RTC_READ_OUTPUT_DELAY_SHIFT 26 80 #define RTC_READ_OUTPUT_DELAY_MASK 0x007C000000 81 #define RTC_READ_OUTPUT_DELAY_MAX 0x1F 82 83 #define RTC_RES 0 84 #define RTC_SOC_RES 1 85 86 87 static struct resource_spec res_spec[] = { 88 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 89 { SYS_RES_MEMORY, 1, RF_ACTIVE }, 90 { -1, 0 } 91 }; 92 93 struct mv_rtc_softc { 94 device_t dev; 95 struct resource *res[2]; 96 struct mtx mutex; 97 }; 98 99 static int mv_rtc_probe(device_t dev); 100 static int mv_rtc_attach(device_t dev); 101 static int mv_rtc_detach(device_t dev); 102 103 static int mv_rtc_gettime(device_t dev, struct timespec *ts); 104 static int mv_rtc_settime(device_t dev, struct timespec *ts); 105 106 static inline uint32_t mv_rtc_reg_read(struct mv_rtc_softc *sc, 107 bus_size_t off); 108 static inline int mv_rtc_reg_write(struct mv_rtc_softc *sc, bus_size_t off, 109 uint32_t val); 110 static inline void mv_rtc_configure_bus(struct mv_rtc_softc *sc); 111 112 static device_method_t mv_rtc_methods[] = { 113 DEVMETHOD(device_probe, mv_rtc_probe), 114 DEVMETHOD(device_attach, mv_rtc_attach), 115 DEVMETHOD(device_detach, mv_rtc_detach), 116 117 DEVMETHOD(clock_gettime, mv_rtc_gettime), 118 DEVMETHOD(clock_settime, mv_rtc_settime), 119 120 { 0, 0 }, 121 }; 122 123 static driver_t mv_rtc_driver = { 124 "rtc", 125 mv_rtc_methods, 126 sizeof(struct mv_rtc_softc), 127 }; 128 129 static struct ofw_compat_data mv_rtc_compat[] = { 130 {"marvell,armada-380-rtc", true}, 131 {"marvell,armada-8k-rtc", true}, 132 {NULL, false}, 133 }; 134 135 static devclass_t mv_rtc_devclass; 136 137 DRIVER_MODULE(a38x_rtc, simplebus, mv_rtc_driver, mv_rtc_devclass, 0, 0); 138 139 static void 140 mv_rtc_reset(device_t dev) 141 { 142 struct mv_rtc_softc *sc; 143 144 sc = device_get_softc(dev); 145 146 /* Reset Test register */ 147 mv_rtc_reg_write(sc, RTC_TEST_CONFIG, 0); 148 DELAY(500000); 149 150 /* Reset Time register */ 151 mv_rtc_reg_write(sc, RTC_TIME, 0); 152 DELAY(62); 153 154 /* Reset Status register */ 155 mv_rtc_reg_write(sc, RTC_STATUS, (RTC_STATUS_ALARM1_MASK | RTC_STATUS_ALARM2_MASK)); 156 DELAY(62); 157 158 /* Turn off Int1 and Int2 sources & clear the Alarm count */ 159 mv_rtc_reg_write(sc, RTC_IRQ_1_CONFIG, 0); 160 mv_rtc_reg_write(sc, RTC_IRQ_2_CONFIG, 0); 161 mv_rtc_reg_write(sc, RTC_ALARM_1, 0); 162 mv_rtc_reg_write(sc, RTC_ALARM_2, 0); 163 164 /* Setup nominal register access timing */ 165 mv_rtc_reg_write(sc, RTC_CLOCK_CORR, RTC_NOMINAL_TIMING); 166 167 /* Reset Time register */ 168 mv_rtc_reg_write(sc, RTC_TIME, 0); 169 DELAY(10); 170 171 /* Reset Status register */ 172 mv_rtc_reg_write(sc, RTC_STATUS, (RTC_STATUS_ALARM1_MASK | RTC_STATUS_ALARM2_MASK)); 173 DELAY(50); 174 } 175 176 static int 177 mv_rtc_probe(device_t dev) 178 { 179 180 if (!ofw_bus_status_okay(dev)) 181 return (ENXIO); 182 183 if (!ofw_bus_search_compatible(dev, mv_rtc_compat)->ocd_data) 184 return (ENXIO); 185 186 device_set_desc(dev, "Marvell Integrated RTC"); 187 188 return (BUS_PROBE_DEFAULT); 189 } 190 191 static int 192 mv_rtc_attach(device_t dev) 193 { 194 struct mv_rtc_softc *sc; 195 int unit, ret; 196 197 unit = device_get_unit(dev); 198 199 sc = device_get_softc(dev); 200 sc->dev = dev; 201 202 clock_register(dev, RTC_RES_US); 203 204 mtx_init(&sc->mutex, device_get_nameunit(dev), NULL, MTX_SPIN); 205 206 ret = bus_alloc_resources(dev, res_spec, sc->res); 207 208 if (ret != 0) { 209 device_printf(dev, "could not allocate resources\n"); 210 mtx_destroy(&sc->mutex); 211 return (ENXIO); 212 } 213 mv_rtc_configure_bus(sc); 214 215 return (0); 216 } 217 218 static int 219 mv_rtc_detach(device_t dev) 220 { 221 struct mv_rtc_softc *sc; 222 223 sc = device_get_softc(dev); 224 225 mtx_destroy(&sc->mutex); 226 227 bus_release_resources(dev, res_spec, sc->res); 228 229 return (0); 230 } 231 232 static int 233 mv_rtc_gettime(device_t dev, struct timespec *ts) 234 { 235 struct mv_rtc_softc *sc; 236 uint32_t val, val_check; 237 238 sc = device_get_softc(dev); 239 240 MV_RTC_LOCK(sc); 241 /* 242 * According to HW Errata if more than one second between 243 * two time reads is detected, then read once again 244 */ 245 val = mv_rtc_reg_read(sc, RTC_TIME); 246 val_check = mv_rtc_reg_read(sc, RTC_TIME); 247 if (val_check - val > 1) 248 val_check = mv_rtc_reg_read(sc, RTC_TIME); 249 250 MV_RTC_UNLOCK(sc); 251 252 ts->tv_sec = val_check; 253 /* RTC resolution is 1 sec */ 254 ts->tv_nsec = 0; 255 256 return (0); 257 } 258 259 static int 260 mv_rtc_settime(device_t dev, struct timespec *ts) 261 { 262 struct mv_rtc_softc *sc; 263 264 sc = device_get_softc(dev); 265 266 /* RTC resolution is 1 sec */ 267 if (ts->tv_nsec >= HALF_OF_SEC_NS) 268 ts->tv_sec++; 269 ts->tv_nsec = 0; 270 271 MV_RTC_LOCK(sc); 272 273 if ((mv_rtc_reg_read(sc, RTC_CLOCK_CORR) & RTC_NOMINAL_TIMING_MASK) != 274 RTC_NOMINAL_TIMING) { 275 /* RTC was not resetted yet */ 276 mv_rtc_reset(dev); 277 } 278 279 /* 280 * According to errata FE-3124064, Write to RTC TIME register 281 * may fail. As a workaround, before writing to RTC TIME register, 282 * issue a dummy write of 0x0 twice to RTC Status register. 283 */ 284 mv_rtc_reg_write(sc, RTC_STATUS, 0x0); 285 mv_rtc_reg_write(sc, RTC_STATUS, 0x0); 286 mv_rtc_reg_write(sc, RTC_TIME, ts->tv_sec); 287 288 MV_RTC_UNLOCK(sc); 289 290 return (0); 291 } 292 293 static inline uint32_t 294 mv_rtc_reg_read(struct mv_rtc_softc *sc, bus_size_t off) 295 { 296 297 return (bus_read_4(sc->res[RTC_RES], off)); 298 } 299 300 /* 301 * According to the datasheet, the OS should wait 5us after every 302 * register write to the RTC hard macro so that the required update 303 * can occur without holding off the system bus 304 */ 305 static inline int 306 mv_rtc_reg_write(struct mv_rtc_softc *sc, bus_size_t off, uint32_t val) 307 { 308 309 bus_write_4(sc->res[RTC_RES], off, val); 310 DELAY(5); 311 312 return (0); 313 } 314 315 static inline void 316 mv_rtc_configure_bus(struct mv_rtc_softc *sc) 317 { 318 int val; 319 320 val = bus_read_4(sc->res[RTC_SOC_RES], RTC_BRIDGE_TIMING_CTRL); 321 val &= ~(RTC_WRCLK_PERIOD_MASK | RTC_READ_OUTPUT_DELAY_MASK); 322 val |= RTC_WRCLK_PERIOD_MAX << RTC_WRCLK_PERIOD_SHIFT; 323 val |= RTC_READ_OUTPUT_DELAY_MAX << RTC_READ_OUTPUT_DELAY_SHIFT; 324 bus_write_4(sc->res[RTC_SOC_RES], RTC_BRIDGE_TIMING_CTRL, val); 325 } 326