116694521SOleksandr Tymoshenko /*- 216694521SOleksandr Tymoshenko * Copyright (c) 2011 Semihalf. 316694521SOleksandr Tymoshenko * All rights reserved. 416694521SOleksandr Tymoshenko * 516694521SOleksandr Tymoshenko * Redistribution and use in source and binary forms, with or without 616694521SOleksandr Tymoshenko * modification, are permitted provided that the following conditions 716694521SOleksandr Tymoshenko * are met: 816694521SOleksandr Tymoshenko * 1. Redistributions of source code must retain the above copyright 916694521SOleksandr Tymoshenko * notice, this list of conditions and the following disclaimer. 1016694521SOleksandr Tymoshenko * 2. Redistributions in binary form must reproduce the above copyright 1116694521SOleksandr Tymoshenko * notice, this list of conditions and the following disclaimer in the 1216694521SOleksandr Tymoshenko * documentation and/or other materials provided with the distribution. 1316694521SOleksandr Tymoshenko * 1416694521SOleksandr Tymoshenko * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 1516694521SOleksandr Tymoshenko * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 1616694521SOleksandr Tymoshenko * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 1716694521SOleksandr Tymoshenko * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 1816694521SOleksandr Tymoshenko * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 1916694521SOleksandr Tymoshenko * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 2016694521SOleksandr Tymoshenko * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 2116694521SOleksandr Tymoshenko * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 2216694521SOleksandr Tymoshenko * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 2316694521SOleksandr Tymoshenko * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 2416694521SOleksandr Tymoshenko * SUCH DAMAGE. 2516694521SOleksandr Tymoshenko * 2616694521SOleksandr Tymoshenko * From: FreeBSD: src/sys/arm/mv/kirkwood/sheevaplug.c,v 1.2 2010/06/13 13:28:53 2716694521SOleksandr Tymoshenko */ 2816694521SOleksandr Tymoshenko 2916694521SOleksandr Tymoshenko #include <sys/cdefs.h> 3016694521SOleksandr Tymoshenko __FBSDID("$FreeBSD$"); 3116694521SOleksandr Tymoshenko 3216694521SOleksandr Tymoshenko #include <sys/param.h> 3316694521SOleksandr Tymoshenko #include <sys/systm.h> 3416694521SOleksandr Tymoshenko #include <sys/bus.h> 3516694521SOleksandr Tymoshenko 3616694521SOleksandr Tymoshenko #include <machine/bus.h> 37d65cdf4bSGrzegorz Bernacki #include <machine/armreg.h> 3816694521SOleksandr Tymoshenko 393a1f2172SGrzegorz Bernacki #include <arm/mv/mvwin.h> 4016694521SOleksandr Tymoshenko #include <arm/mv/mvreg.h> 4116694521SOleksandr Tymoshenko #include <arm/mv/mvvar.h> 4216694521SOleksandr Tymoshenko 4316694521SOleksandr Tymoshenko #include <dev/fdt/fdt_common.h> 4416694521SOleksandr Tymoshenko #include <dev/ofw/openfirm.h> 4516694521SOleksandr Tymoshenko 4616694521SOleksandr Tymoshenko #include <machine/fdt.h> 4716694521SOleksandr Tymoshenko 48d65cdf4bSGrzegorz Bernacki #define CPU_FREQ_FIELD(sar) (((0x01 & (sar >> 52)) << 3) | \ 49d65cdf4bSGrzegorz Bernacki (0x07 & (sar >> 21))) 50d65cdf4bSGrzegorz Bernacki #define FAB_FREQ_FIELD(sar) (((0x01 & (sar >> 51)) << 4) | \ 51d65cdf4bSGrzegorz Bernacki (0x0F & (sar >> 24))) 52d65cdf4bSGrzegorz Bernacki 53d65cdf4bSGrzegorz Bernacki static uint32_t count_l2clk(void); 545c39c3ffSGrzegorz Bernacki void armadaxp_l2_init(void); 555c39c3ffSGrzegorz Bernacki void armadaxp_init_coher_fabric(void); 565c39c3ffSGrzegorz Bernacki int platform_get_ncpus(void); 57d65cdf4bSGrzegorz Bernacki 583a1f2172SGrzegorz Bernacki #define ARMADAXP_L2_BASE (MV_BASE + 0x8000) 593a1f2172SGrzegorz Bernacki #define ARMADAXP_L2_CTRL 0x100 603a1f2172SGrzegorz Bernacki #define L2_ENABLE (1 << 0) 613a1f2172SGrzegorz Bernacki #define ARMADAXP_L2_AUX_CTRL 0x104 623a1f2172SGrzegorz Bernacki #define L2_WBWT_MODE_MASK (3 << 0) 633a1f2172SGrzegorz Bernacki #define L2_WBWT_MODE_PAGE 0 643a1f2172SGrzegorz Bernacki #define L2_WBWT_MODE_WB 1 653a1f2172SGrzegorz Bernacki #define L2_WBWT_MODE_WT 2 663a1f2172SGrzegorz Bernacki #define L2_REP_STRAT_MASK (3 << 27) 673a1f2172SGrzegorz Bernacki #define L2_REP_STRAT_LSFR (1 << 27) 683a1f2172SGrzegorz Bernacki #define L2_REP_STRAT_SEMIPLRU (3 << 27) 693a1f2172SGrzegorz Bernacki 703a1f2172SGrzegorz Bernacki #define ARMADAXP_L2_CNTR_CTRL 0x200 713a1f2172SGrzegorz Bernacki #define ARMADAXP_L2_CNTR_CONF(x) (0x204 + (x) * 0xc) 723a1f2172SGrzegorz Bernacki #define ARMADAXP_L2_CNTR2_VAL_LOW (0x208 + (x) * 0xc) 733a1f2172SGrzegorz Bernacki #define ARMADAXP_L2_CNTR2_VAL_HI (0x20c + (x) * 0xc) 743a1f2172SGrzegorz Bernacki 753a1f2172SGrzegorz Bernacki #define ARMADAXP_L2_INT_CAUSE 0x220 763a1f2172SGrzegorz Bernacki 773a1f2172SGrzegorz Bernacki #define ARMADAXP_L2_SYNC_BARRIER 0x700 783a1f2172SGrzegorz Bernacki #define ARMADAXP_L2_INV_WAY 0x778 793a1f2172SGrzegorz Bernacki #define ARMADAXP_L2_CLEAN_WAY 0x7BC 803a1f2172SGrzegorz Bernacki #define ARMADAXP_L2_FLUSH_PHYS 0x7F0 813a1f2172SGrzegorz Bernacki #define ARMADAXP_L2_FLUSH_WAY 0x7FC 823a1f2172SGrzegorz Bernacki 835c39c3ffSGrzegorz Bernacki #define MV_COHERENCY_FABRIC_BASE (MV_MBUS_BRIDGE_BASE + 0x200) 845c39c3ffSGrzegorz Bernacki #define COHER_FABRIC_CTRL 0x00 855c39c3ffSGrzegorz Bernacki #define COHER_FABRIC_CONF 0x04 865c39c3ffSGrzegorz Bernacki #define COHER_FABRIC_CFU 0x28 875c39c3ffSGrzegorz Bernacki #define COHER_FABRIC_CIB_CTRL 0x80 883a1f2172SGrzegorz Bernacki 89d65cdf4bSGrzegorz Bernacki /* XXX Make gpio driver optional and remove it */ 9016694521SOleksandr Tymoshenko struct resource_spec mv_gpio_res[] = { 9116694521SOleksandr Tymoshenko { SYS_RES_MEMORY, 0, RF_ACTIVE }, 9216694521SOleksandr Tymoshenko { SYS_RES_IRQ, 0, RF_ACTIVE }, 9316694521SOleksandr Tymoshenko { -1, 0 } 9416694521SOleksandr Tymoshenko }; 9516694521SOleksandr Tymoshenko 96d65cdf4bSGrzegorz Bernacki struct vco_freq_ratio { 97d65cdf4bSGrzegorz Bernacki uint8_t vco_cpu; /* VCO to CLK0(CPU) clock ratio */ 98d65cdf4bSGrzegorz Bernacki uint8_t vco_l2c; /* VCO to NB(L2 cache) clock ratio */ 99d65cdf4bSGrzegorz Bernacki uint8_t vco_hcl; /* VCO to HCLK(DDR controller) clock ratio */ 100d65cdf4bSGrzegorz Bernacki uint8_t vco_ddr; /* VCO to DR(DDR memory) clock ratio */ 101d65cdf4bSGrzegorz Bernacki }; 102d65cdf4bSGrzegorz Bernacki 103d65cdf4bSGrzegorz Bernacki static struct vco_freq_ratio freq_conf_table[] = { 104d65cdf4bSGrzegorz Bernacki /*00*/ { 1, 1, 4, 2 }, 105d65cdf4bSGrzegorz Bernacki /*01*/ { 1, 2, 2, 2 }, 106d65cdf4bSGrzegorz Bernacki /*02*/ { 2, 2, 6, 3 }, 107d65cdf4bSGrzegorz Bernacki /*03*/ { 2, 2, 3, 3 }, 108d65cdf4bSGrzegorz Bernacki /*04*/ { 1, 2, 3, 3 }, 109d65cdf4bSGrzegorz Bernacki /*05*/ { 1, 2, 4, 2 }, 110d65cdf4bSGrzegorz Bernacki /*06*/ { 1, 1, 2, 2 }, 111d65cdf4bSGrzegorz Bernacki /*07*/ { 2, 3, 6, 6 }, 112d65cdf4bSGrzegorz Bernacki /*08*/ { 2, 3, 5, 5 }, 113d65cdf4bSGrzegorz Bernacki /*09*/ { 1, 2, 6, 3 }, 114d65cdf4bSGrzegorz Bernacki /*10*/ { 2, 4, 10, 5 }, 115d65cdf4bSGrzegorz Bernacki /*11*/ { 1, 3, 6, 6 }, 116d65cdf4bSGrzegorz Bernacki /*12*/ { 1, 2, 5, 5 }, 117d65cdf4bSGrzegorz Bernacki /*13*/ { 1, 3, 6, 3 }, 118d65cdf4bSGrzegorz Bernacki /*14*/ { 1, 2, 5, 5 }, 119d65cdf4bSGrzegorz Bernacki /*15*/ { 2, 2, 5, 5 }, 120d65cdf4bSGrzegorz Bernacki /*16*/ { 1, 1, 3, 3 }, 121d65cdf4bSGrzegorz Bernacki /*17*/ { 2, 5, 10, 10 }, 122d65cdf4bSGrzegorz Bernacki /*18*/ { 1, 3, 8, 4 }, 123d65cdf4bSGrzegorz Bernacki /*19*/ { 1, 1, 2, 1 }, 124d65cdf4bSGrzegorz Bernacki /*20*/ { 2, 3, 6, 3 }, 125d65cdf4bSGrzegorz Bernacki /*21*/ { 1, 2, 8, 4 }, 126d65cdf4bSGrzegorz Bernacki /*22*/ { 2, 5, 10, 5 } 127d65cdf4bSGrzegorz Bernacki }; 128d65cdf4bSGrzegorz Bernacki 129d65cdf4bSGrzegorz Bernacki static uint16_t cpu_clock_table[] = { 130d65cdf4bSGrzegorz Bernacki 1000, 1066, 1200, 1333, 1500, 1666, 1800, 2000, 600, 667, 800, 1600, 131d65cdf4bSGrzegorz Bernacki 2133, 2200, 2400 }; 132d65cdf4bSGrzegorz Bernacki 13316694521SOleksandr Tymoshenko uint32_t 13416694521SOleksandr Tymoshenko get_tclk(void) 13516694521SOleksandr Tymoshenko { 136d65cdf4bSGrzegorz Bernacki uint32_t cputype; 13716694521SOleksandr Tymoshenko 138d65cdf4bSGrzegorz Bernacki cputype = cpufunc_id(); 139d65cdf4bSGrzegorz Bernacki cputype &= CPU_ID_CPU_MASK; 140d65cdf4bSGrzegorz Bernacki 141d65cdf4bSGrzegorz Bernacki if (cputype == CPU_ID_MV88SV584X_V7) 142d65cdf4bSGrzegorz Bernacki return (TCLK_250MHZ); 143d65cdf4bSGrzegorz Bernacki else 14416694521SOleksandr Tymoshenko return (TCLK_200MHZ); 14516694521SOleksandr Tymoshenko } 14616694521SOleksandr Tymoshenko 147d65cdf4bSGrzegorz Bernacki static uint32_t 148d65cdf4bSGrzegorz Bernacki count_l2clk(void) 149d65cdf4bSGrzegorz Bernacki { 150d65cdf4bSGrzegorz Bernacki uint64_t sar_reg; 151d65cdf4bSGrzegorz Bernacki uint32_t freq_vco, freq_l2clk; 152d65cdf4bSGrzegorz Bernacki uint8_t sar_cpu_freq, sar_fab_freq, array_size; 153d65cdf4bSGrzegorz Bernacki 154d65cdf4bSGrzegorz Bernacki /* Get value of the SAR register and process it */ 155d65cdf4bSGrzegorz Bernacki sar_reg = get_sar_value(); 156d65cdf4bSGrzegorz Bernacki sar_cpu_freq = CPU_FREQ_FIELD(sar_reg); 157d65cdf4bSGrzegorz Bernacki sar_fab_freq = FAB_FREQ_FIELD(sar_reg); 158d65cdf4bSGrzegorz Bernacki 159d65cdf4bSGrzegorz Bernacki /* Check if CPU frequency field has correct value */ 160d65cdf4bSGrzegorz Bernacki array_size = sizeof(cpu_clock_table) / sizeof(cpu_clock_table[0]); 161d65cdf4bSGrzegorz Bernacki if (sar_cpu_freq >= array_size) 162d65cdf4bSGrzegorz Bernacki panic("Reserved value in cpu frequency configuration field: " 163d65cdf4bSGrzegorz Bernacki "%d", sar_cpu_freq); 164d65cdf4bSGrzegorz Bernacki 165d65cdf4bSGrzegorz Bernacki /* Check if fabric frequency field has correct value */ 166d65cdf4bSGrzegorz Bernacki array_size = sizeof(freq_conf_table) / sizeof(freq_conf_table[0]); 167d65cdf4bSGrzegorz Bernacki if (sar_fab_freq >= array_size) 168d65cdf4bSGrzegorz Bernacki panic("Reserved value in fabric frequency configuration field: " 169d65cdf4bSGrzegorz Bernacki "%d", sar_fab_freq); 170d65cdf4bSGrzegorz Bernacki 171d65cdf4bSGrzegorz Bernacki /* Get CPU clock frequency */ 172d65cdf4bSGrzegorz Bernacki freq_vco = cpu_clock_table[sar_cpu_freq] * 173d65cdf4bSGrzegorz Bernacki freq_conf_table[sar_fab_freq].vco_cpu; 174d65cdf4bSGrzegorz Bernacki 175d65cdf4bSGrzegorz Bernacki /* Get L2CLK clock frequency */ 176d65cdf4bSGrzegorz Bernacki freq_l2clk = freq_vco / freq_conf_table[sar_fab_freq].vco_l2c; 177d65cdf4bSGrzegorz Bernacki 178d65cdf4bSGrzegorz Bernacki /* Round L2CLK value to integer MHz */ 179d65cdf4bSGrzegorz Bernacki if (((freq_vco % freq_conf_table[sar_fab_freq].vco_l2c) * 10 / 180d65cdf4bSGrzegorz Bernacki freq_conf_table[sar_fab_freq].vco_l2c) >= 5) 181d65cdf4bSGrzegorz Bernacki freq_l2clk++; 182d65cdf4bSGrzegorz Bernacki 183d65cdf4bSGrzegorz Bernacki return (freq_l2clk * 1000000); 184d65cdf4bSGrzegorz Bernacki } 185d65cdf4bSGrzegorz Bernacki 18616694521SOleksandr Tymoshenko uint32_t 18716694521SOleksandr Tymoshenko get_l2clk(void) 18816694521SOleksandr Tymoshenko { 189d65cdf4bSGrzegorz Bernacki static uint32_t l2clk_freq = 0; 19016694521SOleksandr Tymoshenko 191d65cdf4bSGrzegorz Bernacki /* If get_l2clk is called first time get L2CLK value from register */ 192d65cdf4bSGrzegorz Bernacki if (l2clk_freq == 0) 193d65cdf4bSGrzegorz Bernacki l2clk_freq = count_l2clk(); 194d65cdf4bSGrzegorz Bernacki 195d65cdf4bSGrzegorz Bernacki return (l2clk_freq); 19616694521SOleksandr Tymoshenko } 19716694521SOleksandr Tymoshenko 1985c39c3ffSGrzegorz Bernacki static uint32_t 1995c39c3ffSGrzegorz Bernacki read_coher_fabric(uint32_t reg) 2005c39c3ffSGrzegorz Bernacki { 2015c39c3ffSGrzegorz Bernacki 2025c39c3ffSGrzegorz Bernacki return (bus_space_read_4(fdtbus_bs_tag, MV_COHERENCY_FABRIC_BASE, reg)); 2035c39c3ffSGrzegorz Bernacki } 2045c39c3ffSGrzegorz Bernacki 2055c39c3ffSGrzegorz Bernacki static void 2065c39c3ffSGrzegorz Bernacki write_coher_fabric(uint32_t reg, uint32_t val) 2075c39c3ffSGrzegorz Bernacki { 2085c39c3ffSGrzegorz Bernacki 2095c39c3ffSGrzegorz Bernacki bus_space_write_4(fdtbus_bs_tag, MV_COHERENCY_FABRIC_BASE, reg, val); 2105c39c3ffSGrzegorz Bernacki } 2115c39c3ffSGrzegorz Bernacki 2125c39c3ffSGrzegorz Bernacki int 2135c39c3ffSGrzegorz Bernacki platform_get_ncpus(void) 2145c39c3ffSGrzegorz Bernacki { 2155c39c3ffSGrzegorz Bernacki #if !defined(SMP) 2165c39c3ffSGrzegorz Bernacki return (1); 2175c39c3ffSGrzegorz Bernacki #else 2185c39c3ffSGrzegorz Bernacki return ((read_coher_fabric(COHER_FABRIC_CONF) & 0xf) + 1); 2195c39c3ffSGrzegorz Bernacki #endif 2205c39c3ffSGrzegorz Bernacki } 2215c39c3ffSGrzegorz Bernacki 2225c39c3ffSGrzegorz Bernacki void 2235c39c3ffSGrzegorz Bernacki armadaxp_init_coher_fabric(void) 2245c39c3ffSGrzegorz Bernacki { 2255c39c3ffSGrzegorz Bernacki uint32_t val, cpus, mask; 2265c39c3ffSGrzegorz Bernacki 2275c39c3ffSGrzegorz Bernacki cpus = platform_get_ncpus(); 2285c39c3ffSGrzegorz Bernacki mask = (1 << cpus) - 1; 2295c39c3ffSGrzegorz Bernacki val = read_coher_fabric(COHER_FABRIC_CTRL); 2305c39c3ffSGrzegorz Bernacki val |= (mask << 24); 2315c39c3ffSGrzegorz Bernacki write_coher_fabric(COHER_FABRIC_CTRL, val); 2325c39c3ffSGrzegorz Bernacki 2335c39c3ffSGrzegorz Bernacki val = read_coher_fabric(COHER_FABRIC_CONF); 2345c39c3ffSGrzegorz Bernacki val |= (mask << 24); 2355c39c3ffSGrzegorz Bernacki val |= (1 << 15); 2365c39c3ffSGrzegorz Bernacki write_coher_fabric(COHER_FABRIC_CONF, val); 2375c39c3ffSGrzegorz Bernacki } 2383a1f2172SGrzegorz Bernacki 2393a1f2172SGrzegorz Bernacki #define ALL_WAYS 0xffffffff 2403a1f2172SGrzegorz Bernacki 2413a1f2172SGrzegorz Bernacki /* L2 cache configuration registers */ 2423a1f2172SGrzegorz Bernacki static uint32_t 2433a1f2172SGrzegorz Bernacki read_l2_cache(uint32_t reg) 2443a1f2172SGrzegorz Bernacki { 2453a1f2172SGrzegorz Bernacki 2463a1f2172SGrzegorz Bernacki return (bus_space_read_4(fdtbus_bs_tag, ARMADAXP_L2_BASE, reg)); 2473a1f2172SGrzegorz Bernacki } 2483a1f2172SGrzegorz Bernacki 2493a1f2172SGrzegorz Bernacki static void 2503a1f2172SGrzegorz Bernacki write_l2_cache(uint32_t reg, uint32_t val) 2513a1f2172SGrzegorz Bernacki { 2523a1f2172SGrzegorz Bernacki 2533a1f2172SGrzegorz Bernacki bus_space_write_4(fdtbus_bs_tag, ARMADAXP_L2_BASE, reg, val); 2543a1f2172SGrzegorz Bernacki } 2553a1f2172SGrzegorz Bernacki 2565c39c3ffSGrzegorz Bernacki static void 2573a1f2172SGrzegorz Bernacki armadaxp_l2_idcache_inv_all(void) 2583a1f2172SGrzegorz Bernacki { 2593a1f2172SGrzegorz Bernacki write_l2_cache(ARMADAXP_L2_INV_WAY, ALL_WAYS); 2603a1f2172SGrzegorz Bernacki } 2613a1f2172SGrzegorz Bernacki 2623a1f2172SGrzegorz Bernacki void 2633a1f2172SGrzegorz Bernacki armadaxp_l2_init(void) 2643a1f2172SGrzegorz Bernacki { 2653a1f2172SGrzegorz Bernacki u_int32_t reg; 2663a1f2172SGrzegorz Bernacki 2673a1f2172SGrzegorz Bernacki /* Set L2 policy */ 2683a1f2172SGrzegorz Bernacki reg = read_l2_cache(ARMADAXP_L2_AUX_CTRL); 2693a1f2172SGrzegorz Bernacki reg &= ~(L2_WBWT_MODE_MASK); 2703a1f2172SGrzegorz Bernacki reg &= ~(L2_REP_STRAT_MASK); 2713a1f2172SGrzegorz Bernacki reg |= L2_REP_STRAT_SEMIPLRU; 2723a1f2172SGrzegorz Bernacki reg |= L2_WBWT_MODE_WT; 2733a1f2172SGrzegorz Bernacki write_l2_cache(ARMADAXP_L2_AUX_CTRL, reg); 2743a1f2172SGrzegorz Bernacki 2753a1f2172SGrzegorz Bernacki /* Invalidate l2 cache */ 2763a1f2172SGrzegorz Bernacki armadaxp_l2_idcache_inv_all(); 2773a1f2172SGrzegorz Bernacki 2783a1f2172SGrzegorz Bernacki /* Clear pending L2 interrupts */ 2793a1f2172SGrzegorz Bernacki write_l2_cache(ARMADAXP_L2_INT_CAUSE, 0x1ff); 2803a1f2172SGrzegorz Bernacki 2813a1f2172SGrzegorz Bernacki /* Enable l2 cache */ 2823a1f2172SGrzegorz Bernacki reg = read_l2_cache(ARMADAXP_L2_CTRL); 2833a1f2172SGrzegorz Bernacki write_l2_cache(ARMADAXP_L2_CTRL, reg | L2_ENABLE); 2843a1f2172SGrzegorz Bernacki 2853a1f2172SGrzegorz Bernacki /* 2863a1f2172SGrzegorz Bernacki * For debug purposes 2873a1f2172SGrzegorz Bernacki * Configure and enable counter 2883a1f2172SGrzegorz Bernacki */ 2893a1f2172SGrzegorz Bernacki write_l2_cache(ARMADAXP_L2_CNTR_CONF(0), 0xf0000 | (4 << 2)); 2903a1f2172SGrzegorz Bernacki write_l2_cache(ARMADAXP_L2_CNTR_CONF(1), 0xf0000 | (2 << 2)); 2913a1f2172SGrzegorz Bernacki write_l2_cache(ARMADAXP_L2_CNTR_CTRL, 0x303); 2923a1f2172SGrzegorz Bernacki 2933a1f2172SGrzegorz Bernacki /* 2943a1f2172SGrzegorz Bernacki * Enable Cache maintenance operation propagation in coherency fabric 2953a1f2172SGrzegorz Bernacki * Change point of coherency and point of unification to DRAM. 2963a1f2172SGrzegorz Bernacki */ 2975c39c3ffSGrzegorz Bernacki reg = read_coher_fabric(COHER_FABRIC_CFU); 2983a1f2172SGrzegorz Bernacki reg |= (1 << 17) | (1 << 18); 2995c39c3ffSGrzegorz Bernacki write_coher_fabric(COHER_FABRIC_CFU, reg); 3005c39c3ffSGrzegorz Bernacki 3015c39c3ffSGrzegorz Bernacki /* Coherent IO Bridge initialization */ 3025c39c3ffSGrzegorz Bernacki reg = read_coher_fabric(COHER_FABRIC_CIB_CTRL); 3035c39c3ffSGrzegorz Bernacki reg &= ~(7 << 16); 3045c39c3ffSGrzegorz Bernacki reg |= (7 << 16); 3055c39c3ffSGrzegorz Bernacki write_coher_fabric(COHER_FABRIC_CIB_CTRL, reg); 3063a1f2172SGrzegorz Bernacki } 3073a1f2172SGrzegorz Bernacki 308