1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2011 Semihalf. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * From: FreeBSD: src/sys/arm/mv/kirkwood/sheevaplug.c,v 1.2 2010/06/13 13:28:53 29 */ 30 31 #include <sys/cdefs.h> 32 __FBSDID("$FreeBSD$"); 33 34 #include <sys/param.h> 35 #include <sys/systm.h> 36 #include <sys/bus.h> 37 38 #include <machine/bus.h> 39 #include <machine/armreg.h> 40 41 #include <arm/mv/mvwin.h> 42 #include <arm/mv/mvreg.h> 43 #include <arm/mv/mvvar.h> 44 45 #include <dev/ofw/openfirm.h> 46 47 #include <machine/fdt.h> 48 49 #define CPU_FREQ_FIELD(sar) (((0x01 & (sar >> 52)) << 3) | \ 50 (0x07 & (sar >> 21))) 51 #define FAB_FREQ_FIELD(sar) (((0x01 & (sar >> 51)) << 4) | \ 52 (0x0F & (sar >> 24))) 53 54 static uint32_t count_l2clk(void); 55 void armadaxp_l2_init(void); 56 void armadaxp_init_coher_fabric(void); 57 int platform_get_ncpus(void); 58 59 #define ARMADAXP_L2_BASE (MV_BASE + 0x8000) 60 #define ARMADAXP_L2_CTRL 0x100 61 #define L2_ENABLE (1 << 0) 62 #define ARMADAXP_L2_AUX_CTRL 0x104 63 #define L2_WBWT_MODE_MASK (3 << 0) 64 #define L2_WBWT_MODE_PAGE 0 65 #define L2_WBWT_MODE_WB 1 66 #define L2_WBWT_MODE_WT 2 67 #define L2_REP_STRAT_MASK (3 << 27) 68 #define L2_REP_STRAT_LSFR (1 << 27) 69 #define L2_REP_STRAT_SEMIPLRU (3 << 27) 70 71 #define ARMADAXP_L2_CNTR_CTRL 0x200 72 #define ARMADAXP_L2_CNTR_CONF(x) (0x204 + (x) * 0xc) 73 #define ARMADAXP_L2_CNTR2_VAL_LOW (0x208 + (x) * 0xc) 74 #define ARMADAXP_L2_CNTR2_VAL_HI (0x20c + (x) * 0xc) 75 76 #define ARMADAXP_L2_INT_CAUSE 0x220 77 78 #define ARMADAXP_L2_SYNC_BARRIER 0x700 79 #define ARMADAXP_L2_INV_WAY 0x778 80 #define ARMADAXP_L2_CLEAN_WAY 0x7BC 81 #define ARMADAXP_L2_FLUSH_PHYS 0x7F0 82 #define ARMADAXP_L2_FLUSH_WAY 0x7FC 83 84 #define MV_COHERENCY_FABRIC_BASE (MV_MBUS_BRIDGE_BASE + 0x200) 85 #define COHER_FABRIC_CTRL 0x00 86 #define COHER_FABRIC_CONF 0x04 87 #define COHER_FABRIC_CFU 0x28 88 #define COHER_FABRIC_CIB_CTRL 0x80 89 90 struct vco_freq_ratio { 91 uint8_t vco_cpu; /* VCO to CLK0(CPU) clock ratio */ 92 uint8_t vco_l2c; /* VCO to NB(L2 cache) clock ratio */ 93 uint8_t vco_hcl; /* VCO to HCLK(DDR controller) clock ratio */ 94 uint8_t vco_ddr; /* VCO to DR(DDR memory) clock ratio */ 95 }; 96 97 static struct vco_freq_ratio freq_conf_table[] = { 98 /*00*/ { 1, 1, 4, 2 }, 99 /*01*/ { 1, 2, 2, 2 }, 100 /*02*/ { 2, 2, 6, 3 }, 101 /*03*/ { 2, 2, 3, 3 }, 102 /*04*/ { 1, 2, 3, 3 }, 103 /*05*/ { 1, 2, 4, 2 }, 104 /*06*/ { 1, 1, 2, 2 }, 105 /*07*/ { 2, 3, 6, 6 }, 106 /*08*/ { 2, 3, 5, 5 }, 107 /*09*/ { 1, 2, 6, 3 }, 108 /*10*/ { 2, 4, 10, 5 }, 109 /*11*/ { 1, 3, 6, 6 }, 110 /*12*/ { 1, 2, 5, 5 }, 111 /*13*/ { 1, 3, 6, 3 }, 112 /*14*/ { 1, 2, 5, 5 }, 113 /*15*/ { 2, 2, 5, 5 }, 114 /*16*/ { 1, 1, 3, 3 }, 115 /*17*/ { 2, 5, 10, 10 }, 116 /*18*/ { 1, 3, 8, 4 }, 117 /*19*/ { 1, 1, 2, 1 }, 118 /*20*/ { 2, 3, 6, 3 }, 119 /*21*/ { 1, 2, 8, 4 }, 120 /*22*/ { 2, 5, 10, 5 } 121 }; 122 123 static uint16_t cpu_clock_table[] = { 124 1000, 1066, 1200, 1333, 1500, 1666, 1800, 2000, 600, 667, 800, 1600, 125 2133, 2200, 2400 }; 126 127 uint32_t 128 get_tclk(void) 129 { 130 uint32_t cputype; 131 132 cputype = cpu_ident(); 133 cputype &= CPU_ID_CPU_MASK; 134 135 if (cputype == CPU_ID_MV88SV584X_V7) 136 return (TCLK_250MHZ); 137 else 138 return (TCLK_200MHZ); 139 } 140 141 uint32_t 142 get_cpu_freq(void) 143 { 144 145 return (0); 146 } 147 148 static uint32_t 149 count_l2clk(void) 150 { 151 uint64_t sar_reg; 152 uint32_t freq_vco, freq_l2clk; 153 uint8_t sar_cpu_freq, sar_fab_freq, array_size; 154 155 /* Get value of the SAR register and process it */ 156 sar_reg = get_sar_value(); 157 sar_cpu_freq = CPU_FREQ_FIELD(sar_reg); 158 sar_fab_freq = FAB_FREQ_FIELD(sar_reg); 159 160 /* Check if CPU frequency field has correct value */ 161 array_size = nitems(cpu_clock_table); 162 if (sar_cpu_freq >= array_size) 163 panic("Reserved value in cpu frequency configuration field: " 164 "%d", sar_cpu_freq); 165 166 /* Check if fabric frequency field has correct value */ 167 array_size = nitems(freq_conf_table); 168 if (sar_fab_freq >= array_size) 169 panic("Reserved value in fabric frequency configuration field: " 170 "%d", sar_fab_freq); 171 172 /* Get CPU clock frequency */ 173 freq_vco = cpu_clock_table[sar_cpu_freq] * 174 freq_conf_table[sar_fab_freq].vco_cpu; 175 176 /* Get L2CLK clock frequency */ 177 freq_l2clk = freq_vco / freq_conf_table[sar_fab_freq].vco_l2c; 178 179 /* Round L2CLK value to integer MHz */ 180 if (((freq_vco % freq_conf_table[sar_fab_freq].vco_l2c) * 10 / 181 freq_conf_table[sar_fab_freq].vco_l2c) >= 5) 182 freq_l2clk++; 183 184 return (freq_l2clk * 1000000); 185 } 186 187 uint32_t 188 get_l2clk(void) 189 { 190 static uint32_t l2clk_freq = 0; 191 192 /* If get_l2clk is called first time get L2CLK value from register */ 193 if (l2clk_freq == 0) 194 l2clk_freq = count_l2clk(); 195 196 return (l2clk_freq); 197 } 198 199 static uint32_t 200 read_coher_fabric(uint32_t reg) 201 { 202 203 return (bus_space_read_4(fdtbus_bs_tag, MV_COHERENCY_FABRIC_BASE, reg)); 204 } 205 206 static void 207 write_coher_fabric(uint32_t reg, uint32_t val) 208 { 209 210 bus_space_write_4(fdtbus_bs_tag, MV_COHERENCY_FABRIC_BASE, reg, val); 211 } 212 213 int 214 platform_get_ncpus(void) 215 { 216 #if !defined(SMP) 217 return (1); 218 #else 219 return ((read_coher_fabric(COHER_FABRIC_CONF) & 0xf) + 1); 220 #endif 221 } 222 223 void 224 armadaxp_init_coher_fabric(void) 225 { 226 uint32_t val, cpus, mask; 227 228 cpus = platform_get_ncpus(); 229 mask = (1 << cpus) - 1; 230 val = read_coher_fabric(COHER_FABRIC_CTRL); 231 val |= (mask << 24); 232 write_coher_fabric(COHER_FABRIC_CTRL, val); 233 234 val = read_coher_fabric(COHER_FABRIC_CONF); 235 val |= (mask << 24); 236 val |= (1 << 15); 237 write_coher_fabric(COHER_FABRIC_CONF, val); 238 } 239 240 #define ALL_WAYS 0xffffffff 241 242 /* L2 cache configuration registers */ 243 static uint32_t 244 read_l2_cache(uint32_t reg) 245 { 246 247 return (bus_space_read_4(fdtbus_bs_tag, ARMADAXP_L2_BASE, reg)); 248 } 249 250 static void 251 write_l2_cache(uint32_t reg, uint32_t val) 252 { 253 254 bus_space_write_4(fdtbus_bs_tag, ARMADAXP_L2_BASE, reg, val); 255 } 256 257 static void 258 armadaxp_l2_idcache_inv_all(void) 259 { 260 write_l2_cache(ARMADAXP_L2_INV_WAY, ALL_WAYS); 261 } 262 263 void 264 armadaxp_l2_init(void) 265 { 266 u_int32_t reg; 267 268 /* Set L2 policy */ 269 reg = read_l2_cache(ARMADAXP_L2_AUX_CTRL); 270 reg &= ~(L2_WBWT_MODE_MASK); 271 reg &= ~(L2_REP_STRAT_MASK); 272 reg |= L2_REP_STRAT_SEMIPLRU; 273 reg |= L2_WBWT_MODE_WT; 274 write_l2_cache(ARMADAXP_L2_AUX_CTRL, reg); 275 276 /* Invalidate l2 cache */ 277 armadaxp_l2_idcache_inv_all(); 278 279 /* Clear pending L2 interrupts */ 280 write_l2_cache(ARMADAXP_L2_INT_CAUSE, 0x1ff); 281 282 /* Enable l2 cache */ 283 reg = read_l2_cache(ARMADAXP_L2_CTRL); 284 write_l2_cache(ARMADAXP_L2_CTRL, reg | L2_ENABLE); 285 286 /* 287 * For debug purposes 288 * Configure and enable counter 289 */ 290 write_l2_cache(ARMADAXP_L2_CNTR_CONF(0), 0xf0000 | (4 << 2)); 291 write_l2_cache(ARMADAXP_L2_CNTR_CONF(1), 0xf0000 | (2 << 2)); 292 write_l2_cache(ARMADAXP_L2_CNTR_CTRL, 0x303); 293 294 /* 295 * Enable Cache maintenance operation propagation in coherency fabric 296 * Change point of coherency and point of unification to DRAM. 297 */ 298 reg = read_coher_fabric(COHER_FABRIC_CFU); 299 reg |= (1 << 17) | (1 << 18); 300 write_coher_fabric(COHER_FABRIC_CFU, reg); 301 302 /* Coherent IO Bridge initialization */ 303 reg = read_coher_fabric(COHER_FABRIC_CIB_CTRL); 304 reg &= ~(7 << 16); 305 reg |= (7 << 16); 306 write_coher_fabric(COHER_FABRIC_CIB_CTRL, reg); 307 } 308 309