1 /*- 2 * Copyright (c) 2011 Semihalf. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * From: FreeBSD: src/sys/arm/mv/kirkwood/sheevaplug.c,v 1.2 2010/06/13 13:28:53 27 */ 28 29 #include <sys/cdefs.h> 30 __FBSDID("$FreeBSD$"); 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/bus.h> 35 36 #include <machine/bus.h> 37 #include <machine/armreg.h> 38 39 #include <arm/mv/mvwin.h> 40 #include <arm/mv/mvreg.h> 41 #include <arm/mv/mvvar.h> 42 43 #include <dev/ofw/openfirm.h> 44 45 #include <machine/fdt.h> 46 47 #define CPU_FREQ_FIELD(sar) (((0x01 & (sar >> 52)) << 3) | \ 48 (0x07 & (sar >> 21))) 49 #define FAB_FREQ_FIELD(sar) (((0x01 & (sar >> 51)) << 4) | \ 50 (0x0F & (sar >> 24))) 51 52 static uint32_t count_l2clk(void); 53 void armadaxp_l2_init(void); 54 void armadaxp_init_coher_fabric(void); 55 int platform_get_ncpus(void); 56 57 #define ARMADAXP_L2_BASE (MV_BASE + 0x8000) 58 #define ARMADAXP_L2_CTRL 0x100 59 #define L2_ENABLE (1 << 0) 60 #define ARMADAXP_L2_AUX_CTRL 0x104 61 #define L2_WBWT_MODE_MASK (3 << 0) 62 #define L2_WBWT_MODE_PAGE 0 63 #define L2_WBWT_MODE_WB 1 64 #define L2_WBWT_MODE_WT 2 65 #define L2_REP_STRAT_MASK (3 << 27) 66 #define L2_REP_STRAT_LSFR (1 << 27) 67 #define L2_REP_STRAT_SEMIPLRU (3 << 27) 68 69 #define ARMADAXP_L2_CNTR_CTRL 0x200 70 #define ARMADAXP_L2_CNTR_CONF(x) (0x204 + (x) * 0xc) 71 #define ARMADAXP_L2_CNTR2_VAL_LOW (0x208 + (x) * 0xc) 72 #define ARMADAXP_L2_CNTR2_VAL_HI (0x20c + (x) * 0xc) 73 74 #define ARMADAXP_L2_INT_CAUSE 0x220 75 76 #define ARMADAXP_L2_SYNC_BARRIER 0x700 77 #define ARMADAXP_L2_INV_WAY 0x778 78 #define ARMADAXP_L2_CLEAN_WAY 0x7BC 79 #define ARMADAXP_L2_FLUSH_PHYS 0x7F0 80 #define ARMADAXP_L2_FLUSH_WAY 0x7FC 81 82 #define MV_COHERENCY_FABRIC_BASE (MV_MBUS_BRIDGE_BASE + 0x200) 83 #define COHER_FABRIC_CTRL 0x00 84 #define COHER_FABRIC_CONF 0x04 85 #define COHER_FABRIC_CFU 0x28 86 #define COHER_FABRIC_CIB_CTRL 0x80 87 88 struct vco_freq_ratio { 89 uint8_t vco_cpu; /* VCO to CLK0(CPU) clock ratio */ 90 uint8_t vco_l2c; /* VCO to NB(L2 cache) clock ratio */ 91 uint8_t vco_hcl; /* VCO to HCLK(DDR controller) clock ratio */ 92 uint8_t vco_ddr; /* VCO to DR(DDR memory) clock ratio */ 93 }; 94 95 static struct vco_freq_ratio freq_conf_table[] = { 96 /*00*/ { 1, 1, 4, 2 }, 97 /*01*/ { 1, 2, 2, 2 }, 98 /*02*/ { 2, 2, 6, 3 }, 99 /*03*/ { 2, 2, 3, 3 }, 100 /*04*/ { 1, 2, 3, 3 }, 101 /*05*/ { 1, 2, 4, 2 }, 102 /*06*/ { 1, 1, 2, 2 }, 103 /*07*/ { 2, 3, 6, 6 }, 104 /*08*/ { 2, 3, 5, 5 }, 105 /*09*/ { 1, 2, 6, 3 }, 106 /*10*/ { 2, 4, 10, 5 }, 107 /*11*/ { 1, 3, 6, 6 }, 108 /*12*/ { 1, 2, 5, 5 }, 109 /*13*/ { 1, 3, 6, 3 }, 110 /*14*/ { 1, 2, 5, 5 }, 111 /*15*/ { 2, 2, 5, 5 }, 112 /*16*/ { 1, 1, 3, 3 }, 113 /*17*/ { 2, 5, 10, 10 }, 114 /*18*/ { 1, 3, 8, 4 }, 115 /*19*/ { 1, 1, 2, 1 }, 116 /*20*/ { 2, 3, 6, 3 }, 117 /*21*/ { 1, 2, 8, 4 }, 118 /*22*/ { 2, 5, 10, 5 } 119 }; 120 121 static uint16_t cpu_clock_table[] = { 122 1000, 1066, 1200, 1333, 1500, 1666, 1800, 2000, 600, 667, 800, 1600, 123 2133, 2200, 2400 }; 124 125 uint32_t 126 get_tclk(void) 127 { 128 uint32_t cputype; 129 130 cputype = cpu_ident(); 131 cputype &= CPU_ID_CPU_MASK; 132 133 if (cputype == CPU_ID_MV88SV584X_V7) 134 return (TCLK_250MHZ); 135 else 136 return (TCLK_200MHZ); 137 } 138 139 static uint32_t 140 count_l2clk(void) 141 { 142 uint64_t sar_reg; 143 uint32_t freq_vco, freq_l2clk; 144 uint8_t sar_cpu_freq, sar_fab_freq, array_size; 145 146 /* Get value of the SAR register and process it */ 147 sar_reg = get_sar_value(); 148 sar_cpu_freq = CPU_FREQ_FIELD(sar_reg); 149 sar_fab_freq = FAB_FREQ_FIELD(sar_reg); 150 151 /* Check if CPU frequency field has correct value */ 152 array_size = nitems(cpu_clock_table); 153 if (sar_cpu_freq >= array_size) 154 panic("Reserved value in cpu frequency configuration field: " 155 "%d", sar_cpu_freq); 156 157 /* Check if fabric frequency field has correct value */ 158 array_size = nitems(freq_conf_table); 159 if (sar_fab_freq >= array_size) 160 panic("Reserved value in fabric frequency configuration field: " 161 "%d", sar_fab_freq); 162 163 /* Get CPU clock frequency */ 164 freq_vco = cpu_clock_table[sar_cpu_freq] * 165 freq_conf_table[sar_fab_freq].vco_cpu; 166 167 /* Get L2CLK clock frequency */ 168 freq_l2clk = freq_vco / freq_conf_table[sar_fab_freq].vco_l2c; 169 170 /* Round L2CLK value to integer MHz */ 171 if (((freq_vco % freq_conf_table[sar_fab_freq].vco_l2c) * 10 / 172 freq_conf_table[sar_fab_freq].vco_l2c) >= 5) 173 freq_l2clk++; 174 175 return (freq_l2clk * 1000000); 176 } 177 178 uint32_t 179 get_l2clk(void) 180 { 181 static uint32_t l2clk_freq = 0; 182 183 /* If get_l2clk is called first time get L2CLK value from register */ 184 if (l2clk_freq == 0) 185 l2clk_freq = count_l2clk(); 186 187 return (l2clk_freq); 188 } 189 190 static uint32_t 191 read_coher_fabric(uint32_t reg) 192 { 193 194 return (bus_space_read_4(fdtbus_bs_tag, MV_COHERENCY_FABRIC_BASE, reg)); 195 } 196 197 static void 198 write_coher_fabric(uint32_t reg, uint32_t val) 199 { 200 201 bus_space_write_4(fdtbus_bs_tag, MV_COHERENCY_FABRIC_BASE, reg, val); 202 } 203 204 int 205 platform_get_ncpus(void) 206 { 207 #if !defined(SMP) 208 return (1); 209 #else 210 return ((read_coher_fabric(COHER_FABRIC_CONF) & 0xf) + 1); 211 #endif 212 } 213 214 void 215 armadaxp_init_coher_fabric(void) 216 { 217 uint32_t val, cpus, mask; 218 219 cpus = platform_get_ncpus(); 220 mask = (1 << cpus) - 1; 221 val = read_coher_fabric(COHER_FABRIC_CTRL); 222 val |= (mask << 24); 223 write_coher_fabric(COHER_FABRIC_CTRL, val); 224 225 val = read_coher_fabric(COHER_FABRIC_CONF); 226 val |= (mask << 24); 227 val |= (1 << 15); 228 write_coher_fabric(COHER_FABRIC_CONF, val); 229 } 230 231 #define ALL_WAYS 0xffffffff 232 233 /* L2 cache configuration registers */ 234 static uint32_t 235 read_l2_cache(uint32_t reg) 236 { 237 238 return (bus_space_read_4(fdtbus_bs_tag, ARMADAXP_L2_BASE, reg)); 239 } 240 241 static void 242 write_l2_cache(uint32_t reg, uint32_t val) 243 { 244 245 bus_space_write_4(fdtbus_bs_tag, ARMADAXP_L2_BASE, reg, val); 246 } 247 248 static void 249 armadaxp_l2_idcache_inv_all(void) 250 { 251 write_l2_cache(ARMADAXP_L2_INV_WAY, ALL_WAYS); 252 } 253 254 void 255 armadaxp_l2_init(void) 256 { 257 u_int32_t reg; 258 259 /* Set L2 policy */ 260 reg = read_l2_cache(ARMADAXP_L2_AUX_CTRL); 261 reg &= ~(L2_WBWT_MODE_MASK); 262 reg &= ~(L2_REP_STRAT_MASK); 263 reg |= L2_REP_STRAT_SEMIPLRU; 264 reg |= L2_WBWT_MODE_WT; 265 write_l2_cache(ARMADAXP_L2_AUX_CTRL, reg); 266 267 /* Invalidate l2 cache */ 268 armadaxp_l2_idcache_inv_all(); 269 270 /* Clear pending L2 interrupts */ 271 write_l2_cache(ARMADAXP_L2_INT_CAUSE, 0x1ff); 272 273 /* Enable l2 cache */ 274 reg = read_l2_cache(ARMADAXP_L2_CTRL); 275 write_l2_cache(ARMADAXP_L2_CTRL, reg | L2_ENABLE); 276 277 /* 278 * For debug purposes 279 * Configure and enable counter 280 */ 281 write_l2_cache(ARMADAXP_L2_CNTR_CONF(0), 0xf0000 | (4 << 2)); 282 write_l2_cache(ARMADAXP_L2_CNTR_CONF(1), 0xf0000 | (2 << 2)); 283 write_l2_cache(ARMADAXP_L2_CNTR_CTRL, 0x303); 284 285 /* 286 * Enable Cache maintenance operation propagation in coherency fabric 287 * Change point of coherency and point of unification to DRAM. 288 */ 289 reg = read_coher_fabric(COHER_FABRIC_CFU); 290 reg |= (1 << 17) | (1 << 18); 291 write_coher_fabric(COHER_FABRIC_CFU, reg); 292 293 /* Coherent IO Bridge initialization */ 294 reg = read_coher_fabric(COHER_FABRIC_CIB_CTRL); 295 reg &= ~(7 << 16); 296 reg |= (7 << 16); 297 write_coher_fabric(COHER_FABRIC_CIB_CTRL, reg); 298 } 299 300