1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2021 Semihalf. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #include <sys/param.h> 29 #include <sys/bus.h> 30 #include <sys/kernel.h> 31 #include <sys/module.h> 32 #include <sys/mutex.h> 33 #include <sys/rman.h> 34 #include <machine/bus.h> 35 36 #include <dev/fdt/simplebus.h> 37 38 #include <dev/extres/clk/clk.h> 39 #include <dev/extres/clk/clk_fixed.h> 40 41 #include <dev/ofw/ofw_bus.h> 42 #include <dev/ofw/ofw_bus_subr.h> 43 44 #include "clkdev_if.h" 45 #include "periph.h" 46 47 #define SB_DEV_COUNT 14 48 49 static struct a37x0_periph_clknode_def a37x0_sb_devices [] = { 50 CLK_MDD("gbe_50", 0, 6, 1, DIV_SEL2, DIV_SEL2, 6, 9, 51 "tbg_mux_gbe_50_120", "div1_gbe_50_121", "div2_gbe_50_122"), 52 CLK_MDD("gbe_core", 1, 8, 5, DIV_SEL1, DIV_SEL1, 18, 21, 53 "tbg_mux_gbe_core_124", "div1_gbe_core_125", "div2_gbe_core_126"), 54 CLK_MDD("gbe_125", 2, 10, 3, DIV_SEL1, DIV_SEL1, 6, 9, 55 "tbg_mux_gbe_125_128", "div1_gbe_50_129", "div2_gbe_50_130"), 56 CLK_GATE("gbe1_50", 3, 0, "gbe_50"), 57 CLK_GATE("gbe0_50", 4, 1, "gbe_50"), 58 CLK_GATE("gbe1_125", 5, 2, "gbe_125"), 59 CLK_GATE("gbe0_125", 6, 3, "gbe_125"), 60 CLK_MUX_GATE("gbe1_core", 7, 4, 13, "gbe_core", 61 "mux_gbe1_core_136", "fixed_gbe1_core_138"), 62 CLK_MUX_GATE("gbe0_core", 8, 5, 14, "gbe_core", 63 "mux_gbe0_core_139", "fixed_gbe0_core_141"), 64 CLK_MUX_GATE("gbe_bm", 9, 12, 12, "gbe_core", 65 "mux_gbe_bm_136", "fixed_gbe_bm_138"), 66 CLK_FULL_DD("sdio", 10, 11, 14, 7, DIV_SEL0, DIV_SEL0, 3, 6, 67 "tbg_mux_sdio_139", "div1_sdio_140", "div2_sdio_141", 68 "clk_mux_sdio_142"), 69 CLK_FULL_DD("usb32_usb2_sys", 11, 16, 16, 8, DIV_SEL0, DIV_SEL0, 9, 12, 70 "tbg_mux_usb32_usb2_sys_144", "div1_usb32_usb2_sys_145", 71 "div2_usb32_usb2_sys_146", "clk_mux_usb32_usb2_sys_147"), 72 CLK_FULL_DD("usb32_ss_sys", 12, 17, 18, 9, DIV_SEL0, DIV_SEL0, 15, 18, 73 "tbg_mux_usb32_ss_sys_149", "div1_usb32_ss_sys_150", 74 "div2_usb32_ss_sys_151", "clk_mux_usb32_ss_sys_152"), 75 CLK_GATE("pcie", 13, 14, "gbe_core") 76 }; 77 78 static struct ofw_compat_data a37x0_sb_periph_compat_data[] = { 79 { "marvell,armada-3700-periph-clock-sb", 1 }, 80 { NULL, 0 } 81 }; 82 83 static int a37x0_sb_periph_clk_attach(device_t); 84 static int a37x0_sb_periph_clk_probe(device_t); 85 86 static device_method_t a37x0_sb_periph_clk_methods[] = { 87 DEVMETHOD(clkdev_device_unlock, a37x0_periph_clk_device_unlock), 88 DEVMETHOD(clkdev_device_lock, a37x0_periph_clk_device_lock), 89 DEVMETHOD(clkdev_read_4, a37x0_periph_clk_read_4), 90 91 DEVMETHOD(device_attach, a37x0_sb_periph_clk_attach), 92 DEVMETHOD(device_detach, a37x0_periph_clk_detach), 93 DEVMETHOD(device_probe, a37x0_sb_periph_clk_probe), 94 95 DEVMETHOD_END 96 }; 97 98 static driver_t a37x0_sb_periph_driver = { 99 "a37x0_sb_periph_driver", 100 a37x0_sb_periph_clk_methods, 101 sizeof(struct a37x0_periph_clk_softc) 102 }; 103 104 EARLY_DRIVER_MODULE(a37x0_sb_periph, simplebus, a37x0_sb_periph_driver, 0, 0, 105 BUS_PASS_TIMER + BUS_PASS_ORDER_LATE); 106 107 static int 108 a37x0_sb_periph_clk_attach(device_t dev) 109 { 110 struct a37x0_periph_clk_softc *sc; 111 112 sc = device_get_softc(dev); 113 sc->devices = a37x0_sb_devices; 114 sc->device_count = SB_DEV_COUNT; 115 116 return (a37x0_periph_clk_attach(dev)); 117 } 118 119 static int 120 a37x0_sb_periph_clk_probe(device_t dev) 121 { 122 123 if (!ofw_bus_status_okay(dev)) 124 return (ENXIO); 125 126 if (!ofw_bus_search_compatible(dev, 127 a37x0_sb_periph_compat_data)->ocd_data) 128 return (ENXIO); 129 130 device_set_desc(dev, "marvell,armada-3700-sb-periph-clock"); 131 132 return (BUS_PROBE_DEFAULT); 133 } 134