1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2021 Semihalf. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #include <sys/param.h> 29 #include <sys/bus.h> 30 #include <sys/kernel.h> 31 #include <sys/module.h> 32 #include <sys/mutex.h> 33 #include <sys/rman.h> 34 #include <machine/bus.h> 35 36 #include <dev/fdt/simplebus.h> 37 38 #include <dev/extres/clk/clk.h> 39 #include <dev/extres/clk/clk_div.h> 40 #include <dev/extres/clk/clk_fixed.h> 41 #include <dev/extres/clk/clk_gate.h> 42 #include <dev/extres/clk/clk_mux.h> 43 44 #include <dev/ofw/ofw_bus.h> 45 #include <dev/ofw/ofw_bus_subr.h> 46 47 #include "clkdev_if.h" 48 #include "periph.h" 49 50 #define PARENT_CNT 2 51 #define TBG_A_S_OFW_INDEX 0 52 53 /* 54 * Register chain: fixed (freq/2) -> mux (choose fixed or parent frequency) -> 55 * gate (enable or disable clock). 56 */ 57 58 int 59 a37x0_periph_register_mux_gate(struct clkdom *clkdom, 60 struct a37x0_periph_clknode_def *device_def) 61 { 62 const char *parent_names[PARENT_CNT]; 63 struct clk_fixed_def fixed; 64 struct clk_gate_def *gate; 65 struct clk_mux_def *mux; 66 int error, dev_id; 67 68 dev_id = device_def->common_def.device_id; 69 mux = &device_def->clk_def.mux_gate.mux; 70 gate = &device_def->clk_def.mux_gate.gate; 71 fixed = device_def->clk_def.fixed.fixed; 72 73 fixed.clkdef.id = A37x0_INTERNAL_CLK_ID(dev_id, FIXED1_POS); 74 fixed.clkdef.parent_names = &device_def->common_def.pname; 75 fixed.clkdef.parent_cnt = 1; 76 fixed.clkdef.flags = 0x0; 77 fixed.mult = 1; 78 fixed.div = 2; 79 fixed.freq = 0; 80 81 error = clknode_fixed_register(clkdom, &fixed); 82 if (error) 83 goto fail; 84 85 parent_names[0] = device_def->common_def.pname; 86 parent_names[1] = fixed.clkdef.name; 87 88 a37x0_periph_set_props(&mux->clkdef, parent_names, PARENT_CNT); 89 error = a37x0_periph_create_mux(clkdom, mux, 90 A37x0_INTERNAL_CLK_ID(dev_id, MUX_POS)); 91 if (error) 92 goto fail; 93 94 a37x0_periph_set_props(&gate->clkdef, &mux->clkdef.name, 1); 95 error = a37x0_periph_create_gate(clkdom, gate, 96 dev_id); 97 if (error) 98 goto fail; 99 100 fail: 101 102 return (error); 103 } 104 105 /* 106 * Register chain: fixed1 (freq/2) -> mux (fixed1 or TBG-A-S frequency) -> 107 * gate -> fixed2 (freq/2). 108 */ 109 110 int 111 a37x0_periph_register_mux_gate_fixed(struct clkdom * clkdom, 112 struct a37x0_periph_clknode_def *device_def) 113 { 114 struct clk_fixed_def *fixed1, *fixed2; 115 const char *parent_names[PARENT_CNT]; 116 struct clk_gate_def *gate; 117 struct clk_mux_def *mux; 118 int error, dev_id; 119 120 dev_id = device_def->common_def.device_id; 121 mux = &device_def->clk_def.mux_gate_fixed.mux; 122 gate = &device_def->clk_def.mux_gate_fixed.gate; 123 fixed1 = &device_def->clk_def.mux_gate_fixed.fixed1; 124 fixed2 = &device_def->clk_def.mux_gate_fixed.fixed2; 125 126 fixed1->clkdef.parent_names = &device_def->common_def.pname; 127 fixed1->clkdef.id = A37x0_INTERNAL_CLK_ID(dev_id, FIXED1_POS); 128 fixed1->clkdef.flags = 0x0; 129 fixed1->mult = 1; 130 fixed1->div = 2; 131 fixed1->freq = 0; 132 133 error = clknode_fixed_register(clkdom, fixed1); 134 if (error) 135 goto fail; 136 137 parent_names[0] = device_def->common_def.tbgs[TBG_A_S_OFW_INDEX]; 138 parent_names[1] = fixed1->clkdef.name; 139 140 a37x0_periph_set_props(&mux->clkdef, parent_names, PARENT_CNT); 141 error = a37x0_periph_create_mux(clkdom, mux, 142 A37x0_INTERNAL_CLK_ID(dev_id, MUX_POS)); 143 if (error) 144 goto fail; 145 146 a37x0_periph_set_props(&gate->clkdef, &mux->clkdef.name, 1); 147 error = a37x0_periph_create_gate(clkdom, gate, 148 A37x0_INTERNAL_CLK_ID(dev_id, GATE_POS)); 149 if (error) 150 goto fail; 151 152 fixed2->clkdef.parent_names = &gate->clkdef.name; 153 fixed2->clkdef.parent_cnt = 1; 154 fixed2->clkdef.id = dev_id; 155 156 error = clknode_fixed_register(clkdom, fixed2); 157 if (error) 158 goto fail; 159 160 fail: 161 162 return (error); 163 } 164