1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2006 Benno Rice. 5 * Copyright (C) 2008 MARVELL INTERNATIONAL LTD. 6 * Copyright (c) 2017 Semihalf. 7 * All rights reserved. 8 * 9 * Adapted and extended for Marvell SoCs by Semihalf. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 * 31 * from: FreeBSD: //depot/projects/arm/src/sys/arm/xscale/pxa2x0/pxa2x0_gpio.c, rev 1 32 */ 33 34 #include <sys/cdefs.h> 35 __FBSDID("$FreeBSD$"); 36 37 #include <sys/param.h> 38 #include <sys/systm.h> 39 #include <sys/bus.h> 40 #include <sys/kernel.h> 41 #include <sys/lock.h> 42 #include <sys/interrupt.h> 43 #include <sys/module.h> 44 #include <sys/malloc.h> 45 #include <sys/mutex.h> 46 #include <sys/rman.h> 47 #include <sys/queue.h> 48 #include <sys/timetc.h> 49 #include <sys/callout.h> 50 #include <sys/gpio.h> 51 #include <machine/bus.h> 52 #include <machine/intr.h> 53 54 #include <dev/gpio/gpiobusvar.h> 55 #include <dev/ofw/ofw_bus.h> 56 #include <dev/ofw/ofw_bus_subr.h> 57 58 #include <arm/mv/mvvar.h> 59 #include <arm/mv/mvreg.h> 60 61 #include "gpio_if.h" 62 63 #ifdef __aarch64__ 64 #include "opt_soc.h" 65 #endif 66 67 #define GPIO_MAX_INTR_COUNT 8 68 #define GPIO_PINS_PER_REG 32 69 #define GPIO_GENERIC_CAP (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT | \ 70 GPIO_PIN_OPENDRAIN | GPIO_PIN_PUSHPULL | \ 71 GPIO_PIN_TRISTATE | GPIO_PIN_PULLUP | \ 72 GPIO_PIN_PULLDOWN | GPIO_PIN_INVIN | \ 73 GPIO_PIN_INVOUT) 74 75 #define DEBOUNCE_CHECK_MS 1 76 #define DEBOUNCE_LO_HI_MS 2 77 #define DEBOUNCE_HI_LO_MS 2 78 #define DEBOUNCE_CHECK_TICKS ((hz / 1000) * DEBOUNCE_CHECK_MS) 79 80 struct mv_gpio_softc { 81 device_t dev; 82 device_t sc_busdev; 83 struct resource * mem_res; 84 int mem_rid; 85 struct resource * irq_res[GPIO_MAX_INTR_COUNT]; 86 int irq_rid[GPIO_MAX_INTR_COUNT]; 87 struct intr_event * gpio_events[MV_GPIO_MAX_NPINS]; 88 void *ih_cookie[GPIO_MAX_INTR_COUNT]; 89 bus_space_tag_t bst; 90 bus_space_handle_t bsh; 91 uint32_t offset; 92 struct mtx mutex; 93 uint8_t pin_num; /* number of GPIO pins */ 94 uint8_t irq_num; /* number of real IRQs occupied by GPIO controller */ 95 struct gpio_pin gpio_setup[MV_GPIO_MAX_NPINS]; 96 97 /* Used for debouncing. */ 98 uint32_t debounced_state_lo; 99 uint32_t debounced_state_hi; 100 struct callout **debounce_callouts; 101 int *debounce_counters; 102 }; 103 104 struct mv_gpio_pindev { 105 device_t dev; 106 int pin; 107 }; 108 109 static int mv_gpio_probe(device_t); 110 static int mv_gpio_attach(device_t); 111 static int mv_gpio_intr(device_t, void *); 112 113 static void mv_gpio_double_edge_init(device_t, int); 114 115 static int mv_gpio_debounce_setup(device_t, int); 116 static int mv_gpio_debounce_prepare(device_t, int); 117 static int mv_gpio_debounce_init(device_t, int); 118 static void mv_gpio_debounce_start(device_t, int); 119 static void mv_gpio_debounce(void *); 120 static void mv_gpio_debounced_state_set(device_t, int, uint8_t); 121 static uint32_t mv_gpio_debounced_state_get(device_t, int); 122 123 static void mv_gpio_exec_intr_handlers(device_t, uint32_t, int); 124 static void mv_gpio_intr_handler(device_t, int); 125 static uint32_t mv_gpio_reg_read(device_t, uint32_t); 126 static void mv_gpio_reg_write(device_t, uint32_t, uint32_t); 127 static void mv_gpio_reg_set(device_t, uint32_t, uint32_t); 128 static void mv_gpio_reg_clear(device_t, uint32_t, uint32_t); 129 130 static void mv_gpio_blink(device_t, uint32_t, uint8_t); 131 static void mv_gpio_polarity(device_t, uint32_t, uint8_t, uint8_t); 132 static void mv_gpio_level(device_t, uint32_t, uint8_t); 133 static void mv_gpio_edge(device_t, uint32_t, uint8_t); 134 static void mv_gpio_out_en(device_t, uint32_t, uint8_t); 135 static void mv_gpio_int_ack(struct mv_gpio_pindev *); 136 static void mv_gpio_value_set(device_t, uint32_t, uint8_t); 137 static uint32_t mv_gpio_value_get(device_t, uint32_t, uint8_t); 138 139 static void mv_gpio_intr_mask(struct mv_gpio_pindev *); 140 static void mv_gpio_intr_unmask(struct mv_gpio_pindev *); 141 142 void mv_gpio_finish_intrhandler(struct mv_gpio_pindev *); 143 int mv_gpio_setup_intrhandler(device_t, const char *, 144 driver_filter_t *, void (*)(void *), void *, 145 int, int, void **); 146 int mv_gpio_configure(device_t, uint32_t, uint32_t, uint32_t); 147 void mv_gpio_out(device_t, uint32_t, uint8_t, uint8_t); 148 uint8_t mv_gpio_in(device_t, uint32_t); 149 150 /* 151 * GPIO interface 152 */ 153 static device_t mv_gpio_get_bus(device_t); 154 static int mv_gpio_pin_max(device_t, int *); 155 static int mv_gpio_pin_getcaps(device_t, uint32_t, uint32_t *); 156 static int mv_gpio_pin_getflags(device_t, uint32_t, uint32_t *); 157 static int mv_gpio_pin_getname(device_t, uint32_t, char *); 158 static int mv_gpio_pin_setflags(device_t, uint32_t, uint32_t); 159 static int mv_gpio_pin_set(device_t, uint32_t, unsigned int); 160 static int mv_gpio_pin_get(device_t, uint32_t, unsigned int *); 161 static int mv_gpio_pin_toggle(device_t, uint32_t); 162 static int mv_gpio_map_gpios(device_t, phandle_t, phandle_t, 163 int, pcell_t *, uint32_t *, uint32_t *); 164 165 #define MV_GPIO_LOCK() mtx_lock_spin(&sc->mutex) 166 #define MV_GPIO_UNLOCK() mtx_unlock_spin(&sc->mutex) 167 #define MV_GPIO_ASSERT_LOCKED() mtx_assert(&sc->mutex, MA_OWNED) 168 169 static device_method_t mv_gpio_methods[] = { 170 DEVMETHOD(device_probe, mv_gpio_probe), 171 DEVMETHOD(device_attach, mv_gpio_attach), 172 173 /* GPIO protocol */ 174 DEVMETHOD(gpio_get_bus, mv_gpio_get_bus), 175 DEVMETHOD(gpio_pin_max, mv_gpio_pin_max), 176 DEVMETHOD(gpio_pin_getname, mv_gpio_pin_getname), 177 DEVMETHOD(gpio_pin_getflags, mv_gpio_pin_getflags), 178 DEVMETHOD(gpio_pin_getcaps, mv_gpio_pin_getcaps), 179 DEVMETHOD(gpio_pin_setflags, mv_gpio_pin_setflags), 180 DEVMETHOD(gpio_pin_get, mv_gpio_pin_get), 181 DEVMETHOD(gpio_pin_set, mv_gpio_pin_set), 182 DEVMETHOD(gpio_pin_toggle, mv_gpio_pin_toggle), 183 DEVMETHOD(gpio_map_gpios, mv_gpio_map_gpios), 184 185 DEVMETHOD_END 186 }; 187 188 static driver_t mv_gpio_driver = { 189 "gpio", 190 mv_gpio_methods, 191 sizeof(struct mv_gpio_softc), 192 }; 193 194 static devclass_t mv_gpio_devclass; 195 196 DRIVER_MODULE(mv_gpio, simplebus, mv_gpio_driver, mv_gpio_devclass, 0, 0); 197 198 struct ofw_compat_data compat_data[] = { 199 { "mrvl,gpio", 1 }, 200 { "marvell,orion-gpio", 1 }, 201 #ifdef SOC_MARVELL_8K 202 { "marvell,armada-8k-gpio", 1 }, 203 #endif 204 { NULL, 0 } 205 }; 206 207 static int 208 mv_gpio_probe(device_t dev) 209 { 210 if (!ofw_bus_status_okay(dev)) 211 return (ENXIO); 212 213 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) 214 return (ENXIO); 215 216 device_set_desc(dev, "Marvell Integrated GPIO Controller"); 217 return (0); 218 } 219 220 static int 221 mv_gpio_setup_interrupts(struct mv_gpio_softc *sc, phandle_t node) 222 { 223 phandle_t iparent; 224 pcell_t irq_cells; 225 int i, size; 226 227 /* Find root interrupt controller */ 228 iparent = ofw_bus_find_iparent(node); 229 if (iparent == 0) { 230 device_printf(sc->dev, "No interrupt-parrent found. " 231 "Error in DTB\n"); 232 return (ENXIO); 233 } else { 234 /* While at parent - store interrupt cells prop */ 235 if (OF_searchencprop(OF_node_from_xref(iparent), 236 "#interrupt-cells", &irq_cells, sizeof(irq_cells)) == -1) { 237 device_printf(sc->dev, "DTB: Missing #interrupt-cells " 238 "property in interrupt parent node\n"); 239 return (ENXIO); 240 } 241 } 242 243 size = OF_getproplen(node, "interrupts"); 244 if (size != -1) { 245 size = size / sizeof(pcell_t); 246 size = size / irq_cells; 247 sc->irq_num = size; 248 device_printf(sc->dev, "%d IRQs available\n", sc->irq_num); 249 } else { 250 device_printf(sc->dev, "ERROR: no interrupts entry found!\n"); 251 return (ENXIO); 252 } 253 254 for (i = 0; i < sc->irq_num; i++) { 255 sc->irq_rid[i] = i; 256 sc->irq_res[i] = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, 257 &sc->irq_rid[i], RF_ACTIVE); 258 if (!sc->irq_res[i]) { 259 mtx_destroy(&sc->mutex); 260 device_printf(sc->dev, 261 "could not allocate gpio%d interrupt\n", i+1); 262 return (ENXIO); 263 } 264 } 265 266 device_printf(sc->dev, "Disable interrupts (offset = %x + EDGE(0x18)\n", sc->offset); 267 /* Disable all interrupts */ 268 bus_space_write_4(sc->bst, sc->bsh, sc->offset + GPIO_INT_EDGE_MASK, 0); 269 device_printf(sc->dev, "Disable interrupts (offset = %x + LEV(0x1C))\n", sc->offset); 270 bus_space_write_4(sc->bst, sc->bsh, sc->offset + GPIO_INT_LEV_MASK, 0); 271 272 for (i = 0; i < sc->irq_num; i++) { 273 device_printf(sc->dev, "Setup intr %d\n", i); 274 if (bus_setup_intr(sc->dev, sc->irq_res[i], 275 INTR_TYPE_MISC, 276 (driver_filter_t *)mv_gpio_intr, NULL, 277 sc, &sc->ih_cookie[i]) != 0) { 278 mtx_destroy(&sc->mutex); 279 bus_release_resource(sc->dev, SYS_RES_IRQ, 280 sc->irq_rid[i], sc->irq_res[i]); 281 device_printf(sc->dev, "could not set up intr %d\n", i); 282 return (ENXIO); 283 } 284 } 285 286 /* Clear interrupt status. */ 287 device_printf(sc->dev, "Clear int status (offset = %x)\n", sc->offset); 288 bus_space_write_4(sc->bst, sc->bsh, sc->offset + GPIO_INT_CAUSE, 0); 289 290 sc->debounce_callouts = (struct callout **)malloc(sc->pin_num * 291 sizeof(struct callout *), M_DEVBUF, M_WAITOK | M_ZERO); 292 if (sc->debounce_callouts == NULL) 293 return (ENOMEM); 294 295 sc->debounce_counters = (int *)malloc(sc->pin_num * sizeof(int), 296 M_DEVBUF, M_WAITOK); 297 if (sc->debounce_counters == NULL) 298 return (ENOMEM); 299 300 return (0); 301 } 302 303 static int 304 mv_gpio_attach(device_t dev) 305 { 306 int i, rv; 307 struct mv_gpio_softc *sc; 308 phandle_t node; 309 pcell_t pincnt = 0; 310 311 sc = (struct mv_gpio_softc *)device_get_softc(dev); 312 if (sc == NULL) 313 return (ENXIO); 314 315 node = ofw_bus_get_node(dev); 316 sc->dev = dev; 317 318 if (OF_getencprop(node, "pin-count", &pincnt, sizeof(pcell_t)) >= 0 || 319 OF_getencprop(node, "ngpios", &pincnt, sizeof(pcell_t)) >= 0) { 320 sc->pin_num = MIN(pincnt, MV_GPIO_MAX_NPINS); 321 if (bootverbose) 322 device_printf(dev, "%d pins available\n", sc->pin_num); 323 } else { 324 device_printf(dev, "ERROR: no pin-count or ngpios entry found!\n"); 325 return (ENXIO); 326 } 327 328 if (OF_getencprop(node, "offset", &sc->offset, sizeof(sc->offset)) == -1) 329 sc->offset = 0; 330 331 /* Assign generic capabilities to every gpio pin */ 332 for(i = 0; i < sc->pin_num; i++) 333 sc->gpio_setup[i].gp_caps = GPIO_GENERIC_CAP; 334 335 mtx_init(&sc->mutex, device_get_nameunit(dev), NULL, MTX_SPIN); 336 337 sc->mem_rid = 0; 338 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->mem_rid, 339 RF_ACTIVE | RF_SHAREABLE ); 340 341 if (!sc->mem_res) { 342 mtx_destroy(&sc->mutex); 343 device_printf(dev, "could not allocate memory window\n"); 344 return (ENXIO); 345 } 346 347 sc->bst = rman_get_bustag(sc->mem_res); 348 sc->bsh = rman_get_bushandle(sc->mem_res); 349 350 rv = mv_gpio_setup_interrupts(sc, node); 351 if (rv != 0) 352 return (rv); 353 354 sc->sc_busdev = gpiobus_attach_bus(dev); 355 if (sc->sc_busdev == NULL) { 356 mtx_destroy(&sc->mutex); 357 bus_release_resource(dev, SYS_RES_IRQ, 358 sc->irq_rid[i], sc->irq_res[i]); 359 return (ENXIO); 360 } 361 362 return (0); 363 } 364 365 static int 366 mv_gpio_intr(device_t dev, void *arg) 367 { 368 uint32_t int_cause, gpio_val; 369 struct mv_gpio_softc *sc; 370 sc = (struct mv_gpio_softc *)device_get_softc(dev); 371 372 MV_GPIO_LOCK(); 373 374 /* 375 * According to documentation, edge sensitive interrupts are asserted 376 * when unmasked GPIO_INT_CAUSE register bits are set. 377 */ 378 int_cause = mv_gpio_reg_read(dev, GPIO_INT_CAUSE); 379 int_cause &= mv_gpio_reg_read(dev, GPIO_INT_EDGE_MASK); 380 381 /* 382 * Level sensitive interrupts are asserted when unmasked GPIO_DATA_IN 383 * register bits are set. 384 */ 385 gpio_val = mv_gpio_reg_read(dev, GPIO_DATA_IN); 386 gpio_val &= mv_gpio_reg_read(dev, GPIO_INT_LEV_MASK); 387 388 mv_gpio_exec_intr_handlers(dev, int_cause | gpio_val, 0); 389 390 MV_GPIO_UNLOCK(); 391 392 return (FILTER_HANDLED); 393 } 394 395 /* 396 * GPIO interrupt handling 397 */ 398 399 void 400 mv_gpio_finish_intrhandler(struct mv_gpio_pindev *s) 401 { 402 /* When we acheive full interrupt support 403 * This function will be opposite to 404 * mv_gpio_setup_intrhandler 405 */ 406 407 /* Now it exists only to remind that 408 * there should be place to free mv_gpio_pindev 409 * allocated by mv_gpio_setup_intrhandler 410 */ 411 free(s, M_DEVBUF); 412 } 413 414 int 415 mv_gpio_setup_intrhandler(device_t dev, const char *name, driver_filter_t *filt, 416 void (*hand)(void *), void *arg, int pin, int flags, void **cookiep) 417 { 418 struct intr_event *event; 419 int error; 420 struct mv_gpio_pindev *s; 421 struct mv_gpio_softc *sc; 422 sc = (struct mv_gpio_softc *)device_get_softc(dev); 423 s = malloc(sizeof(struct mv_gpio_pindev), M_DEVBUF, M_NOWAIT | M_ZERO); 424 425 if (pin < 0 || pin >= sc->pin_num) 426 return (ENXIO); 427 event = sc->gpio_events[pin]; 428 if (event == NULL) { 429 MV_GPIO_LOCK(); 430 if (sc->gpio_setup[pin].gp_flags & MV_GPIO_IN_DEBOUNCE) { 431 error = mv_gpio_debounce_init(dev, pin); 432 if (error != 0) { 433 MV_GPIO_UNLOCK(); 434 return (error); 435 } 436 } else if (sc->gpio_setup[pin].gp_flags & MV_GPIO_IN_IRQ_DOUBLE_EDGE) 437 mv_gpio_double_edge_init(dev, pin); 438 MV_GPIO_UNLOCK(); 439 error = intr_event_create(&event, (void *)s, 0, pin, 440 (void (*)(void *))mv_gpio_intr_mask, 441 (void (*)(void *))mv_gpio_intr_unmask, 442 (void (*)(void *))mv_gpio_int_ack, 443 NULL, 444 "gpio%d:", pin); 445 if (error != 0) 446 return (error); 447 sc->gpio_events[pin] = event; 448 } 449 450 intr_event_add_handler(event, name, filt, hand, arg, 451 intr_priority(flags), flags, cookiep); 452 return (0); 453 } 454 455 static void 456 mv_gpio_intr_mask(struct mv_gpio_pindev *s) 457 { 458 struct mv_gpio_softc *sc; 459 sc = (struct mv_gpio_softc *)device_get_softc(s->dev); 460 461 if (s->pin >= sc->pin_num) 462 return; 463 464 MV_GPIO_LOCK(); 465 466 if (sc->gpio_setup[s->pin].gp_flags & (MV_GPIO_IN_IRQ_EDGE | 467 MV_GPIO_IN_IRQ_DOUBLE_EDGE)) 468 mv_gpio_edge(s->dev, s->pin, 0); 469 else 470 mv_gpio_level(s->dev, s->pin, 0); 471 472 /* 473 * The interrupt has to be acknowledged before scheduling an interrupt 474 * thread. This way we allow for interrupt source to trigger again 475 * (which can happen with shared IRQs e.g. PCI) while processing the 476 * current event. 477 */ 478 mv_gpio_int_ack(s); 479 480 MV_GPIO_UNLOCK(); 481 482 return; 483 } 484 485 static void 486 mv_gpio_intr_unmask(struct mv_gpio_pindev *s) 487 { 488 struct mv_gpio_softc *sc; 489 sc = (struct mv_gpio_softc *)device_get_softc(s->dev); 490 491 if (s->pin >= sc->pin_num) 492 return; 493 494 MV_GPIO_LOCK(); 495 496 if (sc->gpio_setup[s->pin].gp_flags & (MV_GPIO_IN_IRQ_EDGE | 497 MV_GPIO_IN_IRQ_DOUBLE_EDGE)) 498 mv_gpio_edge(s->dev, s->pin, 1); 499 else 500 mv_gpio_level(s->dev, s->pin, 1); 501 502 MV_GPIO_UNLOCK(); 503 504 return; 505 } 506 507 static void 508 mv_gpio_exec_intr_handlers(device_t dev, uint32_t status, int high) 509 { 510 int i, pin; 511 struct mv_gpio_softc *sc; 512 sc = (struct mv_gpio_softc *)device_get_softc(dev); 513 514 MV_GPIO_ASSERT_LOCKED(); 515 516 i = 0; 517 while (status != 0) { 518 if (status & 1) { 519 pin = (high ? (i + GPIO_PINS_PER_REG) : i); 520 if (sc->gpio_setup[pin].gp_flags & MV_GPIO_IN_DEBOUNCE) 521 mv_gpio_debounce_start(dev, pin); 522 else if (sc->gpio_setup[pin].gp_flags & MV_GPIO_IN_IRQ_DOUBLE_EDGE) { 523 mv_gpio_polarity(dev, pin, 0, 1); 524 mv_gpio_intr_handler(dev, pin); 525 } else 526 mv_gpio_intr_handler(dev, pin); 527 } 528 status >>= 1; 529 i++; 530 } 531 } 532 533 static void 534 mv_gpio_intr_handler(device_t dev, int pin) 535 { 536 #ifdef INTRNG 537 struct intr_irqsrc isrc; 538 struct mv_gpio_softc *sc; 539 sc = (struct mv_gpio_softc *)device_get_softc(dev); 540 541 MV_GPIO_ASSERT_LOCKED(); 542 543 #ifdef INTR_SOLO 544 isrc.isrc_filter = NULL; 545 #endif 546 isrc.isrc_event = sc->gpio_events[pin]; 547 548 if (isrc.isrc_event == NULL || 549 CK_SLIST_EMPTY(&isrc.isrc_event->ie_handlers)) 550 return; 551 552 intr_isrc_dispatch(&isrc, NULL); 553 #endif 554 } 555 556 int 557 mv_gpio_configure(device_t dev, uint32_t pin, uint32_t flags, uint32_t mask) 558 { 559 int error; 560 struct mv_gpio_softc *sc; 561 sc = (struct mv_gpio_softc *)device_get_softc(dev); 562 error = 0; 563 564 if (pin >= sc->pin_num) 565 return (EINVAL); 566 567 /* check flags consistency */ 568 if (((flags & mask) & (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT)) == 569 (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT)) 570 return (EINVAL); 571 572 if (mask & MV_GPIO_IN_DEBOUNCE) { 573 if (sc->irq_num == 0) 574 return (EINVAL); 575 error = mv_gpio_debounce_prepare(dev, pin); 576 if (error != 0) 577 return (error); 578 } 579 580 MV_GPIO_LOCK(); 581 582 if ((mask & flags) & GPIO_PIN_INPUT) 583 mv_gpio_out_en(dev, pin, 0); 584 if ((mask & flags) & GPIO_PIN_OUTPUT) { 585 if ((flags & mask) & GPIO_PIN_OPENDRAIN) 586 mv_gpio_value_set(dev, pin, 0); 587 else 588 mv_gpio_value_set(dev, pin, 1); 589 mv_gpio_out_en(dev, pin, 1); 590 } 591 592 if (mask & MV_GPIO_OUT_BLINK) 593 mv_gpio_blink(dev, pin, flags & MV_GPIO_OUT_BLINK); 594 if (mask & MV_GPIO_IN_POL_LOW) 595 mv_gpio_polarity(dev, pin, flags & MV_GPIO_IN_POL_LOW, 0); 596 if (mask & MV_GPIO_IN_DEBOUNCE) { 597 error = mv_gpio_debounce_setup(dev, pin); 598 if (error) { 599 MV_GPIO_UNLOCK(); 600 return (error); 601 } 602 } 603 604 sc->gpio_setup[pin].gp_flags &= ~(mask); 605 sc->gpio_setup[pin].gp_flags |= (flags & mask); 606 607 MV_GPIO_UNLOCK(); 608 609 return (0); 610 } 611 612 static void 613 mv_gpio_double_edge_init(device_t dev, int pin) 614 { 615 uint8_t raw_read; 616 struct mv_gpio_softc *sc; 617 sc = (struct mv_gpio_softc *)device_get_softc(dev); 618 619 MV_GPIO_ASSERT_LOCKED(); 620 621 raw_read = (mv_gpio_value_get(dev, pin, 1) ? 1 : 0); 622 623 if (raw_read) 624 mv_gpio_polarity(dev, pin, 1, 0); 625 else 626 mv_gpio_polarity(dev, pin, 0, 0); 627 } 628 629 static int 630 mv_gpio_debounce_setup(device_t dev, int pin) 631 { 632 struct callout *c; 633 struct mv_gpio_softc *sc; 634 635 sc = (struct mv_gpio_softc *)device_get_softc(dev); 636 637 MV_GPIO_ASSERT_LOCKED(); 638 639 c = sc->debounce_callouts[pin]; 640 if (c == NULL) 641 return (ENXIO); 642 643 if (callout_active(c)) 644 callout_deactivate(c); 645 646 callout_stop(c); 647 648 return (0); 649 } 650 651 static int 652 mv_gpio_debounce_prepare(device_t dev, int pin) 653 { 654 struct callout *c; 655 struct mv_gpio_softc *sc; 656 657 sc = (struct mv_gpio_softc *)device_get_softc(dev); 658 659 c = sc->debounce_callouts[pin]; 660 if (c == NULL) { 661 c = (struct callout *)malloc(sizeof(struct callout), 662 M_DEVBUF, M_WAITOK); 663 sc->debounce_callouts[pin] = c; 664 if (c == NULL) 665 return (ENOMEM); 666 callout_init(c, 1); 667 } 668 669 return (0); 670 } 671 672 static int 673 mv_gpio_debounce_init(device_t dev, int pin) 674 { 675 uint8_t raw_read; 676 int *cnt; 677 struct mv_gpio_softc *sc; 678 679 sc = (struct mv_gpio_softc *)device_get_softc(dev); 680 681 MV_GPIO_ASSERT_LOCKED(); 682 683 cnt = &sc->debounce_counters[pin]; 684 raw_read = (mv_gpio_value_get(dev, pin, 1) ? 1 : 0); 685 if (raw_read) { 686 mv_gpio_polarity(dev, pin, 1, 0); 687 *cnt = DEBOUNCE_HI_LO_MS / DEBOUNCE_CHECK_MS; 688 } else { 689 mv_gpio_polarity(dev, pin, 0, 0); 690 *cnt = DEBOUNCE_LO_HI_MS / DEBOUNCE_CHECK_MS; 691 } 692 693 mv_gpio_debounced_state_set(dev, pin, raw_read); 694 695 return (0); 696 } 697 698 static void 699 mv_gpio_debounce_start(device_t dev, int pin) 700 { 701 struct callout *c; 702 struct mv_gpio_pindev s = {dev, pin}; 703 struct mv_gpio_pindev *sd; 704 struct mv_gpio_softc *sc; 705 sc = (struct mv_gpio_softc *)device_get_softc(dev); 706 707 MV_GPIO_ASSERT_LOCKED(); 708 709 c = sc->debounce_callouts[pin]; 710 if (c == NULL) { 711 mv_gpio_int_ack(&s); 712 return; 713 } 714 715 if (callout_pending(c) || callout_active(c)) { 716 mv_gpio_int_ack(&s); 717 return; 718 } 719 720 sd = (struct mv_gpio_pindev *)malloc(sizeof(struct mv_gpio_pindev), 721 M_DEVBUF, M_WAITOK); 722 if (sd == NULL) { 723 mv_gpio_int_ack(&s); 724 return; 725 } 726 sd->pin = pin; 727 sd->dev = dev; 728 729 callout_reset(c, DEBOUNCE_CHECK_TICKS, mv_gpio_debounce, sd); 730 } 731 732 static void 733 mv_gpio_debounce(void *arg) 734 { 735 uint8_t raw_read, last_state; 736 int pin; 737 device_t dev; 738 int *debounce_counter; 739 struct mv_gpio_softc *sc; 740 struct mv_gpio_pindev *s; 741 742 s = (struct mv_gpio_pindev *)arg; 743 dev = s->dev; 744 pin = s->pin; 745 sc = (struct mv_gpio_softc *)device_get_softc(dev); 746 747 MV_GPIO_LOCK(); 748 749 raw_read = (mv_gpio_value_get(dev, pin, 1) ? 1 : 0); 750 last_state = (mv_gpio_debounced_state_get(dev, pin) ? 1 : 0); 751 debounce_counter = &sc->debounce_counters[pin]; 752 753 if (raw_read == last_state) { 754 if (last_state) 755 *debounce_counter = DEBOUNCE_HI_LO_MS / 756 DEBOUNCE_CHECK_MS; 757 else 758 *debounce_counter = DEBOUNCE_LO_HI_MS / 759 DEBOUNCE_CHECK_MS; 760 761 callout_reset(sc->debounce_callouts[pin], 762 DEBOUNCE_CHECK_TICKS, mv_gpio_debounce, arg); 763 } else { 764 *debounce_counter = *debounce_counter - 1; 765 if (*debounce_counter != 0) 766 callout_reset(sc->debounce_callouts[pin], 767 DEBOUNCE_CHECK_TICKS, mv_gpio_debounce, arg); 768 else { 769 mv_gpio_debounced_state_set(dev, pin, raw_read); 770 771 if (last_state) 772 *debounce_counter = DEBOUNCE_HI_LO_MS / 773 DEBOUNCE_CHECK_MS; 774 else 775 *debounce_counter = DEBOUNCE_LO_HI_MS / 776 DEBOUNCE_CHECK_MS; 777 778 if (((sc->gpio_setup[pin].gp_flags & MV_GPIO_IN_POL_LOW) && 779 (raw_read == 0)) || 780 (((sc->gpio_setup[pin].gp_flags & MV_GPIO_IN_POL_LOW) == 0) && 781 raw_read) || 782 (sc->gpio_setup[pin].gp_flags & MV_GPIO_IN_IRQ_DOUBLE_EDGE)) 783 mv_gpio_intr_handler(dev, pin); 784 785 /* Toggle polarity for next edge. */ 786 mv_gpio_polarity(dev, pin, 0, 1); 787 788 free(arg, M_DEVBUF); 789 callout_deactivate(sc->debounce_callouts[pin]); 790 } 791 } 792 793 MV_GPIO_UNLOCK(); 794 } 795 796 static void 797 mv_gpio_debounced_state_set(device_t dev, int pin, uint8_t new_state) 798 { 799 uint32_t *old_state; 800 struct mv_gpio_softc *sc; 801 sc = (struct mv_gpio_softc *)device_get_softc(dev); 802 803 MV_GPIO_ASSERT_LOCKED(); 804 805 if (pin >= GPIO_PINS_PER_REG) { 806 old_state = &sc->debounced_state_hi; 807 pin -= GPIO_PINS_PER_REG; 808 } else 809 old_state = &sc->debounced_state_lo; 810 811 if (new_state) 812 *old_state |= (1 << pin); 813 else 814 *old_state &= ~(1 << pin); 815 } 816 817 static uint32_t 818 mv_gpio_debounced_state_get(device_t dev, int pin) 819 { 820 uint32_t *state; 821 struct mv_gpio_softc *sc; 822 sc = (struct mv_gpio_softc *)device_get_softc(dev); 823 824 MV_GPIO_ASSERT_LOCKED(); 825 826 if (pin >= GPIO_PINS_PER_REG) { 827 state = &sc->debounced_state_hi; 828 pin -= GPIO_PINS_PER_REG; 829 } else 830 state = &sc->debounced_state_lo; 831 832 return (*state & (1 << pin)); 833 } 834 835 void 836 mv_gpio_out(device_t dev, uint32_t pin, uint8_t val, uint8_t enable) 837 { 838 struct mv_gpio_softc *sc; 839 sc = (struct mv_gpio_softc *)device_get_softc(dev); 840 841 MV_GPIO_LOCK(); 842 843 mv_gpio_value_set(dev, pin, val); 844 mv_gpio_out_en(dev, pin, enable); 845 846 MV_GPIO_UNLOCK(); 847 } 848 849 uint8_t 850 mv_gpio_in(device_t dev, uint32_t pin) 851 { 852 uint8_t state; 853 struct mv_gpio_softc *sc; 854 sc = (struct mv_gpio_softc *)device_get_softc(dev); 855 856 MV_GPIO_ASSERT_LOCKED(); 857 858 if (sc->gpio_setup[pin].gp_flags & MV_GPIO_IN_DEBOUNCE) { 859 if (sc->gpio_setup[pin].gp_flags & MV_GPIO_IN_POL_LOW) 860 state = (mv_gpio_debounced_state_get(dev, pin) ? 0 : 1); 861 else 862 state = (mv_gpio_debounced_state_get(dev, pin) ? 1 : 0); 863 } else if (sc->gpio_setup[pin].gp_flags & MV_GPIO_IN_IRQ_DOUBLE_EDGE) { 864 if (sc->gpio_setup[pin].gp_flags & MV_GPIO_IN_POL_LOW) 865 state = (mv_gpio_value_get(dev, pin, 1) ? 0 : 1); 866 else 867 state = (mv_gpio_value_get(dev, pin, 1) ? 1 : 0); 868 } else 869 state = (mv_gpio_value_get(dev, pin, 0) ? 1 : 0); 870 871 return (state); 872 } 873 874 static uint32_t 875 mv_gpio_reg_read(device_t dev, uint32_t reg) 876 { 877 struct mv_gpio_softc *sc; 878 sc = (struct mv_gpio_softc *)device_get_softc(dev); 879 880 return (bus_space_read_4(sc->bst, sc->bsh, sc->offset + reg)); 881 } 882 883 static void 884 mv_gpio_reg_write(device_t dev, uint32_t reg, uint32_t val) 885 { 886 struct mv_gpio_softc *sc; 887 sc = (struct mv_gpio_softc *)device_get_softc(dev); 888 889 bus_space_write_4(sc->bst, sc->bsh, sc->offset + reg, val); 890 } 891 892 static void 893 mv_gpio_reg_set(device_t dev, uint32_t reg, uint32_t pin) 894 { 895 uint32_t reg_val; 896 897 reg_val = mv_gpio_reg_read(dev, reg); 898 reg_val |= GPIO(pin); 899 mv_gpio_reg_write(dev, reg, reg_val); 900 } 901 902 static void 903 mv_gpio_reg_clear(device_t dev, uint32_t reg, uint32_t pin) 904 { 905 uint32_t reg_val; 906 907 reg_val = mv_gpio_reg_read(dev, reg); 908 reg_val &= ~(GPIO(pin)); 909 mv_gpio_reg_write(dev, reg, reg_val); 910 } 911 912 static void 913 mv_gpio_out_en(device_t dev, uint32_t pin, uint8_t enable) 914 { 915 uint32_t reg; 916 struct mv_gpio_softc *sc; 917 sc = (struct mv_gpio_softc *)device_get_softc(dev); 918 919 if (pin >= sc->pin_num) 920 return; 921 922 reg = GPIO_DATA_OUT_EN_CTRL; 923 924 if (enable) 925 mv_gpio_reg_clear(dev, reg, pin); 926 else 927 mv_gpio_reg_set(dev, reg, pin); 928 } 929 930 static void 931 mv_gpio_blink(device_t dev, uint32_t pin, uint8_t enable) 932 { 933 uint32_t reg; 934 struct mv_gpio_softc *sc; 935 sc = (struct mv_gpio_softc *)device_get_softc(dev); 936 937 if (pin >= sc->pin_num) 938 return; 939 940 reg = GPIO_BLINK_EN; 941 942 if (enable) 943 mv_gpio_reg_set(dev, reg, pin); 944 else 945 mv_gpio_reg_clear(dev, reg, pin); 946 } 947 948 static void 949 mv_gpio_polarity(device_t dev, uint32_t pin, uint8_t enable, uint8_t toggle) 950 { 951 uint32_t reg, reg_val; 952 struct mv_gpio_softc *sc; 953 sc = (struct mv_gpio_softc *)device_get_softc(dev); 954 955 if (pin >= sc->pin_num) 956 return; 957 958 reg = GPIO_DATA_IN_POLAR; 959 960 if (toggle) { 961 reg_val = mv_gpio_reg_read(dev, reg) & GPIO(pin); 962 if (reg_val) 963 mv_gpio_reg_clear(dev, reg, pin); 964 else 965 mv_gpio_reg_set(dev, reg, pin); 966 } else if (enable) 967 mv_gpio_reg_set(dev, reg, pin); 968 else 969 mv_gpio_reg_clear(dev, reg, pin); 970 } 971 972 static void 973 mv_gpio_level(device_t dev, uint32_t pin, uint8_t enable) 974 { 975 uint32_t reg; 976 struct mv_gpio_softc *sc; 977 sc = (struct mv_gpio_softc *)device_get_softc(dev); 978 979 if (pin >= sc->pin_num) 980 return; 981 982 reg = GPIO_INT_LEV_MASK; 983 984 if (enable) 985 mv_gpio_reg_set(dev, reg, pin); 986 else 987 mv_gpio_reg_clear(dev, reg, pin); 988 } 989 990 static void 991 mv_gpio_edge(device_t dev, uint32_t pin, uint8_t enable) 992 { 993 uint32_t reg; 994 struct mv_gpio_softc *sc; 995 sc = (struct mv_gpio_softc *)device_get_softc(dev); 996 997 if (pin >= sc->pin_num) 998 return; 999 1000 reg = GPIO_INT_EDGE_MASK; 1001 1002 if (enable) 1003 mv_gpio_reg_set(dev, reg, pin); 1004 else 1005 mv_gpio_reg_clear(dev, reg, pin); 1006 } 1007 1008 static void 1009 mv_gpio_int_ack(struct mv_gpio_pindev *s) 1010 { 1011 uint32_t reg, pin; 1012 struct mv_gpio_softc *sc; 1013 sc = (struct mv_gpio_softc *)device_get_softc(s->dev); 1014 pin = s->pin; 1015 1016 if (pin >= sc->pin_num) 1017 return; 1018 1019 reg = GPIO_INT_CAUSE; 1020 1021 mv_gpio_reg_clear(s->dev, reg, pin); 1022 } 1023 1024 static uint32_t 1025 mv_gpio_value_get(device_t dev, uint32_t pin, uint8_t exclude_polar) 1026 { 1027 uint32_t reg, polar_reg, reg_val, polar_reg_val; 1028 struct mv_gpio_softc *sc; 1029 sc = (struct mv_gpio_softc *)device_get_softc(dev); 1030 1031 if (pin >= sc->pin_num) 1032 return (0); 1033 1034 reg = GPIO_DATA_IN; 1035 polar_reg = GPIO_DATA_IN_POLAR; 1036 1037 reg_val = mv_gpio_reg_read(dev, reg); 1038 1039 if (exclude_polar) { 1040 polar_reg_val = mv_gpio_reg_read(dev, polar_reg); 1041 return ((reg_val & GPIO(pin)) ^ (polar_reg_val & GPIO(pin))); 1042 } else 1043 return (reg_val & GPIO(pin)); 1044 } 1045 1046 static void 1047 mv_gpio_value_set(device_t dev, uint32_t pin, uint8_t val) 1048 { 1049 uint32_t reg; 1050 struct mv_gpio_softc *sc; 1051 sc = (struct mv_gpio_softc *)device_get_softc(dev); 1052 1053 MV_GPIO_ASSERT_LOCKED(); 1054 1055 if (pin >= sc->pin_num) 1056 return; 1057 1058 reg = GPIO_DATA_OUT; 1059 1060 if (val) 1061 mv_gpio_reg_set(dev, reg, pin); 1062 else 1063 mv_gpio_reg_clear(dev, reg, pin); 1064 } 1065 1066 /* 1067 * GPIO interface methods 1068 */ 1069 1070 static int 1071 mv_gpio_pin_max(device_t dev, int *maxpin) 1072 { 1073 struct mv_gpio_softc *sc; 1074 if (maxpin == NULL) 1075 return (EINVAL); 1076 1077 sc = device_get_softc(dev); 1078 *maxpin = sc->pin_num; 1079 1080 return (0); 1081 } 1082 1083 static int 1084 mv_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps) 1085 { 1086 struct mv_gpio_softc *sc = device_get_softc(dev); 1087 if (caps == NULL) 1088 return (EINVAL); 1089 1090 if (pin >= sc->pin_num) 1091 return (EINVAL); 1092 1093 MV_GPIO_LOCK(); 1094 *caps = sc->gpio_setup[pin].gp_caps; 1095 MV_GPIO_UNLOCK(); 1096 1097 return (0); 1098 } 1099 1100 static int 1101 mv_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags) 1102 { 1103 struct mv_gpio_softc *sc = device_get_softc(dev); 1104 if (flags == NULL) 1105 return (EINVAL); 1106 1107 if (pin >= sc->pin_num) 1108 return (EINVAL); 1109 1110 MV_GPIO_LOCK(); 1111 *flags = sc->gpio_setup[pin].gp_flags; 1112 MV_GPIO_UNLOCK(); 1113 1114 return (0); 1115 } 1116 1117 static int 1118 mv_gpio_pin_getname(device_t dev, uint32_t pin, char *name) 1119 { 1120 struct mv_gpio_softc *sc = device_get_softc(dev); 1121 if (name == NULL) 1122 return (EINVAL); 1123 1124 if (pin >= sc->pin_num) 1125 return (EINVAL); 1126 1127 MV_GPIO_LOCK(); 1128 memcpy(name, sc->gpio_setup[pin].gp_name, GPIOMAXNAME); 1129 MV_GPIO_UNLOCK(); 1130 1131 return (0); 1132 } 1133 1134 static int 1135 mv_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags) 1136 { 1137 int ret; 1138 struct mv_gpio_softc *sc = device_get_softc(dev); 1139 if (pin >= sc->pin_num) 1140 return (EINVAL); 1141 1142 /* Check for unwanted flags. */ 1143 if ((flags & sc->gpio_setup[pin].gp_caps) != flags) 1144 return (EINVAL); 1145 1146 ret = mv_gpio_configure(dev, pin, flags, ~0); 1147 1148 return (ret); 1149 } 1150 1151 static int 1152 mv_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value) 1153 { 1154 struct mv_gpio_softc *sc = device_get_softc(dev); 1155 if (pin >= sc->pin_num) 1156 return (EINVAL); 1157 1158 MV_GPIO_LOCK(); 1159 mv_gpio_value_set(dev, pin, value); 1160 MV_GPIO_UNLOCK(); 1161 1162 return (0); 1163 } 1164 1165 static int 1166 mv_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *value) 1167 { 1168 struct mv_gpio_softc *sc = device_get_softc(dev); 1169 if (value == NULL) 1170 return (EINVAL); 1171 1172 if (pin >= sc->pin_num) 1173 return (EINVAL); 1174 1175 MV_GPIO_LOCK(); 1176 *value = mv_gpio_in(dev, pin); 1177 MV_GPIO_UNLOCK(); 1178 1179 return (0); 1180 } 1181 1182 static int 1183 mv_gpio_pin_toggle(device_t dev, uint32_t pin) 1184 { 1185 struct mv_gpio_softc *sc = device_get_softc(dev); 1186 uint32_t value; 1187 if (pin >= sc->pin_num) 1188 return (EINVAL); 1189 1190 MV_GPIO_LOCK(); 1191 value = mv_gpio_in(dev, pin); 1192 value = (~value) & 1; 1193 mv_gpio_value_set(dev, pin, value); 1194 MV_GPIO_UNLOCK(); 1195 1196 return (0); 1197 } 1198 1199 static device_t 1200 mv_gpio_get_bus(device_t dev) 1201 { 1202 struct mv_gpio_softc *sc = device_get_softc(dev); 1203 1204 return (sc->sc_busdev); 1205 } 1206 1207 static int 1208 mv_gpio_map_gpios(device_t bus, phandle_t dev, phandle_t gparent, int gcells, 1209 pcell_t *gpios, uint32_t *pin, uint32_t *flags) 1210 { 1211 struct mv_gpio_softc *sc = device_get_softc(bus); 1212 1213 if (gpios[0] >= sc->pin_num) 1214 return (EINVAL); 1215 1216 *pin = gpios[0]; 1217 *flags = gpios[1]; 1218 mv_gpio_configure(bus, *pin, *flags, ~0); 1219 1220 return (0); 1221 } 1222