1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2006 Benno Rice. 5 * Copyright (C) 2008 MARVELL INTERNATIONAL LTD. 6 * Copyright (c) 2017 Semihalf. 7 * All rights reserved. 8 * 9 * Adapted and extended for Marvell SoCs by Semihalf. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 * 31 * from: FreeBSD: //depot/projects/arm/src/sys/arm/xscale/pxa2x0/pxa2x0_gpio.c, rev 1 32 */ 33 34 #include <sys/cdefs.h> 35 __FBSDID("$FreeBSD$"); 36 37 #include <sys/param.h> 38 #include <sys/systm.h> 39 #include <sys/bus.h> 40 #include <sys/kernel.h> 41 #include <sys/lock.h> 42 #include <sys/interrupt.h> 43 #include <sys/module.h> 44 #include <sys/malloc.h> 45 #include <sys/mutex.h> 46 #include <sys/rman.h> 47 #include <sys/queue.h> 48 #include <sys/timetc.h> 49 #include <sys/callout.h> 50 #include <sys/gpio.h> 51 #include <machine/bus.h> 52 #include <machine/intr.h> 53 54 #include <dev/gpio/gpiobusvar.h> 55 #include <dev/ofw/ofw_bus.h> 56 #include <dev/ofw/ofw_bus_subr.h> 57 58 #include <arm/mv/mvvar.h> 59 #include <arm/mv/mvreg.h> 60 61 #include "gpio_if.h" 62 63 #define GPIO_MAX_INTR_COUNT 8 64 #define GPIO_PINS_PER_REG 32 65 #define GPIO_GENERIC_CAP (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT | \ 66 GPIO_PIN_OPENDRAIN | GPIO_PIN_PUSHPULL | \ 67 GPIO_PIN_TRISTATE | GPIO_PIN_PULLUP | \ 68 GPIO_PIN_PULLDOWN | GPIO_PIN_INVIN | \ 69 GPIO_PIN_INVOUT) 70 71 #define DEBOUNCE_CHECK_MS 1 72 #define DEBOUNCE_LO_HI_MS 2 73 #define DEBOUNCE_HI_LO_MS 2 74 #define DEBOUNCE_CHECK_TICKS ((hz / 1000) * DEBOUNCE_CHECK_MS) 75 76 struct mv_gpio_softc { 77 device_t dev; 78 device_t sc_busdev; 79 struct resource * mem_res; 80 int mem_rid; 81 struct resource * irq_res[GPIO_MAX_INTR_COUNT]; 82 int irq_rid[GPIO_MAX_INTR_COUNT]; 83 struct intr_event * gpio_events[MV_GPIO_MAX_NPINS]; 84 void *ih_cookie[GPIO_MAX_INTR_COUNT]; 85 bus_space_tag_t bst; 86 bus_space_handle_t bsh; 87 uint32_t offset; 88 struct mtx mutex; 89 uint8_t pin_num; /* number of GPIO pins */ 90 uint8_t irq_num; /* number of real IRQs occupied by GPIO controller */ 91 struct gpio_pin gpio_setup[MV_GPIO_MAX_NPINS]; 92 93 /* Used for debouncing. */ 94 uint32_t debounced_state_lo; 95 uint32_t debounced_state_hi; 96 struct callout **debounce_callouts; 97 int *debounce_counters; 98 }; 99 100 struct mv_gpio_pindev { 101 device_t dev; 102 int pin; 103 }; 104 105 static int mv_gpio_probe(device_t); 106 static int mv_gpio_attach(device_t); 107 static int mv_gpio_intr(device_t, void *); 108 109 static void mv_gpio_double_edge_init(device_t, int); 110 111 static int mv_gpio_debounce_setup(device_t, int); 112 static int mv_gpio_debounce_prepare(device_t, int); 113 static int mv_gpio_debounce_init(device_t, int); 114 static void mv_gpio_debounce_start(device_t, int); 115 static void mv_gpio_debounce(void *); 116 static void mv_gpio_debounced_state_set(device_t, int, uint8_t); 117 static uint32_t mv_gpio_debounced_state_get(device_t, int); 118 119 static void mv_gpio_exec_intr_handlers(device_t, uint32_t, int); 120 static void mv_gpio_intr_handler(device_t, int); 121 static uint32_t mv_gpio_reg_read(device_t, uint32_t); 122 static void mv_gpio_reg_write(device_t, uint32_t, uint32_t); 123 static void mv_gpio_reg_set(device_t, uint32_t, uint32_t); 124 static void mv_gpio_reg_clear(device_t, uint32_t, uint32_t); 125 126 static void mv_gpio_blink(device_t, uint32_t, uint8_t); 127 static void mv_gpio_polarity(device_t, uint32_t, uint8_t, uint8_t); 128 static void mv_gpio_level(device_t, uint32_t, uint8_t); 129 static void mv_gpio_edge(device_t, uint32_t, uint8_t); 130 static void mv_gpio_out_en(device_t, uint32_t, uint8_t); 131 static void mv_gpio_int_ack(struct mv_gpio_pindev *); 132 static void mv_gpio_value_set(device_t, uint32_t, uint8_t); 133 static uint32_t mv_gpio_value_get(device_t, uint32_t, uint8_t); 134 135 static void mv_gpio_intr_mask(struct mv_gpio_pindev *); 136 static void mv_gpio_intr_unmask(struct mv_gpio_pindev *); 137 138 void mv_gpio_finish_intrhandler(struct mv_gpio_pindev *); 139 int mv_gpio_setup_intrhandler(device_t, const char *, 140 driver_filter_t *, void (*)(void *), void *, 141 int, int, void **); 142 int mv_gpio_configure(device_t, uint32_t, uint32_t, uint32_t); 143 void mv_gpio_out(device_t, uint32_t, uint8_t, uint8_t); 144 uint8_t mv_gpio_in(device_t, uint32_t); 145 146 /* 147 * GPIO interface 148 */ 149 static device_t mv_gpio_get_bus(device_t); 150 static int mv_gpio_pin_max(device_t, int *); 151 static int mv_gpio_pin_getcaps(device_t, uint32_t, uint32_t *); 152 static int mv_gpio_pin_getflags(device_t, uint32_t, uint32_t *); 153 static int mv_gpio_pin_getname(device_t, uint32_t, char *); 154 static int mv_gpio_pin_setflags(device_t, uint32_t, uint32_t); 155 static int mv_gpio_pin_set(device_t, uint32_t, unsigned int); 156 static int mv_gpio_pin_get(device_t, uint32_t, unsigned int *); 157 static int mv_gpio_pin_toggle(device_t, uint32_t); 158 static int mv_gpio_map_gpios(device_t, phandle_t, phandle_t, 159 int, pcell_t *, uint32_t *, uint32_t *); 160 161 #define MV_GPIO_LOCK() mtx_lock_spin(&sc->mutex) 162 #define MV_GPIO_UNLOCK() mtx_unlock_spin(&sc->mutex) 163 #define MV_GPIO_ASSERT_LOCKED() mtx_assert(&sc->mutex, MA_OWNED) 164 165 static device_method_t mv_gpio_methods[] = { 166 DEVMETHOD(device_probe, mv_gpio_probe), 167 DEVMETHOD(device_attach, mv_gpio_attach), 168 169 /* GPIO protocol */ 170 DEVMETHOD(gpio_get_bus, mv_gpio_get_bus), 171 DEVMETHOD(gpio_pin_max, mv_gpio_pin_max), 172 DEVMETHOD(gpio_pin_getname, mv_gpio_pin_getname), 173 DEVMETHOD(gpio_pin_getflags, mv_gpio_pin_getflags), 174 DEVMETHOD(gpio_pin_getcaps, mv_gpio_pin_getcaps), 175 DEVMETHOD(gpio_pin_setflags, mv_gpio_pin_setflags), 176 DEVMETHOD(gpio_pin_get, mv_gpio_pin_get), 177 DEVMETHOD(gpio_pin_set, mv_gpio_pin_set), 178 DEVMETHOD(gpio_pin_toggle, mv_gpio_pin_toggle), 179 DEVMETHOD(gpio_map_gpios, mv_gpio_map_gpios), 180 181 DEVMETHOD_END 182 }; 183 184 static driver_t mv_gpio_driver = { 185 "gpio", 186 mv_gpio_methods, 187 sizeof(struct mv_gpio_softc), 188 }; 189 190 static devclass_t mv_gpio_devclass; 191 192 EARLY_DRIVER_MODULE(mv_gpio, simplebus, mv_gpio_driver, mv_gpio_devclass, 0, 0, 193 BUS_PASS_INTERRUPT + BUS_PASS_ORDER_LAST); 194 195 struct ofw_compat_data compat_data[] = { 196 { "mrvl,gpio", 1 }, 197 { "marvell,orion-gpio", 1 }, 198 { NULL, 0 } 199 }; 200 201 static int 202 mv_gpio_probe(device_t dev) 203 { 204 if (!ofw_bus_status_okay(dev)) 205 return (ENXIO); 206 207 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) 208 return (ENXIO); 209 210 device_set_desc(dev, "Marvell Integrated GPIO Controller"); 211 return (0); 212 } 213 214 static int 215 mv_gpio_setup_interrupts(struct mv_gpio_softc *sc, phandle_t node) 216 { 217 phandle_t iparent; 218 pcell_t irq_cells; 219 int i, size; 220 221 /* Find root interrupt controller */ 222 iparent = ofw_bus_find_iparent(node); 223 if (iparent == 0) { 224 device_printf(sc->dev, "No interrupt-parrent found. " 225 "Error in DTB\n"); 226 return (ENXIO); 227 } else { 228 /* While at parent - store interrupt cells prop */ 229 if (OF_searchencprop(OF_node_from_xref(iparent), 230 "#interrupt-cells", &irq_cells, sizeof(irq_cells)) == -1) { 231 device_printf(sc->dev, "DTB: Missing #interrupt-cells " 232 "property in interrupt parent node\n"); 233 return (ENXIO); 234 } 235 } 236 237 size = OF_getproplen(node, "interrupts"); 238 if (size != -1) { 239 size = size / sizeof(pcell_t); 240 size = size / irq_cells; 241 sc->irq_num = size; 242 device_printf(sc->dev, "%d IRQs available\n", sc->irq_num); 243 } else { 244 device_printf(sc->dev, "ERROR: no interrupts entry found!\n"); 245 return (ENXIO); 246 } 247 248 for (i = 0; i < sc->irq_num; i++) { 249 sc->irq_rid[i] = i; 250 sc->irq_res[i] = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, 251 &sc->irq_rid[i], RF_ACTIVE); 252 if (!sc->irq_res[i]) { 253 mtx_destroy(&sc->mutex); 254 device_printf(sc->dev, 255 "could not allocate gpio%d interrupt\n", i+1); 256 return (ENXIO); 257 } 258 } 259 260 device_printf(sc->dev, "Disable interrupts (offset = %x + EDGE(0x18)\n", sc->offset); 261 /* Disable all interrupts */ 262 bus_space_write_4(sc->bst, sc->bsh, sc->offset + GPIO_INT_EDGE_MASK, 0); 263 device_printf(sc->dev, "Disable interrupts (offset = %x + LEV(0x1C))\n", sc->offset); 264 bus_space_write_4(sc->bst, sc->bsh, sc->offset + GPIO_INT_LEV_MASK, 0); 265 266 for (i = 0; i < sc->irq_num; i++) { 267 device_printf(sc->dev, "Setup intr %d\n", i); 268 if (bus_setup_intr(sc->dev, sc->irq_res[i], 269 INTR_TYPE_MISC, 270 (driver_filter_t *)mv_gpio_intr, NULL, 271 sc, &sc->ih_cookie[i]) != 0) { 272 mtx_destroy(&sc->mutex); 273 bus_release_resource(sc->dev, SYS_RES_IRQ, 274 sc->irq_rid[i], sc->irq_res[i]); 275 device_printf(sc->dev, "could not set up intr %d\n", i); 276 return (ENXIO); 277 } 278 } 279 280 /* Clear interrupt status. */ 281 device_printf(sc->dev, "Clear int status (offset = %x)\n", sc->offset); 282 bus_space_write_4(sc->bst, sc->bsh, sc->offset + GPIO_INT_CAUSE, 0); 283 284 sc->debounce_callouts = (struct callout **)malloc(sc->pin_num * 285 sizeof(struct callout *), M_DEVBUF, M_WAITOK | M_ZERO); 286 if (sc->debounce_callouts == NULL) 287 return (ENOMEM); 288 289 sc->debounce_counters = (int *)malloc(sc->pin_num * sizeof(int), 290 M_DEVBUF, M_WAITOK); 291 if (sc->debounce_counters == NULL) 292 return (ENOMEM); 293 294 return (0); 295 } 296 297 static int 298 mv_gpio_attach(device_t dev) 299 { 300 int i, rv; 301 struct mv_gpio_softc *sc; 302 phandle_t node; 303 pcell_t pincnt = 0; 304 305 sc = (struct mv_gpio_softc *)device_get_softc(dev); 306 if (sc == NULL) 307 return (ENXIO); 308 309 node = ofw_bus_get_node(dev); 310 sc->dev = dev; 311 312 if (OF_getencprop(node, "pin-count", &pincnt, sizeof(pcell_t)) >= 0 || 313 OF_getencprop(node, "ngpios", &pincnt, sizeof(pcell_t)) >= 0) { 314 sc->pin_num = MIN(pincnt, MV_GPIO_MAX_NPINS); 315 if (bootverbose) 316 device_printf(dev, "%d pins available\n", sc->pin_num); 317 } else { 318 device_printf(dev, "ERROR: no pin-count or ngpios entry found!\n"); 319 return (ENXIO); 320 } 321 322 if (OF_getencprop(node, "offset", &sc->offset, sizeof(sc->offset)) == -1) 323 sc->offset = 0; 324 325 /* Assign generic capabilities to every gpio pin */ 326 for(i = 0; i < sc->pin_num; i++) 327 sc->gpio_setup[i].gp_caps = GPIO_GENERIC_CAP; 328 329 mtx_init(&sc->mutex, device_get_nameunit(dev), NULL, MTX_SPIN); 330 331 sc->mem_rid = 0; 332 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->mem_rid, 333 RF_ACTIVE | RF_SHAREABLE ); 334 335 if (!sc->mem_res) { 336 mtx_destroy(&sc->mutex); 337 device_printf(dev, "could not allocate memory window\n"); 338 return (ENXIO); 339 } 340 341 sc->bst = rman_get_bustag(sc->mem_res); 342 sc->bsh = rman_get_bushandle(sc->mem_res); 343 344 rv = mv_gpio_setup_interrupts(sc, node); 345 if (rv != 0) 346 return (rv); 347 348 sc->sc_busdev = gpiobus_attach_bus(dev); 349 if (sc->sc_busdev == NULL) { 350 mtx_destroy(&sc->mutex); 351 bus_release_resource(dev, SYS_RES_IRQ, 352 sc->irq_rid[i], sc->irq_res[i]); 353 return (ENXIO); 354 } 355 356 return (0); 357 } 358 359 static int 360 mv_gpio_intr(device_t dev, void *arg) 361 { 362 uint32_t int_cause, gpio_val; 363 struct mv_gpio_softc *sc; 364 sc = (struct mv_gpio_softc *)device_get_softc(dev); 365 366 MV_GPIO_LOCK(); 367 368 /* 369 * According to documentation, edge sensitive interrupts are asserted 370 * when unmasked GPIO_INT_CAUSE register bits are set. 371 */ 372 int_cause = mv_gpio_reg_read(dev, GPIO_INT_CAUSE); 373 int_cause &= mv_gpio_reg_read(dev, GPIO_INT_EDGE_MASK); 374 375 /* 376 * Level sensitive interrupts are asserted when unmasked GPIO_DATA_IN 377 * register bits are set. 378 */ 379 gpio_val = mv_gpio_reg_read(dev, GPIO_DATA_IN); 380 gpio_val &= mv_gpio_reg_read(dev, GPIO_INT_LEV_MASK); 381 382 mv_gpio_exec_intr_handlers(dev, int_cause | gpio_val, 0); 383 384 MV_GPIO_UNLOCK(); 385 386 return (FILTER_HANDLED); 387 } 388 389 /* 390 * GPIO interrupt handling 391 */ 392 393 void 394 mv_gpio_finish_intrhandler(struct mv_gpio_pindev *s) 395 { 396 /* When we acheive full interrupt support 397 * This function will be opposite to 398 * mv_gpio_setup_intrhandler 399 */ 400 401 /* Now it exists only to remind that 402 * there should be place to free mv_gpio_pindev 403 * allocated by mv_gpio_setup_intrhandler 404 */ 405 free(s, M_DEVBUF); 406 } 407 408 int 409 mv_gpio_setup_intrhandler(device_t dev, const char *name, driver_filter_t *filt, 410 void (*hand)(void *), void *arg, int pin, int flags, void **cookiep) 411 { 412 struct intr_event *event; 413 int error; 414 struct mv_gpio_pindev *s; 415 struct mv_gpio_softc *sc; 416 sc = (struct mv_gpio_softc *)device_get_softc(dev); 417 s = malloc(sizeof(struct mv_gpio_pindev), M_DEVBUF, M_NOWAIT | M_ZERO); 418 419 if (pin < 0 || pin >= sc->pin_num) 420 return (ENXIO); 421 event = sc->gpio_events[pin]; 422 if (event == NULL) { 423 MV_GPIO_LOCK(); 424 if (sc->gpio_setup[pin].gp_flags & MV_GPIO_IN_DEBOUNCE) { 425 error = mv_gpio_debounce_init(dev, pin); 426 if (error != 0) { 427 MV_GPIO_UNLOCK(); 428 return (error); 429 } 430 } else if (sc->gpio_setup[pin].gp_flags & MV_GPIO_IN_IRQ_DOUBLE_EDGE) 431 mv_gpio_double_edge_init(dev, pin); 432 MV_GPIO_UNLOCK(); 433 error = intr_event_create(&event, (void *)s, 0, pin, 434 (void (*)(void *))mv_gpio_intr_mask, 435 (void (*)(void *))mv_gpio_intr_unmask, 436 (void (*)(void *))mv_gpio_int_ack, 437 NULL, 438 "gpio%d:", pin); 439 if (error != 0) 440 return (error); 441 sc->gpio_events[pin] = event; 442 } 443 444 intr_event_add_handler(event, name, filt, hand, arg, 445 intr_priority(flags), flags, cookiep); 446 return (0); 447 } 448 449 static void 450 mv_gpio_intr_mask(struct mv_gpio_pindev *s) 451 { 452 struct mv_gpio_softc *sc; 453 sc = (struct mv_gpio_softc *)device_get_softc(s->dev); 454 455 if (s->pin >= sc->pin_num) 456 return; 457 458 MV_GPIO_LOCK(); 459 460 if (sc->gpio_setup[s->pin].gp_flags & (MV_GPIO_IN_IRQ_EDGE | 461 MV_GPIO_IN_IRQ_DOUBLE_EDGE)) 462 mv_gpio_edge(s->dev, s->pin, 0); 463 else 464 mv_gpio_level(s->dev, s->pin, 0); 465 466 /* 467 * The interrupt has to be acknowledged before scheduling an interrupt 468 * thread. This way we allow for interrupt source to trigger again 469 * (which can happen with shared IRQs e.g. PCI) while processing the 470 * current event. 471 */ 472 mv_gpio_int_ack(s); 473 474 MV_GPIO_UNLOCK(); 475 476 return; 477 } 478 479 static void 480 mv_gpio_intr_unmask(struct mv_gpio_pindev *s) 481 { 482 struct mv_gpio_softc *sc; 483 sc = (struct mv_gpio_softc *)device_get_softc(s->dev); 484 485 if (s->pin >= sc->pin_num) 486 return; 487 488 MV_GPIO_LOCK(); 489 490 if (sc->gpio_setup[s->pin].gp_flags & (MV_GPIO_IN_IRQ_EDGE | 491 MV_GPIO_IN_IRQ_DOUBLE_EDGE)) 492 mv_gpio_edge(s->dev, s->pin, 1); 493 else 494 mv_gpio_level(s->dev, s->pin, 1); 495 496 MV_GPIO_UNLOCK(); 497 498 return; 499 } 500 501 static void 502 mv_gpio_exec_intr_handlers(device_t dev, uint32_t status, int high) 503 { 504 int i, pin; 505 struct mv_gpio_softc *sc; 506 sc = (struct mv_gpio_softc *)device_get_softc(dev); 507 508 MV_GPIO_ASSERT_LOCKED(); 509 510 i = 0; 511 while (status != 0) { 512 if (status & 1) { 513 pin = (high ? (i + GPIO_PINS_PER_REG) : i); 514 if (sc->gpio_setup[pin].gp_flags & MV_GPIO_IN_DEBOUNCE) 515 mv_gpio_debounce_start(dev, pin); 516 else if (sc->gpio_setup[pin].gp_flags & MV_GPIO_IN_IRQ_DOUBLE_EDGE) { 517 mv_gpio_polarity(dev, pin, 0, 1); 518 mv_gpio_intr_handler(dev, pin); 519 } else 520 mv_gpio_intr_handler(dev, pin); 521 } 522 status >>= 1; 523 i++; 524 } 525 } 526 527 static void 528 mv_gpio_intr_handler(device_t dev, int pin) 529 { 530 #ifdef INTRNG 531 struct intr_irqsrc isrc; 532 struct mv_gpio_softc *sc; 533 sc = (struct mv_gpio_softc *)device_get_softc(dev); 534 535 MV_GPIO_ASSERT_LOCKED(); 536 537 #ifdef INTR_SOLO 538 isrc.isrc_filter = NULL; 539 #endif 540 isrc.isrc_event = sc->gpio_events[pin]; 541 542 if (isrc.isrc_event == NULL || 543 CK_SLIST_EMPTY(&isrc.isrc_event->ie_handlers)) 544 return; 545 546 intr_isrc_dispatch(&isrc, NULL); 547 #endif 548 } 549 550 int 551 mv_gpio_configure(device_t dev, uint32_t pin, uint32_t flags, uint32_t mask) 552 { 553 int error; 554 struct mv_gpio_softc *sc; 555 sc = (struct mv_gpio_softc *)device_get_softc(dev); 556 error = 0; 557 558 if (pin >= sc->pin_num) 559 return (EINVAL); 560 561 /* check flags consistency */ 562 if (((flags & mask) & (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT)) == 563 (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT)) 564 return (EINVAL); 565 566 if (mask & MV_GPIO_IN_DEBOUNCE) { 567 if (sc->irq_num == 0) 568 return (EINVAL); 569 error = mv_gpio_debounce_prepare(dev, pin); 570 if (error != 0) 571 return (error); 572 } 573 574 MV_GPIO_LOCK(); 575 576 if ((mask & flags) & GPIO_PIN_INPUT) 577 mv_gpio_out_en(dev, pin, 0); 578 if ((mask & flags) & GPIO_PIN_OUTPUT) { 579 if ((flags & mask) & GPIO_PIN_OPENDRAIN) 580 mv_gpio_value_set(dev, pin, 0); 581 else 582 mv_gpio_value_set(dev, pin, 1); 583 mv_gpio_out_en(dev, pin, 1); 584 } 585 586 if (mask & MV_GPIO_OUT_BLINK) 587 mv_gpio_blink(dev, pin, flags & MV_GPIO_OUT_BLINK); 588 if (mask & MV_GPIO_IN_POL_LOW) 589 mv_gpio_polarity(dev, pin, flags & MV_GPIO_IN_POL_LOW, 0); 590 if (mask & MV_GPIO_IN_DEBOUNCE) { 591 error = mv_gpio_debounce_setup(dev, pin); 592 if (error) { 593 MV_GPIO_UNLOCK(); 594 return (error); 595 } 596 } 597 598 sc->gpio_setup[pin].gp_flags &= ~(mask); 599 sc->gpio_setup[pin].gp_flags |= (flags & mask); 600 601 MV_GPIO_UNLOCK(); 602 603 return (0); 604 } 605 606 static void 607 mv_gpio_double_edge_init(device_t dev, int pin) 608 { 609 uint8_t raw_read; 610 struct mv_gpio_softc *sc; 611 sc = (struct mv_gpio_softc *)device_get_softc(dev); 612 613 MV_GPIO_ASSERT_LOCKED(); 614 615 raw_read = (mv_gpio_value_get(dev, pin, 1) ? 1 : 0); 616 617 if (raw_read) 618 mv_gpio_polarity(dev, pin, 1, 0); 619 else 620 mv_gpio_polarity(dev, pin, 0, 0); 621 } 622 623 static int 624 mv_gpio_debounce_setup(device_t dev, int pin) 625 { 626 struct callout *c; 627 struct mv_gpio_softc *sc; 628 629 sc = (struct mv_gpio_softc *)device_get_softc(dev); 630 631 MV_GPIO_ASSERT_LOCKED(); 632 633 c = sc->debounce_callouts[pin]; 634 if (c == NULL) 635 return (ENXIO); 636 637 if (callout_active(c)) 638 callout_deactivate(c); 639 640 callout_stop(c); 641 642 return (0); 643 } 644 645 static int 646 mv_gpio_debounce_prepare(device_t dev, int pin) 647 { 648 struct callout *c; 649 struct mv_gpio_softc *sc; 650 651 sc = (struct mv_gpio_softc *)device_get_softc(dev); 652 653 c = sc->debounce_callouts[pin]; 654 if (c == NULL) { 655 c = (struct callout *)malloc(sizeof(struct callout), 656 M_DEVBUF, M_WAITOK); 657 sc->debounce_callouts[pin] = c; 658 if (c == NULL) 659 return (ENOMEM); 660 callout_init(c, 1); 661 } 662 663 return (0); 664 } 665 666 static int 667 mv_gpio_debounce_init(device_t dev, int pin) 668 { 669 uint8_t raw_read; 670 int *cnt; 671 struct mv_gpio_softc *sc; 672 673 sc = (struct mv_gpio_softc *)device_get_softc(dev); 674 675 MV_GPIO_ASSERT_LOCKED(); 676 677 cnt = &sc->debounce_counters[pin]; 678 raw_read = (mv_gpio_value_get(dev, pin, 1) ? 1 : 0); 679 if (raw_read) { 680 mv_gpio_polarity(dev, pin, 1, 0); 681 *cnt = DEBOUNCE_HI_LO_MS / DEBOUNCE_CHECK_MS; 682 } else { 683 mv_gpio_polarity(dev, pin, 0, 0); 684 *cnt = DEBOUNCE_LO_HI_MS / DEBOUNCE_CHECK_MS; 685 } 686 687 mv_gpio_debounced_state_set(dev, pin, raw_read); 688 689 return (0); 690 } 691 692 static void 693 mv_gpio_debounce_start(device_t dev, int pin) 694 { 695 struct callout *c; 696 struct mv_gpio_pindev s = {dev, pin}; 697 struct mv_gpio_pindev *sd; 698 struct mv_gpio_softc *sc; 699 sc = (struct mv_gpio_softc *)device_get_softc(dev); 700 701 MV_GPIO_ASSERT_LOCKED(); 702 703 c = sc->debounce_callouts[pin]; 704 if (c == NULL) { 705 mv_gpio_int_ack(&s); 706 return; 707 } 708 709 if (callout_pending(c) || callout_active(c)) { 710 mv_gpio_int_ack(&s); 711 return; 712 } 713 714 sd = (struct mv_gpio_pindev *)malloc(sizeof(struct mv_gpio_pindev), 715 M_DEVBUF, M_WAITOK); 716 if (sd == NULL) { 717 mv_gpio_int_ack(&s); 718 return; 719 } 720 sd->pin = pin; 721 sd->dev = dev; 722 723 callout_reset(c, DEBOUNCE_CHECK_TICKS, mv_gpio_debounce, sd); 724 } 725 726 static void 727 mv_gpio_debounce(void *arg) 728 { 729 uint8_t raw_read, last_state; 730 int pin; 731 device_t dev; 732 int *debounce_counter; 733 struct mv_gpio_softc *sc; 734 struct mv_gpio_pindev *s; 735 736 s = (struct mv_gpio_pindev *)arg; 737 dev = s->dev; 738 pin = s->pin; 739 sc = (struct mv_gpio_softc *)device_get_softc(dev); 740 741 MV_GPIO_LOCK(); 742 743 raw_read = (mv_gpio_value_get(dev, pin, 1) ? 1 : 0); 744 last_state = (mv_gpio_debounced_state_get(dev, pin) ? 1 : 0); 745 debounce_counter = &sc->debounce_counters[pin]; 746 747 if (raw_read == last_state) { 748 if (last_state) 749 *debounce_counter = DEBOUNCE_HI_LO_MS / 750 DEBOUNCE_CHECK_MS; 751 else 752 *debounce_counter = DEBOUNCE_LO_HI_MS / 753 DEBOUNCE_CHECK_MS; 754 755 callout_reset(sc->debounce_callouts[pin], 756 DEBOUNCE_CHECK_TICKS, mv_gpio_debounce, arg); 757 } else { 758 *debounce_counter = *debounce_counter - 1; 759 if (*debounce_counter != 0) 760 callout_reset(sc->debounce_callouts[pin], 761 DEBOUNCE_CHECK_TICKS, mv_gpio_debounce, arg); 762 else { 763 mv_gpio_debounced_state_set(dev, pin, raw_read); 764 765 if (last_state) 766 *debounce_counter = DEBOUNCE_HI_LO_MS / 767 DEBOUNCE_CHECK_MS; 768 else 769 *debounce_counter = DEBOUNCE_LO_HI_MS / 770 DEBOUNCE_CHECK_MS; 771 772 if (((sc->gpio_setup[pin].gp_flags & MV_GPIO_IN_POL_LOW) && 773 (raw_read == 0)) || 774 (((sc->gpio_setup[pin].gp_flags & MV_GPIO_IN_POL_LOW) == 0) && 775 raw_read) || 776 (sc->gpio_setup[pin].gp_flags & MV_GPIO_IN_IRQ_DOUBLE_EDGE)) 777 mv_gpio_intr_handler(dev, pin); 778 779 /* Toggle polarity for next edge. */ 780 mv_gpio_polarity(dev, pin, 0, 1); 781 782 free(arg, M_DEVBUF); 783 callout_deactivate(sc->debounce_callouts[pin]); 784 } 785 } 786 787 MV_GPIO_UNLOCK(); 788 } 789 790 static void 791 mv_gpio_debounced_state_set(device_t dev, int pin, uint8_t new_state) 792 { 793 uint32_t *old_state; 794 struct mv_gpio_softc *sc; 795 sc = (struct mv_gpio_softc *)device_get_softc(dev); 796 797 MV_GPIO_ASSERT_LOCKED(); 798 799 if (pin >= GPIO_PINS_PER_REG) { 800 old_state = &sc->debounced_state_hi; 801 pin -= GPIO_PINS_PER_REG; 802 } else 803 old_state = &sc->debounced_state_lo; 804 805 if (new_state) 806 *old_state |= (1 << pin); 807 else 808 *old_state &= ~(1 << pin); 809 } 810 811 static uint32_t 812 mv_gpio_debounced_state_get(device_t dev, int pin) 813 { 814 uint32_t *state; 815 struct mv_gpio_softc *sc; 816 sc = (struct mv_gpio_softc *)device_get_softc(dev); 817 818 MV_GPIO_ASSERT_LOCKED(); 819 820 if (pin >= GPIO_PINS_PER_REG) { 821 state = &sc->debounced_state_hi; 822 pin -= GPIO_PINS_PER_REG; 823 } else 824 state = &sc->debounced_state_lo; 825 826 return (*state & (1 << pin)); 827 } 828 829 void 830 mv_gpio_out(device_t dev, uint32_t pin, uint8_t val, uint8_t enable) 831 { 832 struct mv_gpio_softc *sc; 833 sc = (struct mv_gpio_softc *)device_get_softc(dev); 834 835 MV_GPIO_LOCK(); 836 837 mv_gpio_value_set(dev, pin, val); 838 mv_gpio_out_en(dev, pin, enable); 839 840 MV_GPIO_UNLOCK(); 841 } 842 843 uint8_t 844 mv_gpio_in(device_t dev, uint32_t pin) 845 { 846 uint8_t state; 847 struct mv_gpio_softc *sc; 848 sc = (struct mv_gpio_softc *)device_get_softc(dev); 849 850 MV_GPIO_ASSERT_LOCKED(); 851 852 if (sc->gpio_setup[pin].gp_flags & MV_GPIO_IN_DEBOUNCE) { 853 if (sc->gpio_setup[pin].gp_flags & MV_GPIO_IN_POL_LOW) 854 state = (mv_gpio_debounced_state_get(dev, pin) ? 0 : 1); 855 else 856 state = (mv_gpio_debounced_state_get(dev, pin) ? 1 : 0); 857 } else if (sc->gpio_setup[pin].gp_flags & MV_GPIO_IN_IRQ_DOUBLE_EDGE) { 858 if (sc->gpio_setup[pin].gp_flags & MV_GPIO_IN_POL_LOW) 859 state = (mv_gpio_value_get(dev, pin, 1) ? 0 : 1); 860 else 861 state = (mv_gpio_value_get(dev, pin, 1) ? 1 : 0); 862 } else 863 state = (mv_gpio_value_get(dev, pin, 0) ? 1 : 0); 864 865 return (state); 866 } 867 868 static uint32_t 869 mv_gpio_reg_read(device_t dev, uint32_t reg) 870 { 871 struct mv_gpio_softc *sc; 872 sc = (struct mv_gpio_softc *)device_get_softc(dev); 873 874 return (bus_space_read_4(sc->bst, sc->bsh, sc->offset + reg)); 875 } 876 877 static void 878 mv_gpio_reg_write(device_t dev, uint32_t reg, uint32_t val) 879 { 880 struct mv_gpio_softc *sc; 881 sc = (struct mv_gpio_softc *)device_get_softc(dev); 882 883 bus_space_write_4(sc->bst, sc->bsh, sc->offset + reg, val); 884 } 885 886 static void 887 mv_gpio_reg_set(device_t dev, uint32_t reg, uint32_t pin) 888 { 889 uint32_t reg_val; 890 891 reg_val = mv_gpio_reg_read(dev, reg); 892 reg_val |= GPIO(pin); 893 mv_gpio_reg_write(dev, reg, reg_val); 894 } 895 896 static void 897 mv_gpio_reg_clear(device_t dev, uint32_t reg, uint32_t pin) 898 { 899 uint32_t reg_val; 900 901 reg_val = mv_gpio_reg_read(dev, reg); 902 reg_val &= ~(GPIO(pin)); 903 mv_gpio_reg_write(dev, reg, reg_val); 904 } 905 906 static void 907 mv_gpio_out_en(device_t dev, uint32_t pin, uint8_t enable) 908 { 909 uint32_t reg; 910 struct mv_gpio_softc *sc; 911 sc = (struct mv_gpio_softc *)device_get_softc(dev); 912 913 if (pin >= sc->pin_num) 914 return; 915 916 reg = GPIO_DATA_OUT_EN_CTRL; 917 918 if (enable) 919 mv_gpio_reg_clear(dev, reg, pin); 920 else 921 mv_gpio_reg_set(dev, reg, pin); 922 } 923 924 static void 925 mv_gpio_blink(device_t dev, uint32_t pin, uint8_t enable) 926 { 927 uint32_t reg; 928 struct mv_gpio_softc *sc; 929 sc = (struct mv_gpio_softc *)device_get_softc(dev); 930 931 if (pin >= sc->pin_num) 932 return; 933 934 reg = GPIO_BLINK_EN; 935 936 if (enable) 937 mv_gpio_reg_set(dev, reg, pin); 938 else 939 mv_gpio_reg_clear(dev, reg, pin); 940 } 941 942 static void 943 mv_gpio_polarity(device_t dev, uint32_t pin, uint8_t enable, uint8_t toggle) 944 { 945 uint32_t reg, reg_val; 946 struct mv_gpio_softc *sc; 947 sc = (struct mv_gpio_softc *)device_get_softc(dev); 948 949 if (pin >= sc->pin_num) 950 return; 951 952 reg = GPIO_DATA_IN_POLAR; 953 954 if (toggle) { 955 reg_val = mv_gpio_reg_read(dev, reg) & GPIO(pin); 956 if (reg_val) 957 mv_gpio_reg_clear(dev, reg, pin); 958 else 959 mv_gpio_reg_set(dev, reg, pin); 960 } else if (enable) 961 mv_gpio_reg_set(dev, reg, pin); 962 else 963 mv_gpio_reg_clear(dev, reg, pin); 964 } 965 966 static void 967 mv_gpio_level(device_t dev, uint32_t pin, uint8_t enable) 968 { 969 uint32_t reg; 970 struct mv_gpio_softc *sc; 971 sc = (struct mv_gpio_softc *)device_get_softc(dev); 972 973 if (pin >= sc->pin_num) 974 return; 975 976 reg = GPIO_INT_LEV_MASK; 977 978 if (enable) 979 mv_gpio_reg_set(dev, reg, pin); 980 else 981 mv_gpio_reg_clear(dev, reg, pin); 982 } 983 984 static void 985 mv_gpio_edge(device_t dev, uint32_t pin, uint8_t enable) 986 { 987 uint32_t reg; 988 struct mv_gpio_softc *sc; 989 sc = (struct mv_gpio_softc *)device_get_softc(dev); 990 991 if (pin >= sc->pin_num) 992 return; 993 994 reg = GPIO_INT_EDGE_MASK; 995 996 if (enable) 997 mv_gpio_reg_set(dev, reg, pin); 998 else 999 mv_gpio_reg_clear(dev, reg, pin); 1000 } 1001 1002 static void 1003 mv_gpio_int_ack(struct mv_gpio_pindev *s) 1004 { 1005 uint32_t reg, pin; 1006 struct mv_gpio_softc *sc; 1007 sc = (struct mv_gpio_softc *)device_get_softc(s->dev); 1008 pin = s->pin; 1009 1010 if (pin >= sc->pin_num) 1011 return; 1012 1013 reg = GPIO_INT_CAUSE; 1014 1015 mv_gpio_reg_clear(s->dev, reg, pin); 1016 } 1017 1018 static uint32_t 1019 mv_gpio_value_get(device_t dev, uint32_t pin, uint8_t exclude_polar) 1020 { 1021 uint32_t reg, polar_reg, reg_val, polar_reg_val; 1022 struct mv_gpio_softc *sc; 1023 sc = (struct mv_gpio_softc *)device_get_softc(dev); 1024 1025 if (pin >= sc->pin_num) 1026 return (0); 1027 1028 reg = GPIO_DATA_IN; 1029 polar_reg = GPIO_DATA_IN_POLAR; 1030 1031 reg_val = mv_gpio_reg_read(dev, reg); 1032 1033 if (exclude_polar) { 1034 polar_reg_val = mv_gpio_reg_read(dev, polar_reg); 1035 return ((reg_val & GPIO(pin)) ^ (polar_reg_val & GPIO(pin))); 1036 } else 1037 return (reg_val & GPIO(pin)); 1038 } 1039 1040 static void 1041 mv_gpio_value_set(device_t dev, uint32_t pin, uint8_t val) 1042 { 1043 uint32_t reg; 1044 struct mv_gpio_softc *sc; 1045 sc = (struct mv_gpio_softc *)device_get_softc(dev); 1046 1047 MV_GPIO_ASSERT_LOCKED(); 1048 1049 if (pin >= sc->pin_num) 1050 return; 1051 1052 reg = GPIO_DATA_OUT; 1053 1054 if (val) 1055 mv_gpio_reg_set(dev, reg, pin); 1056 else 1057 mv_gpio_reg_clear(dev, reg, pin); 1058 } 1059 1060 /* 1061 * GPIO interface methods 1062 */ 1063 1064 static int 1065 mv_gpio_pin_max(device_t dev, int *maxpin) 1066 { 1067 struct mv_gpio_softc *sc; 1068 if (maxpin == NULL) 1069 return (EINVAL); 1070 1071 sc = device_get_softc(dev); 1072 *maxpin = sc->pin_num; 1073 1074 return (0); 1075 } 1076 1077 static int 1078 mv_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps) 1079 { 1080 struct mv_gpio_softc *sc = device_get_softc(dev); 1081 if (caps == NULL) 1082 return (EINVAL); 1083 1084 if (pin >= sc->pin_num) 1085 return (EINVAL); 1086 1087 MV_GPIO_LOCK(); 1088 *caps = sc->gpio_setup[pin].gp_caps; 1089 MV_GPIO_UNLOCK(); 1090 1091 return (0); 1092 } 1093 1094 static int 1095 mv_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags) 1096 { 1097 struct mv_gpio_softc *sc = device_get_softc(dev); 1098 if (flags == NULL) 1099 return (EINVAL); 1100 1101 if (pin >= sc->pin_num) 1102 return (EINVAL); 1103 1104 MV_GPIO_LOCK(); 1105 *flags = sc->gpio_setup[pin].gp_flags; 1106 MV_GPIO_UNLOCK(); 1107 1108 return (0); 1109 } 1110 1111 static int 1112 mv_gpio_pin_getname(device_t dev, uint32_t pin, char *name) 1113 { 1114 struct mv_gpio_softc *sc = device_get_softc(dev); 1115 if (name == NULL) 1116 return (EINVAL); 1117 1118 if (pin >= sc->pin_num) 1119 return (EINVAL); 1120 1121 MV_GPIO_LOCK(); 1122 memcpy(name, sc->gpio_setup[pin].gp_name, GPIOMAXNAME); 1123 MV_GPIO_UNLOCK(); 1124 1125 return (0); 1126 } 1127 1128 static int 1129 mv_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags) 1130 { 1131 int ret; 1132 struct mv_gpio_softc *sc = device_get_softc(dev); 1133 if (pin >= sc->pin_num) 1134 return (EINVAL); 1135 1136 /* Check for unwanted flags. */ 1137 if ((flags & sc->gpio_setup[pin].gp_caps) != flags) 1138 return (EINVAL); 1139 1140 ret = mv_gpio_configure(dev, pin, flags, ~0); 1141 1142 return (ret); 1143 } 1144 1145 static int 1146 mv_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value) 1147 { 1148 struct mv_gpio_softc *sc = device_get_softc(dev); 1149 if (pin >= sc->pin_num) 1150 return (EINVAL); 1151 1152 MV_GPIO_LOCK(); 1153 mv_gpio_value_set(dev, pin, value); 1154 MV_GPIO_UNLOCK(); 1155 1156 return (0); 1157 } 1158 1159 static int 1160 mv_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *value) 1161 { 1162 struct mv_gpio_softc *sc = device_get_softc(dev); 1163 if (value == NULL) 1164 return (EINVAL); 1165 1166 if (pin >= sc->pin_num) 1167 return (EINVAL); 1168 1169 MV_GPIO_LOCK(); 1170 *value = mv_gpio_in(dev, pin); 1171 MV_GPIO_UNLOCK(); 1172 1173 return (0); 1174 } 1175 1176 static int 1177 mv_gpio_pin_toggle(device_t dev, uint32_t pin) 1178 { 1179 struct mv_gpio_softc *sc = device_get_softc(dev); 1180 uint32_t value; 1181 if (pin >= sc->pin_num) 1182 return (EINVAL); 1183 1184 MV_GPIO_LOCK(); 1185 value = mv_gpio_in(dev, pin); 1186 value = (~value) & 1; 1187 mv_gpio_value_set(dev, pin, value); 1188 MV_GPIO_UNLOCK(); 1189 1190 return (0); 1191 } 1192 1193 static device_t 1194 mv_gpio_get_bus(device_t dev) 1195 { 1196 struct mv_gpio_softc *sc = device_get_softc(dev); 1197 1198 return (sc->sc_busdev); 1199 } 1200 1201 static int 1202 mv_gpio_map_gpios(device_t bus, phandle_t dev, phandle_t gparent, int gcells, 1203 pcell_t *gpios, uint32_t *pin, uint32_t *flags) 1204 { 1205 struct mv_gpio_softc *sc = device_get_softc(bus); 1206 1207 if (gpios[0] >= sc->pin_num) 1208 return (EINVAL); 1209 1210 *pin = gpios[0]; 1211 *flags = gpios[1]; 1212 mv_gpio_configure(bus, *pin, *flags, ~0); 1213 1214 return (0); 1215 } 1216