1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2006 Benno Rice. 5 * Copyright (C) 2008 MARVELL INTERNATIONAL LTD. 6 * Copyright (c) 2017 Semihalf. 7 * All rights reserved. 8 * 9 * Adapted and extended for Marvell SoCs by Semihalf. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 * 31 * from: FreeBSD: //depot/projects/arm/src/sys/arm/xscale/pxa2x0/pxa2x0_gpio.c, rev 1 32 */ 33 34 #include <sys/cdefs.h> 35 __FBSDID("$FreeBSD$"); 36 37 #include <sys/param.h> 38 #include <sys/systm.h> 39 #include <sys/bus.h> 40 #include <sys/kernel.h> 41 #include <sys/lock.h> 42 #include <sys/interrupt.h> 43 #include <sys/module.h> 44 #include <sys/malloc.h> 45 #include <sys/mutex.h> 46 #include <sys/rman.h> 47 #include <sys/queue.h> 48 #include <sys/timetc.h> 49 #include <sys/callout.h> 50 #include <sys/gpio.h> 51 #include <machine/bus.h> 52 #include <machine/intr.h> 53 54 #include <dev/fdt/fdt_common.h> 55 #include <dev/ofw/ofw_bus.h> 56 #include <dev/ofw/ofw_bus_subr.h> 57 58 #include <arm/mv/mvvar.h> 59 #include <arm/mv/mvreg.h> 60 61 #define GPIO_MAX_INTR_COUNT 8 62 #define GPIO_PINS_PER_REG 32 63 64 #define DEBOUNCE_CHECK_MS 1 65 #define DEBOUNCE_LO_HI_MS 2 66 #define DEBOUNCE_HI_LO_MS 2 67 #define DEBOUNCE_CHECK_TICKS ((hz / 1000) * DEBOUNCE_CHECK_MS) 68 69 struct mv_gpio_softc { 70 struct resource * mem_res; 71 int mem_rid; 72 struct resource * irq_res[GPIO_MAX_INTR_COUNT]; 73 int irq_rid[GPIO_MAX_INTR_COUNT]; 74 void *ih_cookie[GPIO_MAX_INTR_COUNT]; 75 bus_space_tag_t bst; 76 bus_space_handle_t bsh; 77 struct mtx mutex; 78 uint8_t pin_num; /* number of GPIO pins */ 79 uint8_t irq_num; /* number of real IRQs occupied by GPIO controller */ 80 uint8_t use_high; 81 82 /* Used for debouncing. */ 83 uint32_t debounced_state_lo; 84 uint32_t debounced_state_hi; 85 struct callout **debounce_callouts; 86 int *debounce_counters; 87 }; 88 89 static struct mv_gpio_softc *mv_gpio_softc = NULL; 90 static uint32_t gpio_setup[MV_GPIO_MAX_NPINS]; 91 92 static int mv_gpio_probe(device_t); 93 static int mv_gpio_attach(device_t); 94 static int mv_gpio_intr(void *); 95 static int mv_gpio_init(void); 96 97 static void mv_gpio_double_edge_init(int pin); 98 99 static int mv_gpio_debounce_setup(int pin); 100 static int mv_gpio_debounce_init(int pin); 101 static void mv_gpio_debounce_start(int pin); 102 static int mv_gpio_debounce_prepare(int pin); 103 static void mv_gpio_debounce(void *arg); 104 static void mv_gpio_debounced_state_set(int pin, uint8_t new_state); 105 static uint32_t mv_gpio_debounced_state_get(int pin); 106 107 static void mv_gpio_exec_intr_handlers(uint32_t status, int high); 108 static void mv_gpio_intr_handler(int pin); 109 static uint32_t mv_gpio_reg_read(uint32_t reg); 110 static void mv_gpio_reg_write(uint32_t reg, uint32_t val); 111 static void mv_gpio_reg_set(uint32_t reg, uint32_t val); 112 static void mv_gpio_reg_clear(uint32_t reg, uint32_t val); 113 114 static void mv_gpio_blink(uint32_t pin, uint8_t enable); 115 static void mv_gpio_polarity(uint32_t pin, uint8_t enable, uint8_t toggle); 116 static void mv_gpio_level(uint32_t pin, uint8_t enable); 117 static void mv_gpio_edge(uint32_t pin, uint8_t enable); 118 static void mv_gpio_out_en(uint32_t pin, uint8_t enable); 119 static void mv_gpio_int_ack(uint32_t pin); 120 static void mv_gpio_value_set(uint32_t pin, uint8_t val); 121 static uint32_t mv_gpio_value_get(uint32_t pin, uint8_t exclude_polar); 122 123 static void mv_gpio_intr_mask(int pin); 124 static void mv_gpio_intr_unmask(int pin); 125 int mv_gpio_setup_intrhandler(const char *name, driver_filter_t *filt, 126 void (*hand)(void *), void *arg, int pin, int flags, void **cookiep); 127 128 int mv_gpio_configure(uint32_t pin, uint32_t flags, uint32_t mask); 129 void mv_gpio_out(uint32_t pin, uint8_t val, uint8_t enable); 130 uint8_t mv_gpio_in(uint32_t pin); 131 132 #define MV_GPIO_LOCK() mtx_lock_spin(&mv_gpio_softc->mutex) 133 #define MV_GPIO_UNLOCK() mtx_unlock_spin(&mv_gpio_softc->mutex) 134 #define MV_GPIO_ASSERT_LOCKED() mtx_assert(&mv_gpio_softc->mutex, MA_OWNED) 135 136 static device_method_t mv_gpio_methods[] = { 137 DEVMETHOD(device_probe, mv_gpio_probe), 138 DEVMETHOD(device_attach, mv_gpio_attach), 139 { 0, 0 } 140 }; 141 142 static driver_t mv_gpio_driver = { 143 "gpio", 144 mv_gpio_methods, 145 sizeof(struct mv_gpio_softc), 146 }; 147 148 static devclass_t mv_gpio_devclass; 149 150 DRIVER_MODULE(gpio, simplebus, mv_gpio_driver, mv_gpio_devclass, 0, 0); 151 152 typedef int (*gpios_phandler_t)(phandle_t, pcell_t *, int); 153 154 struct gpio_ctrl_entry { 155 const char *compat; 156 gpios_phandler_t handler; 157 }; 158 159 static int mv_handle_gpios_prop(phandle_t ctrl, pcell_t *gpios, int len); 160 int gpio_get_config_from_dt(void); 161 162 struct gpio_ctrl_entry gpio_controllers[] = { 163 { "mrvl,gpio", &mv_handle_gpios_prop }, 164 { NULL, NULL } 165 }; 166 167 static int 168 mv_gpio_probe(device_t dev) 169 { 170 171 if (!ofw_bus_status_okay(dev)) 172 return (ENXIO); 173 174 if (!ofw_bus_is_compatible(dev, "mrvl,gpio")) 175 return (ENXIO); 176 177 device_set_desc(dev, "Marvell Integrated GPIO Controller"); 178 return (0); 179 } 180 181 static int 182 mv_gpio_attach(device_t dev) 183 { 184 int error, i, size; 185 struct mv_gpio_softc *sc; 186 uint32_t dev_id, rev_id; 187 pcell_t pincnt = 0; 188 pcell_t irq_cells = 0; 189 phandle_t iparent; 190 191 sc = (struct mv_gpio_softc *)device_get_softc(dev); 192 if (sc == NULL) 193 return (ENXIO); 194 195 if (mv_gpio_softc != NULL) 196 return (ENXIO); 197 mv_gpio_softc = sc; 198 199 /* Get chip id and revision */ 200 soc_id(&dev_id, &rev_id); 201 202 if (dev_id == MV_DEV_88F5182 || 203 dev_id == MV_DEV_88F5281 || 204 dev_id == MV_DEV_MV78100 || 205 dev_id == MV_DEV_MV78100_Z0 ) { 206 sc->pin_num = 32; 207 sc->irq_num = 4; 208 sc->use_high = 0; 209 210 } else if (dev_id == MV_DEV_88F6281 || 211 dev_id == MV_DEV_88F6282) { 212 sc->pin_num = 50; 213 sc->irq_num = 7; 214 sc->use_high = 1; 215 216 } else { 217 if (OF_getencprop(ofw_bus_get_node(dev), "pin-count", &pincnt, 218 sizeof(pcell_t)) >= 0 || 219 OF_getencprop(ofw_bus_get_node(dev), "ngpios", &pincnt, 220 sizeof(pcell_t)) >= 0) { 221 sc->pin_num = pincnt; 222 device_printf(dev, "%d pins available\n", sc->pin_num); 223 } else { 224 device_printf(dev, "ERROR: no pin-count entry found!\n"); 225 return (ENXIO); 226 } 227 } 228 229 /* Find root interrupt controller */ 230 iparent = ofw_bus_find_iparent(ofw_bus_get_node(dev)); 231 if (iparent == 0) { 232 device_printf(dev, "No interrupt-parrent found. " 233 "Error in DTB\n"); 234 return (ENXIO); 235 } else { 236 /* While at parent - store interrupt cells prop */ 237 if (OF_searchencprop(OF_node_from_xref(iparent), 238 "#interrupt-cells", &irq_cells, sizeof(irq_cells)) == -1) { 239 device_printf(dev, "DTB: Missing #interrupt-cells " 240 "property in interrupt parent node\n"); 241 return (ENXIO); 242 } 243 } 244 245 size = OF_getproplen(ofw_bus_get_node(dev), "interrupts"); 246 if (size != -1) { 247 size = size / sizeof(pcell_t); 248 size = size / irq_cells; 249 sc->irq_num = size; 250 device_printf(dev, "%d IRQs available\n", sc->irq_num); 251 } else { 252 device_printf(dev, "ERROR: no interrupts entry found!\n"); 253 return (ENXIO); 254 } 255 256 sc->debounce_callouts = (struct callout **)malloc(sc->pin_num * 257 sizeof(struct callout *), M_DEVBUF, M_WAITOK | M_ZERO); 258 if (sc->debounce_callouts == NULL) 259 return (ENOMEM); 260 261 sc->debounce_counters = (int *)malloc(sc->pin_num * sizeof(int), 262 M_DEVBUF, M_WAITOK); 263 if (sc->debounce_counters == NULL) 264 return (ENOMEM); 265 266 mtx_init(&sc->mutex, device_get_nameunit(dev), NULL, MTX_SPIN); 267 268 sc->mem_rid = 0; 269 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->mem_rid, 270 RF_ACTIVE); 271 272 if (!sc->mem_res) { 273 mtx_destroy(&sc->mutex); 274 device_printf(dev, "could not allocate memory window\n"); 275 return (ENXIO); 276 } 277 278 sc->bst = rman_get_bustag(sc->mem_res); 279 sc->bsh = rman_get_bushandle(sc->mem_res); 280 281 for (i = 0; i < sc->irq_num; i++) { 282 sc->irq_rid[i] = i; 283 sc->irq_res[i] = bus_alloc_resource_any(dev, SYS_RES_IRQ, 284 &sc->irq_rid[i], RF_ACTIVE); 285 if (!sc->irq_res[i]) { 286 mtx_destroy(&sc->mutex); 287 device_printf(dev, 288 "could not allocate gpio%d interrupt\n", i+1); 289 return (ENXIO); 290 } 291 } 292 293 /* Disable all interrupts */ 294 bus_space_write_4(sc->bst, sc->bsh, GPIO_INT_EDGE_MASK, 0); 295 bus_space_write_4(sc->bst, sc->bsh, GPIO_INT_LEV_MASK, 0); 296 297 if (sc->use_high) { 298 bus_space_write_4(sc->bst, sc->bsh, 299 GPIO_HI_INT_EDGE_MASK, 0); 300 bus_space_write_4(sc->bst, sc->bsh, 301 GPIO_HI_INT_LEV_MASK, 0); 302 bus_space_write_4(sc->bst, sc->bsh, 303 GPIO_HI_INT_CAUSE, 0); 304 } 305 306 for (i = 0; i < sc->irq_num; i++) { 307 if (bus_setup_intr(dev, sc->irq_res[i], 308 INTR_TYPE_MISC, 309 (driver_filter_t *)mv_gpio_intr, NULL, 310 sc, &sc->ih_cookie[i]) != 0) { 311 mtx_destroy(&sc->mutex); 312 bus_release_resource(dev, SYS_RES_IRQ, 313 sc->irq_rid[i], sc->irq_res[i]); 314 device_printf(dev, "could not set up intr %d\n", i); 315 return (ENXIO); 316 } 317 } 318 319 error = mv_gpio_init(); 320 if (error) { 321 device_printf(dev, "WARNING: failed to initialize GPIO pins, " 322 "error = %d\n", error); 323 } 324 325 /* Clear interrupt status. */ 326 bus_space_write_4(sc->bst, sc->bsh, GPIO_INT_CAUSE, 0); 327 328 return (0); 329 } 330 331 static int 332 mv_gpio_intr(void *arg) 333 { 334 uint32_t int_cause, gpio_val; 335 uint32_t int_cause_hi, gpio_val_hi; 336 337 MV_GPIO_LOCK(); 338 339 /* 340 * According to documentation, edge sensitive interrupts are asserted 341 * when unmasked GPIO_INT_CAUSE register bits are set. 342 */ 343 int_cause = mv_gpio_reg_read(GPIO_INT_CAUSE); 344 int_cause &= mv_gpio_reg_read(GPIO_INT_EDGE_MASK); 345 346 /* 347 * Level sensitive interrupts are asserted when unmasked GPIO_DATA_IN 348 * register bits are set. 349 */ 350 gpio_val = mv_gpio_reg_read(GPIO_DATA_IN); 351 gpio_val &= mv_gpio_reg_read(GPIO_INT_LEV_MASK); 352 353 int_cause_hi = 0; 354 gpio_val_hi = 0; 355 if (mv_gpio_softc->use_high) { 356 int_cause_hi = mv_gpio_reg_read(GPIO_HI_INT_CAUSE); 357 int_cause_hi &= mv_gpio_reg_read(GPIO_HI_INT_EDGE_MASK); 358 359 gpio_val_hi = mv_gpio_reg_read(GPIO_HI_DATA_IN); 360 gpio_val_hi &= mv_gpio_reg_read(GPIO_HI_INT_LEV_MASK); 361 } 362 363 mv_gpio_exec_intr_handlers(int_cause | gpio_val, 0); 364 365 if (mv_gpio_softc->use_high) 366 mv_gpio_exec_intr_handlers(int_cause_hi | gpio_val_hi, 1); 367 368 MV_GPIO_UNLOCK(); 369 370 return (FILTER_HANDLED); 371 } 372 373 /* 374 * GPIO interrupt handling 375 */ 376 377 static struct intr_event *gpio_events[MV_GPIO_MAX_NPINS]; 378 379 int 380 mv_gpio_setup_intrhandler(const char *name, driver_filter_t *filt, 381 void (*hand)(void *), void *arg, int pin, int flags, void **cookiep) 382 { 383 struct intr_event *event; 384 int error; 385 386 if (pin < 0 || pin >= mv_gpio_softc->pin_num) 387 return (ENXIO); 388 event = gpio_events[pin]; 389 if (event == NULL) { 390 MV_GPIO_LOCK(); 391 if (gpio_setup[pin] & MV_GPIO_IN_DEBOUNCE) { 392 error = mv_gpio_debounce_init(pin); 393 if (error != 0) { 394 MV_GPIO_UNLOCK(); 395 return (error); 396 } 397 } else if (gpio_setup[pin] & MV_GPIO_IN_IRQ_DOUBLE_EDGE) 398 mv_gpio_double_edge_init(pin); 399 MV_GPIO_UNLOCK(); 400 401 error = intr_event_create(&event, (void *)pin, 0, pin, 402 (void (*)(void *))mv_gpio_intr_mask, 403 (void (*)(void *))mv_gpio_intr_unmask, 404 (void (*)(void *))mv_gpio_int_ack, 405 NULL, 406 "gpio%d:", pin); 407 if (error != 0) 408 return (error); 409 gpio_events[pin] = event; 410 } 411 412 intr_event_add_handler(event, name, filt, hand, arg, 413 intr_priority(flags), flags, cookiep); 414 return (0); 415 } 416 417 void 418 mv_gpio_intr_mask(int pin) 419 { 420 421 if (pin >= mv_gpio_softc->pin_num) 422 return; 423 424 MV_GPIO_LOCK(); 425 426 if (gpio_setup[pin] & (MV_GPIO_IN_IRQ_EDGE | MV_GPIO_IN_IRQ_DOUBLE_EDGE)) 427 mv_gpio_edge(pin, 0); 428 else 429 mv_gpio_level(pin, 0); 430 431 /* 432 * The interrupt has to be acknowledged before scheduling an interrupt 433 * thread. This way we allow for interrupt source to trigger again 434 * (which can happen with shared IRQs e.g. PCI) while processing the 435 * current event. 436 */ 437 mv_gpio_int_ack(pin); 438 439 MV_GPIO_UNLOCK(); 440 } 441 442 void 443 mv_gpio_intr_unmask(int pin) 444 { 445 446 if (pin >= mv_gpio_softc->pin_num) 447 return; 448 449 MV_GPIO_LOCK(); 450 451 if (gpio_setup[pin] & (MV_GPIO_IN_IRQ_EDGE | MV_GPIO_IN_IRQ_DOUBLE_EDGE)) 452 mv_gpio_edge(pin, 1); 453 else 454 mv_gpio_level(pin, 1); 455 456 MV_GPIO_UNLOCK(); 457 } 458 459 static void 460 mv_gpio_exec_intr_handlers(uint32_t status, int high) 461 { 462 int i, pin; 463 464 MV_GPIO_ASSERT_LOCKED(); 465 466 i = 0; 467 while (status != 0) { 468 if (status & 1) { 469 pin = (high ? (i + GPIO_PINS_PER_REG) : i); 470 if (gpio_setup[pin] & MV_GPIO_IN_DEBOUNCE) 471 mv_gpio_debounce_start(pin); 472 else if (gpio_setup[pin] & MV_GPIO_IN_IRQ_DOUBLE_EDGE) { 473 mv_gpio_polarity(pin, 0, 1); 474 mv_gpio_intr_handler(pin); 475 } else 476 mv_gpio_intr_handler(pin); 477 } 478 status >>= 1; 479 i++; 480 } 481 } 482 483 static void 484 mv_gpio_intr_handler(int pin) 485 { 486 #ifdef INTRNG 487 struct intr_irqsrc isrc; 488 489 MV_GPIO_ASSERT_LOCKED(); 490 491 #ifdef INTR_SOLO 492 isrc.isrc_filter = NULL; 493 #endif 494 isrc.isrc_event = gpio_events[pin]; 495 496 if (isrc.isrc_event == NULL || TAILQ_EMPTY(&isrc.isrc_event->ie_handlers)) 497 return; 498 499 intr_isrc_dispatch(&isrc, NULL); 500 #endif 501 } 502 503 int 504 mv_gpio_configure(uint32_t pin, uint32_t flags, uint32_t mask) 505 { 506 int error; 507 508 if (pin >= mv_gpio_softc->pin_num) 509 return (EINVAL); 510 511 /* check flags consistency */ 512 if (((flags & mask) & (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT)) == 513 (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT)) 514 return (EINVAL); 515 516 if (mask & MV_GPIO_IN_DEBOUNCE) { 517 error = mv_gpio_debounce_prepare(pin); 518 if (error != 0) 519 return (error); 520 } 521 522 MV_GPIO_LOCK(); 523 524 if (mask & MV_GPIO_OUT_BLINK) 525 mv_gpio_blink(pin, flags & MV_GPIO_OUT_BLINK); 526 if (mask & MV_GPIO_IN_POL_LOW) 527 mv_gpio_polarity(pin, flags & MV_GPIO_IN_POL_LOW, 0); 528 if (mask & MV_GPIO_IN_DEBOUNCE) { 529 error = mv_gpio_debounce_setup(pin); 530 if (error) { 531 MV_GPIO_UNLOCK(); 532 return (error); 533 } 534 } 535 536 gpio_setup[pin] &= ~(mask); 537 gpio_setup[pin] |= (flags & mask); 538 539 MV_GPIO_UNLOCK(); 540 541 return (0); 542 } 543 544 static void 545 mv_gpio_double_edge_init(int pin) 546 { 547 uint8_t raw_read; 548 549 MV_GPIO_ASSERT_LOCKED(); 550 551 raw_read = (mv_gpio_value_get(pin, 1) ? 1 : 0); 552 553 if (raw_read) 554 mv_gpio_polarity(pin, 1, 0); 555 else 556 mv_gpio_polarity(pin, 0, 0); 557 } 558 559 static int 560 mv_gpio_debounce_setup(int pin) 561 { 562 struct callout *c; 563 564 MV_GPIO_ASSERT_LOCKED(); 565 566 c = mv_gpio_softc->debounce_callouts[pin]; 567 if (c == NULL) 568 return (ENXIO); 569 570 if (callout_active(c)) 571 callout_deactivate(c); 572 573 callout_stop(c); 574 575 return (0); 576 } 577 578 static int 579 mv_gpio_debounce_prepare(int pin) 580 { 581 struct callout *c; 582 struct mv_gpio_softc *sc; 583 584 sc = (struct mv_gpio_softc *)mv_gpio_softc; 585 586 c = sc->debounce_callouts[pin]; 587 if (c == NULL) { 588 c = (struct callout *)malloc(sizeof(struct callout), 589 M_DEVBUF, M_WAITOK); 590 sc->debounce_callouts[pin] = c; 591 if (c == NULL) 592 return (ENOMEM); 593 callout_init(c, 1); 594 } 595 596 return (0); 597 } 598 599 static int 600 mv_gpio_debounce_init(int pin) 601 { 602 uint8_t raw_read; 603 int *cnt; 604 605 MV_GPIO_ASSERT_LOCKED(); 606 607 cnt = &mv_gpio_softc->debounce_counters[pin]; 608 609 raw_read = (mv_gpio_value_get(pin, 1) ? 1 : 0); 610 if (raw_read) { 611 mv_gpio_polarity(pin, 1, 0); 612 *cnt = DEBOUNCE_HI_LO_MS / DEBOUNCE_CHECK_MS; 613 } else { 614 mv_gpio_polarity(pin, 0, 0); 615 *cnt = DEBOUNCE_LO_HI_MS / DEBOUNCE_CHECK_MS; 616 } 617 618 mv_gpio_debounced_state_set(pin, raw_read); 619 620 return (0); 621 } 622 623 static void 624 mv_gpio_debounce_start(int pin) 625 { 626 struct callout *c; 627 int *debounced_pin; 628 629 MV_GPIO_ASSERT_LOCKED(); 630 631 c = mv_gpio_softc->debounce_callouts[pin]; 632 if (c == NULL) { 633 mv_gpio_int_ack(pin); 634 return; 635 } 636 637 if (callout_pending(c) || callout_active(c)) { 638 mv_gpio_int_ack(pin); 639 return; 640 } 641 642 debounced_pin = (int *)malloc(sizeof(int), M_DEVBUF, 643 M_WAITOK); 644 if (debounced_pin == NULL) { 645 mv_gpio_int_ack(pin); 646 return; 647 } 648 *debounced_pin = pin; 649 650 callout_reset(c, DEBOUNCE_CHECK_TICKS, mv_gpio_debounce, 651 debounced_pin); 652 } 653 654 static void 655 mv_gpio_debounce(void *arg) 656 { 657 uint8_t raw_read, last_state; 658 int pin; 659 int *debounce_counter; 660 661 pin = *((int *)arg); 662 663 MV_GPIO_LOCK(); 664 665 raw_read = (mv_gpio_value_get(pin, 1) ? 1 : 0); 666 last_state = (mv_gpio_debounced_state_get(pin) ? 1 : 0); 667 debounce_counter = &mv_gpio_softc->debounce_counters[pin]; 668 669 if (raw_read == last_state) { 670 if (last_state) 671 *debounce_counter = DEBOUNCE_HI_LO_MS / 672 DEBOUNCE_CHECK_MS; 673 else 674 *debounce_counter = DEBOUNCE_LO_HI_MS / 675 DEBOUNCE_CHECK_MS; 676 677 callout_reset(mv_gpio_softc->debounce_callouts[pin], 678 DEBOUNCE_CHECK_TICKS, mv_gpio_debounce, arg); 679 } else { 680 *debounce_counter = *debounce_counter - 1; 681 if (*debounce_counter != 0) 682 callout_reset(mv_gpio_softc->debounce_callouts[pin], 683 DEBOUNCE_CHECK_TICKS, mv_gpio_debounce, arg); 684 else { 685 mv_gpio_debounced_state_set(pin, raw_read); 686 687 if (last_state) 688 *debounce_counter = DEBOUNCE_HI_LO_MS / 689 DEBOUNCE_CHECK_MS; 690 else 691 *debounce_counter = DEBOUNCE_LO_HI_MS / 692 DEBOUNCE_CHECK_MS; 693 694 if (((gpio_setup[pin] & MV_GPIO_IN_POL_LOW) && 695 (raw_read == 0)) || 696 (((gpio_setup[pin] & MV_GPIO_IN_POL_LOW) == 0) && 697 raw_read) || 698 (gpio_setup[pin] & MV_GPIO_IN_IRQ_DOUBLE_EDGE)) 699 mv_gpio_intr_handler(pin); 700 701 /* Toggle polarity for next edge. */ 702 mv_gpio_polarity(pin, 0, 1); 703 704 free(arg, M_DEVBUF); 705 callout_deactivate(mv_gpio_softc-> 706 debounce_callouts[pin]); 707 } 708 } 709 710 MV_GPIO_UNLOCK(); 711 } 712 713 static void 714 mv_gpio_debounced_state_set(int pin, uint8_t new_state) 715 { 716 uint32_t *old_state; 717 718 MV_GPIO_ASSERT_LOCKED(); 719 720 if (pin >= GPIO_PINS_PER_REG) { 721 old_state = &mv_gpio_softc->debounced_state_hi; 722 pin -= GPIO_PINS_PER_REG; 723 } else 724 old_state = &mv_gpio_softc->debounced_state_lo; 725 726 if (new_state) 727 *old_state |= (1 << pin); 728 else 729 *old_state &= ~(1 << pin); 730 } 731 732 static uint32_t 733 mv_gpio_debounced_state_get(int pin) 734 { 735 uint32_t *state; 736 737 MV_GPIO_ASSERT_LOCKED(); 738 739 if (pin >= GPIO_PINS_PER_REG) { 740 state = &mv_gpio_softc->debounced_state_hi; 741 pin -= GPIO_PINS_PER_REG; 742 } else 743 state = &mv_gpio_softc->debounced_state_lo; 744 745 return (*state & (1 << pin)); 746 } 747 748 void 749 mv_gpio_out(uint32_t pin, uint8_t val, uint8_t enable) 750 { 751 752 MV_GPIO_LOCK(); 753 754 mv_gpio_value_set(pin, val); 755 mv_gpio_out_en(pin, enable); 756 757 MV_GPIO_UNLOCK(); 758 } 759 760 uint8_t 761 mv_gpio_in(uint32_t pin) 762 { 763 uint8_t state; 764 765 MV_GPIO_LOCK(); 766 767 if (gpio_setup[pin] & MV_GPIO_IN_DEBOUNCE) { 768 if (gpio_setup[pin] & MV_GPIO_IN_POL_LOW) 769 state = (mv_gpio_debounced_state_get(pin) ? 0 : 1); 770 else 771 state = (mv_gpio_debounced_state_get(pin) ? 1 : 0); 772 } else if (gpio_setup[pin] & MV_GPIO_IN_IRQ_DOUBLE_EDGE) { 773 if (gpio_setup[pin] & MV_GPIO_IN_POL_LOW) 774 state = (mv_gpio_value_get(pin, 1) ? 0 : 1); 775 else 776 state = (mv_gpio_value_get(pin, 1) ? 1 : 0); 777 } else 778 state = (mv_gpio_value_get(pin, 0) ? 1 : 0); 779 780 MV_GPIO_UNLOCK(); 781 782 return (state); 783 } 784 785 static uint32_t 786 mv_gpio_reg_read(uint32_t reg) 787 { 788 789 return (bus_space_read_4(mv_gpio_softc->bst, 790 mv_gpio_softc->bsh, reg)); 791 } 792 793 static void 794 mv_gpio_reg_write(uint32_t reg, uint32_t val) 795 { 796 797 bus_space_write_4(mv_gpio_softc->bst, 798 mv_gpio_softc->bsh, reg, val); 799 } 800 801 static void 802 mv_gpio_reg_set(uint32_t reg, uint32_t pin) 803 { 804 uint32_t reg_val; 805 806 reg_val = mv_gpio_reg_read(reg); 807 reg_val |= GPIO(pin); 808 mv_gpio_reg_write(reg, reg_val); 809 } 810 811 static void 812 mv_gpio_reg_clear(uint32_t reg, uint32_t pin) 813 { 814 uint32_t reg_val; 815 816 reg_val = mv_gpio_reg_read(reg); 817 reg_val &= ~(GPIO(pin)); 818 mv_gpio_reg_write(reg, reg_val); 819 } 820 821 static void 822 mv_gpio_out_en(uint32_t pin, uint8_t enable) 823 { 824 uint32_t reg; 825 826 if (pin >= mv_gpio_softc->pin_num) 827 return; 828 829 if (pin >= GPIO_PINS_PER_REG) { 830 reg = GPIO_HI_DATA_OUT_EN_CTRL; 831 pin -= GPIO_PINS_PER_REG; 832 } else 833 reg = GPIO_DATA_OUT_EN_CTRL; 834 835 if (enable) 836 mv_gpio_reg_clear(reg, pin); 837 else 838 mv_gpio_reg_set(reg, pin); 839 } 840 841 static void 842 mv_gpio_blink(uint32_t pin, uint8_t enable) 843 { 844 uint32_t reg; 845 846 if (pin >= mv_gpio_softc->pin_num) 847 return; 848 849 if (pin >= GPIO_PINS_PER_REG) { 850 reg = GPIO_HI_BLINK_EN; 851 pin -= GPIO_PINS_PER_REG; 852 } else 853 reg = GPIO_BLINK_EN; 854 855 if (enable) 856 mv_gpio_reg_set(reg, pin); 857 else 858 mv_gpio_reg_clear(reg, pin); 859 } 860 861 static void 862 mv_gpio_polarity(uint32_t pin, uint8_t enable, uint8_t toggle) 863 { 864 uint32_t reg, reg_val; 865 866 if (pin >= mv_gpio_softc->pin_num) 867 return; 868 869 if (pin >= GPIO_PINS_PER_REG) { 870 reg = GPIO_HI_DATA_IN_POLAR; 871 pin -= GPIO_PINS_PER_REG; 872 } else 873 reg = GPIO_DATA_IN_POLAR; 874 875 if (toggle) { 876 reg_val = mv_gpio_reg_read(reg) & GPIO(pin); 877 if (reg_val) 878 mv_gpio_reg_clear(reg, pin); 879 else 880 mv_gpio_reg_set(reg, pin); 881 } else if (enable) 882 mv_gpio_reg_set(reg, pin); 883 else 884 mv_gpio_reg_clear(reg, pin); 885 } 886 887 static void 888 mv_gpio_level(uint32_t pin, uint8_t enable) 889 { 890 uint32_t reg; 891 892 if (pin >= mv_gpio_softc->pin_num) 893 return; 894 895 if (pin >= GPIO_PINS_PER_REG) { 896 reg = GPIO_HI_INT_LEV_MASK; 897 pin -= GPIO_PINS_PER_REG; 898 } else 899 reg = GPIO_INT_LEV_MASK; 900 901 if (enable) 902 mv_gpio_reg_set(reg, pin); 903 else 904 mv_gpio_reg_clear(reg, pin); 905 } 906 907 static void 908 mv_gpio_edge(uint32_t pin, uint8_t enable) 909 { 910 uint32_t reg; 911 912 if (pin >= mv_gpio_softc->pin_num) 913 return; 914 915 if (pin >= GPIO_PINS_PER_REG) { 916 reg = GPIO_HI_INT_EDGE_MASK; 917 pin -= GPIO_PINS_PER_REG; 918 } else 919 reg = GPIO_INT_EDGE_MASK; 920 921 if (enable) 922 mv_gpio_reg_set(reg, pin); 923 else 924 mv_gpio_reg_clear(reg, pin); 925 } 926 927 static void 928 mv_gpio_int_ack(uint32_t pin) 929 { 930 uint32_t reg; 931 932 if (pin >= mv_gpio_softc->pin_num) 933 return; 934 935 if (pin >= GPIO_PINS_PER_REG) { 936 reg = GPIO_HI_INT_CAUSE; 937 pin -= GPIO_PINS_PER_REG; 938 } else 939 reg = GPIO_INT_CAUSE; 940 941 mv_gpio_reg_clear(reg, pin); 942 } 943 944 static uint32_t 945 mv_gpio_value_get(uint32_t pin, uint8_t exclude_polar) 946 { 947 uint32_t reg, polar_reg, reg_val, polar_reg_val; 948 949 if (pin >= mv_gpio_softc->pin_num) 950 return (0); 951 952 if (pin >= GPIO_PINS_PER_REG) { 953 reg = GPIO_HI_DATA_IN; 954 pin -= GPIO_PINS_PER_REG; 955 polar_reg = GPIO_HI_DATA_IN_POLAR; 956 } else { 957 reg = GPIO_DATA_IN; 958 polar_reg = GPIO_DATA_IN_POLAR; 959 } 960 961 reg_val = mv_gpio_reg_read(reg); 962 963 if (exclude_polar) { 964 polar_reg_val = mv_gpio_reg_read(polar_reg); 965 return ((reg_val & GPIO(pin)) ^ (polar_reg_val & GPIO(pin))); 966 } else 967 return (reg_val & GPIO(pin)); 968 } 969 970 static void 971 mv_gpio_value_set(uint32_t pin, uint8_t val) 972 { 973 uint32_t reg; 974 975 if (pin >= mv_gpio_softc->pin_num) 976 return; 977 978 if (pin >= GPIO_PINS_PER_REG) { 979 reg = GPIO_HI_DATA_OUT; 980 pin -= GPIO_PINS_PER_REG; 981 } else 982 reg = GPIO_DATA_OUT; 983 984 if (val) 985 mv_gpio_reg_set(reg, pin); 986 else 987 mv_gpio_reg_clear(reg, pin); 988 } 989 990 static int 991 mv_handle_gpios_prop(phandle_t ctrl, pcell_t *gpios, int len) 992 { 993 pcell_t gpio_cells, pincnt; 994 int inc, t, tuples, tuple_size; 995 int dir, flags, pin; 996 u_long gpio_ctrl, size; 997 struct mv_gpio_softc sc; 998 999 pincnt = 0; 1000 if (!OF_hasprop(ctrl, "gpio-controller")) 1001 /* Node is not a GPIO controller. */ 1002 return (ENXIO); 1003 1004 if (OF_getencprop(ctrl, "#gpio-cells", &gpio_cells, sizeof(pcell_t)) < 0) 1005 return (ENXIO); 1006 if (gpio_cells != 3) 1007 return (ENXIO); 1008 1009 tuple_size = gpio_cells * sizeof(pcell_t) + sizeof(phandle_t); 1010 tuples = len / tuple_size; 1011 1012 if (fdt_regsize(ctrl, &gpio_ctrl, &size)) 1013 return (ENXIO); 1014 1015 if (OF_getencprop(ctrl, "pin-count", &pincnt, sizeof(pcell_t)) < 0) 1016 return (ENXIO); 1017 sc.pin_num = pincnt; 1018 1019 /* 1020 * Skip controller reference, since controller's phandle is given 1021 * explicitly (in a function argument). 1022 */ 1023 inc = sizeof(ihandle_t) / sizeof(pcell_t); 1024 gpios += inc; 1025 1026 for (t = 0; t < tuples; t++) { 1027 pin = gpios[0]; 1028 dir = gpios[1]; 1029 flags = gpios[2]; 1030 1031 mv_gpio_configure(pin, flags, ~0); 1032 1033 if (dir == 1) 1034 /* Input. */ 1035 mv_gpio_out_en(pin, 0); 1036 else { 1037 /* Output. */ 1038 if (flags & MV_GPIO_OUT_OPEN_DRAIN) 1039 mv_gpio_out(pin, 0, 1); 1040 1041 if (flags & MV_GPIO_OUT_OPEN_SRC) 1042 mv_gpio_out(pin, 1, 1); 1043 } 1044 gpios += gpio_cells + inc; 1045 } 1046 1047 return (0); 1048 } 1049 1050 #define MAX_PINS_PER_NODE 5 1051 #define GPIOS_PROP_CELLS 4 1052 static int 1053 mv_gpio_init(void) 1054 { 1055 phandle_t child, parent, root, ctrl; 1056 pcell_t gpios[MAX_PINS_PER_NODE * GPIOS_PROP_CELLS]; 1057 struct gpio_ctrl_entry *e; 1058 int len, rv; 1059 1060 root = OF_finddevice("/"); 1061 len = 0; 1062 parent = root; 1063 1064 /* Traverse through entire tree to find nodes with 'gpios' prop */ 1065 for (child = OF_child(parent); child != 0; child = OF_peer(child)) { 1066 1067 /* Find a 'leaf'. Start the search from this node. */ 1068 while (OF_child(child)) { 1069 parent = child; 1070 child = OF_child(child); 1071 } 1072 if ((len = OF_getproplen(child, "gpios")) > 0) { 1073 1074 if (len > sizeof(gpios)) 1075 return (ENXIO); 1076 1077 /* Get 'gpios' property. */ 1078 OF_getencprop(child, "gpios", gpios, len); 1079 1080 e = (struct gpio_ctrl_entry *)&gpio_controllers; 1081 1082 /* Find and call a handler. */ 1083 for (; e->compat; e++) { 1084 /* 1085 * First cell of 'gpios' property should 1086 * contain a ref. to a node defining GPIO 1087 * controller. 1088 */ 1089 ctrl = OF_node_from_xref(gpios[0]); 1090 1091 if (ofw_bus_node_is_compatible(ctrl, e->compat)) 1092 /* Call a handler. */ 1093 if ((rv = e->handler(ctrl, 1094 (pcell_t *)&gpios, len))) 1095 return (rv); 1096 } 1097 } 1098 1099 if (OF_peer(child) == 0) { 1100 /* No more siblings. */ 1101 child = parent; 1102 parent = OF_parent(child); 1103 } 1104 } 1105 return (0); 1106 } 1107